1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * machdep.c
38 *
39 * Machine dependant functions for kernel setup
40 *
41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46#include <sys/cdefs.h>
47__FBSDID("$FreeBSD: stable/10/sys/arm/at91/at91_machdep.c 266311 2014-05-17 13:53:38Z ian $");
48
49#define _ARM32_BUS_DMA_PRIVATE
50#include <sys/param.h>
51#include <sys/systm.h>
52#include <sys/sysproto.h>
53#include <sys/signalvar.h>
54#include <sys/imgact.h>
55#include <sys/kernel.h>
56#include <sys/ktr.h>
57#include <sys/linker.h>
58#include <sys/lock.h>
59#include <sys/malloc.h>
60#include <sys/mutex.h>
61#include <sys/pcpu.h>
62#include <sys/proc.h>
63#include <sys/ptrace.h>
64#include <sys/cons.h>
65#include <sys/bio.h>
66#include <sys/bus.h>
67#include <sys/buf.h>
68#include <sys/exec.h>
69#include <sys/kdb.h>
70#include <sys/msgbuf.h>
71#include <machine/physmem.h>
72#include <machine/reg.h>
73#include <machine/cpu.h>
74#include <machine/board.h>
75
76#include <vm/vm.h>
77#include <vm/pmap.h>
78#include <vm/vm_object.h>
79#include <vm/vm_page.h>
80#include <vm/vm_map.h>
81#include <machine/devmap.h>
82#include <machine/vmparam.h>
83#include <machine/pcb.h>
84#include <machine/undefined.h>
85#include <machine/machdep.h>
86#include <machine/metadata.h>
87#include <machine/armreg.h>
88#include <machine/bus.h>
89#include <sys/reboot.h>
90
91#include <arm/at91/at91board.h>
92#include <arm/at91/at91var.h>
93#include <arm/at91/at91soc.h>
94#include <arm/at91/at91_usartreg.h>
95#include <arm/at91/at91rm92reg.h>
96#include <arm/at91/at91sam9g20reg.h>
97#include <arm/at91/at91sam9g45reg.h>
98
99#ifndef MAXCPU
100#define MAXCPU 1
101#endif
102
103/* Page table for mapping proc0 zero page */
104#define KERNEL_PT_SYS 0
105#define KERNEL_PT_KERN 1
106#define KERNEL_PT_KERN_NUM 22
107/* L2 table for mapping after kernel */
108#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM
109#define KERNEL_PT_AFKERNEL_NUM 5
110
111/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
112#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
113
114struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
115
116/* Static device mappings. */
117const struct arm_devmap_entry at91_devmap[] = {
118 /*
119 * Map the critical on-board devices. The interrupt vector at
120 * 0xffff0000 makes it impossible to map them PA == VA, so we map all
121 * 0xfffxxxxx addresses to 0xdffxxxxx. This covers all critical devices
122 * on all members of the AT91SAM9 and AT91RM9200 families.
123 */
124 {
125 0xdff00000,
126 0xfff00000,
127 0x00100000,
128 VM_PROT_READ|VM_PROT_WRITE,
129 PTE_NOCACHE,
130 },
131 /* There's a notion that we should do the rest of these lazily. */
132 /*
133 * We can't just map the OHCI registers VA == PA, because
134 * AT91xx_xxx_BASE belongs to the userland address space.
135 * We could just choose a different virtual address, but a better
136 * solution would probably be to just use pmap_mapdev() to allocate
137 * KVA, as we don't need the OHCI controller before the vm
138 * initialization is done. However, the AT91 resource allocation
139 * system doesn't know how to use pmap_mapdev() yet.
140 * Care must be taken to ensure PA and VM address do not overlap
141 * between entries.
142 */
143 {
144 /*
145 * Add the ohci controller, and anything else that might be
146 * on this chip select for a VA/PA mapping.
147 */
148 /* Internal Memory 1MB */
149 AT91RM92_OHCI_VA_BASE,
150 AT91RM92_OHCI_BASE,
151 0x00100000,
152 VM_PROT_READ|VM_PROT_WRITE,
153 PTE_NOCACHE,
154 },
155 {
156 /* CompactFlash controller. Portion of EBI CS4 1MB */
157 AT91RM92_CF_VA_BASE,
158 AT91RM92_CF_BASE,
159 0x00100000,
160 VM_PROT_READ|VM_PROT_WRITE,
161 PTE_NOCACHE,
162 },
163 /*
164 * The next two should be good for the 9260, 9261 and 9G20 since
165 * addresses mapping is the same.
166 */
167 {
168 /* Internal Memory 1MB */
169 AT91SAM9G20_OHCI_VA_BASE,
170 AT91SAM9G20_OHCI_BASE,
171 0x00100000,
172 VM_PROT_READ|VM_PROT_WRITE,
173 PTE_NOCACHE,
174 },
175 {
176 /* EBI CS3 256MB */
177 AT91SAM9G20_NAND_VA_BASE,
178 AT91SAM9G20_NAND_BASE,
179 AT91SAM9G20_NAND_SIZE,
180 VM_PROT_READ|VM_PROT_WRITE,
181 PTE_NOCACHE,
182 },
183 /*
184 * The next should be good for the 9G45.
185 */
186 {
187 /* Internal Memory 1MB */
188 AT91SAM9G45_OHCI_VA_BASE,
189 AT91SAM9G45_OHCI_BASE,
190 0x00100000,
191 VM_PROT_READ|VM_PROT_WRITE,
192 PTE_NOCACHE,
193 },
194 { 0, 0, 0, 0, 0, }
195};
196
197/* Physical and virtual addresses for some global pages */
198
199struct pv_addr systempage;
200struct pv_addr msgbufpv;
201struct pv_addr irqstack;
202struct pv_addr undstack;
203struct pv_addr abtstack;
204struct pv_addr kernelstack;
205
206#ifdef LINUX_BOOT_ABI
207extern int membanks;
208extern int memstart[];
209extern int memsize[];
210#endif
211
212long
213at91_ramsize(void)
214{
215 uint32_t cr, mdr, mr, *SDRAMC;
216 int banks, rows, cols, bw;
217#ifdef LINUX_BOOT_ABI
218 /*
219 * If we found any ATAGs that were for memory, return the first bank.
220 */
221 if (membanks > 0)
222 return (memsize[0]);
223#endif
224
225 if (at91_is_rm92()) {
226 SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
227 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
228 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
229 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
230 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
231 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
232 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
233 } else if (at91_cpu_is(AT91_T_SAM9G45)) {
234 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G45_DDRSDRC0_BASE);
235 cr = SDRAMC[AT91SAM9G45_DDRSDRC_CR / 4];
236 mdr = SDRAMC[AT91SAM9G45_DDRSDRC_MDR / 4];
237 banks = 0;
238 rows = ((cr & AT91SAM9G45_DDRSDRC_CR_NR_MASK) >> 2) + 11;
239 cols = (cr & AT91SAM9G45_DDRSDRC_CR_NC_MASK) + 8;
240 bw = (mdr & AT91SAM9G45_DDRSDRC_MDR_DBW_16) ? 1 : 2;
241
242 /* Fix the calculation for DDR memory */
243 mdr &= AT91SAM9G45_DDRSDRC_MDR_MASK;
244 if (mdr & AT91SAM9G45_DDRSDRC_MDR_LPDDR1 ||
245 mdr & AT91SAM9G45_DDRSDRC_MDR_DDR2) {
246 /* The cols value is 1 higher for DDR */
247 cols += 1;
248 /* DDR has 4 internal banks. */
249 banks = 2;
250 }
251 } else {
252 /*
253 * This should be good for the 9260, 9261, 9G20, 9G35 and 9X25
254 * as addresses and registers are the same.
255 */
256 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
257 cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
258 mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];
259 banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1;
260 rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
261 cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
262 bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
263 }
264
265 return (1 << (cols + rows + banks + bw));
266}
267
268static const char *soc_type_name[] = {
269 [AT91_T_CAP9] = "at91cap9",
270 [AT91_T_RM9200] = "at91rm9200",
271 [AT91_T_SAM9260] = "at91sam9260",
272 [AT91_T_SAM9261] = "at91sam9261",
273 [AT91_T_SAM9263] = "at91sam9263",
274 [AT91_T_SAM9G10] = "at91sam9g10",
275 [AT91_T_SAM9G20] = "at91sam9g20",
276 [AT91_T_SAM9G45] = "at91sam9g45",
277 [AT91_T_SAM9N12] = "at91sam9n12",
278 [AT91_T_SAM9RL] = "at91sam9rl",
279 [AT91_T_SAM9X5] = "at91sam9x5",
280 [AT91_T_NONE] = "UNKNOWN"
281};
282
283static const char *soc_subtype_name[] = {
284 [AT91_ST_NONE] = "UNKNOWN",
285 [AT91_ST_RM9200_BGA] = "at91rm9200_bga",
286 [AT91_ST_RM9200_PQFP] = "at91rm9200_pqfp",
287 [AT91_ST_SAM9XE] = "at91sam9xe",
288 [AT91_ST_SAM9G45] = "at91sam9g45",
289 [AT91_ST_SAM9M10] = "at91sam9m10",
290 [AT91_ST_SAM9G46] = "at91sam9g46",
291 [AT91_ST_SAM9M11] = "at91sam9m11",
292 [AT91_ST_SAM9G15] = "at91sam9g15",
293 [AT91_ST_SAM9G25] = "at91sam9g25",
294 [AT91_ST_SAM9G35] = "at91sam9g35",
295 [AT91_ST_SAM9X25] = "at91sam9x25",
296 [AT91_ST_SAM9X35] = "at91sam9x35",
297};
298
299struct at91_soc_info soc_info;
300
301/*
302 * Read the SoC ID from the CIDR register and try to match it against the
303 * values we know. If we find a good one, we return true. If not, we
304 * return false. When we find a good one, we also find the subtype
305 * and CPU family.
306 */
307static int
308at91_try_id(uint32_t dbgu_base)
309{
310 uint32_t socid;
311
312 soc_info.cidr = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
313 DBGU_C1R);
314 socid = soc_info.cidr & ~AT91_CPU_VERSION_MASK;
315
316 soc_info.type = AT91_T_NONE;
317 soc_info.subtype = AT91_ST_NONE;
318 soc_info.family = (soc_info.cidr & AT91_CPU_FAMILY_MASK) >> 20;
319 soc_info.exid = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
320 DBGU_C2R);
321
322 switch (socid) {
323 case AT91_CPU_CAP9:
324 soc_info.type = AT91_T_CAP9;
325 break;
326 case AT91_CPU_RM9200:
327 soc_info.type = AT91_T_RM9200;
328 break;
329 case AT91_CPU_SAM9XE128:
330 case AT91_CPU_SAM9XE256:
331 case AT91_CPU_SAM9XE512:
332 case AT91_CPU_SAM9260:
333 soc_info.type = AT91_T_SAM9260;
334 if (soc_info.family == AT91_FAMILY_SAM9XE)
335 soc_info.subtype = AT91_ST_SAM9XE;
336 break;
337 case AT91_CPU_SAM9261:
338 soc_info.type = AT91_T_SAM9261;
339 break;
340 case AT91_CPU_SAM9263:
341 soc_info.type = AT91_T_SAM9263;
342 break;
343 case AT91_CPU_SAM9G10:
344 soc_info.type = AT91_T_SAM9G10;
345 break;
346 case AT91_CPU_SAM9G20:
347 soc_info.type = AT91_T_SAM9G20;
348 break;
349 case AT91_CPU_SAM9G45:
350 soc_info.type = AT91_T_SAM9G45;
351 break;
352 case AT91_CPU_SAM9N12:
353 soc_info.type = AT91_T_SAM9N12;
354 break;
355 case AT91_CPU_SAM9RL64:
356 soc_info.type = AT91_T_SAM9RL;
357 break;
358 case AT91_CPU_SAM9X5:
359 soc_info.type = AT91_T_SAM9X5;
360 break;
361 default:
362 return (0);
363 }
364
365 switch (soc_info.type) {
366 case AT91_T_SAM9G45:
367 switch (soc_info.exid) {
368 case AT91_EXID_SAM9G45:
369 soc_info.subtype = AT91_ST_SAM9G45;
370 break;
371 case AT91_EXID_SAM9G46:
372 soc_info.subtype = AT91_ST_SAM9G46;
373 break;
374 case AT91_EXID_SAM9M10:
375 soc_info.subtype = AT91_ST_SAM9M10;
376 break;
377 case AT91_EXID_SAM9M11:
378 soc_info.subtype = AT91_ST_SAM9M11;
379 break;
380 }
381 break;
382 case AT91_T_SAM9X5:
383 switch (soc_info.exid) {
384 case AT91_EXID_SAM9G15:
385 soc_info.subtype = AT91_ST_SAM9G15;
386 break;
387 case AT91_EXID_SAM9G25:
388 soc_info.subtype = AT91_ST_SAM9G25;
389 break;
390 case AT91_EXID_SAM9G35:
391 soc_info.subtype = AT91_ST_SAM9G35;
392 break;
393 case AT91_EXID_SAM9X25:
394 soc_info.subtype = AT91_ST_SAM9X25;
395 break;
396 case AT91_EXID_SAM9X35:
397 soc_info.subtype = AT91_ST_SAM9X35;
398 break;
399 }
400 break;
401 default:
402 break;
403 }
404 /*
405 * Disable interrupts in the DBGU unit...
406 */
407 *(volatile uint32_t *)(AT91_BASE + dbgu_base + USART_IDR) = 0xffffffff;
408
409 /*
410 * Save the name for later...
411 */
412 snprintf(soc_info.name, sizeof(soc_info.name), "%s%s%s",
413 soc_type_name[soc_info.type],
414 soc_info.subtype == AT91_ST_NONE ? "" : " subtype ",
415 soc_info.subtype == AT91_ST_NONE ? "" :
416 soc_subtype_name[soc_info.subtype]);
417
418 /*
419 * try to get the matching CPU support.
420 */
421 soc_info.soc_data = at91_match_soc(soc_info.type, soc_info.subtype);
422 soc_info.dbgu_base = AT91_BASE + dbgu_base;
423
424 return (1);
425}
426
427static void
428at91_soc_id(void)
429{
430
431 if (!at91_try_id(AT91_DBGU0))
432 at91_try_id(AT91_DBGU1);
433}
434
435#ifdef ARM_MANY_BOARD
436/* likely belongs in arm/arm/machdep.c, but since board_init is still at91 only... */
437SET_DECLARE(arm_board_set, const struct arm_board);
438
439/* Not yet fully functional, but enough to build ATMEL config */
440static long
441board_init(void)
442{
443 return -1;
444}
445#endif
446
447void *
448initarm(struct arm_boot_params *abp)
449{
450 struct pv_addr kernel_l1pt;
451 struct pv_addr dpcpu;
452 int i;
453 u_int l1pagetable;
454 vm_offset_t freemempos;
455 vm_offset_t afterkern;
456 uint32_t memsize;
457 vm_offset_t lastaddr;
458
459 lastaddr = parse_boot_param(abp);
460 arm_physmem_kernaddr = abp->abp_physaddr;
461 set_cpufuncs();
462 pcpu0_init();
463
464 /* Do basic tuning, hz etc */
465 init_param1();
466
467 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
468 /* Define a macro to simplify memory allocation */
469#define valloc_pages(var, np) \
470 alloc_pages((var).pv_va, (np)); \
471 (var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR);
472
473#define alloc_pages(var, np) \
474 (var) = freemempos; \
475 freemempos += (np * PAGE_SIZE); \
476 memset((char *)(var), 0, ((np) * PAGE_SIZE));
477
478 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
479 freemempos += PAGE_SIZE;
480 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
481 for (i = 0; i < NUM_KERNEL_PTS; ++i) {
482 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
483 valloc_pages(kernel_pt_table[i],
484 L2_TABLE_SIZE / PAGE_SIZE);
485 } else {
486 kernel_pt_table[i].pv_va = freemempos -
487 (i % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
488 L2_TABLE_SIZE_REAL;
489 kernel_pt_table[i].pv_pa =
490 kernel_pt_table[i].pv_va - KERNVIRTADDR +
491 abp->abp_physaddr;
492 }
493 }
494 /*
495 * Allocate a page for the system page mapped to 0x00000000
496 * or 0xffff0000. This page will just contain the system vectors
497 * and can be shared by all processes.
498 */
499 valloc_pages(systempage, 1);
500
501 /* Allocate dynamic per-cpu area. */
502 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
503 dpcpu_init((void *)dpcpu.pv_va, 0);
504
505 /* Allocate stacks for all modes */
506 valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU);
507 valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU);
508 valloc_pages(undstack, UND_STACK_SIZE * MAXCPU);
509 valloc_pages(kernelstack, KSTACK_PAGES * MAXCPU);
510 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
511
512 /*
513 * Now we start construction of the L1 page table
514 * We start by mapping the L2 page tables into the L1.
515 * This means that we can replace L1 mappings later on if necessary
516 */
517 l1pagetable = kernel_l1pt.pv_va;
518
519 /* Map the L2 pages tables in the L1 page table */
520 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
521 &kernel_pt_table[KERNEL_PT_SYS]);
522 for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
523 pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
524 &kernel_pt_table[KERNEL_PT_KERN + i]);
525 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
526 (((uint32_t)lastaddr - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
527 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
528 afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1));
529 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
530 pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
531 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
532 }
533
534 /* Map the vector page. */
535 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
536 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
537
538 /* Map the DPCPU pages */
539 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE,
540 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
541
542 /* Map the stack pages */
543 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
544 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
545 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
546 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
547 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
548 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
549 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
550 KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
551
552 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
553 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
554 pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
555 msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
556
557 for (i = 0; i < NUM_KERNEL_PTS; ++i) {
558 pmap_map_chunk(l1pagetable, kernel_pt_table[i].pv_va,
559 kernel_pt_table[i].pv_pa, L2_TABLE_SIZE,
560 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
561 }
562
563 arm_devmap_bootstrap(l1pagetable, at91_devmap);
564 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT);
565 setttb(kernel_l1pt.pv_pa);
566 cpu_tlb_flushID();
567 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
568
569 at91_soc_id();
570
571 /*
572 * Initialize all the clocks, so that the console can work. We can only
573 * do this if at91_soc_id() was able to fill in the support data. Even
574 * if we can't init the clocks, still try to do a console init so we can
575 * try to print the error message about missing soc support. There's a
576 * chance the printf will work if the bootloader set up the DBGU.
577 */
578 if (soc_info.soc_data != NULL) {
579 soc_info.soc_data->soc_clock_init();
580 at91_pmc_init_clock();
581 }
582
583 cninit();
584
585 if (soc_info.soc_data == NULL)
586 printf("Warning: No soc support for %s found.\n", soc_info.name);
587
588 memsize = board_init();
589 if (memsize == -1) {
590 printf("board_init() failed, cannot determine ram size; "
591 "assuming 16MB\n");
592 memsize = 16 * 1024 * 1024;
593 }
594
595 /*
596 * Pages were allocated during the secondary bootstrap for the
597 * stacks for different CPU modes.
598 * We must now set the r13 registers in the different CPU modes to
599 * point to these stacks.
600 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
601 * of the stack memory.
602 */
603 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
604 cpu_setup("");
605
606 set_stackptrs(0);
607
608 /*
609 * We must now clean the cache again....
610 * Cleaning may be done by reading new data to displace any
611 * dirty data in the cache. This will have happened in setttb()
612 * but since we are boot strapping the addresses used for the read
613 * may have just been remapped and thus the cache could be out
614 * of sync. A re-clean after the switch will cure this.
615 * After booting there are no gross relocations of the kernel thus
616 * this problem will not occur after initarm().
617 */
618 cpu_idcache_wbinv_all();
619
620 undefined_init();
621
622 init_proc0(kernelstack.pv_va);
623
624 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
625
626 pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1);
627 /* Always use the 256MB of KVA we have available between the kernel and devices */
628 vm_max_kernel_address = KERNVIRTADDR + (256 << 20);
629 pmap_bootstrap(freemempos, &kernel_l1pt);
630 msgbufp = (void*)msgbufpv.pv_va;
631 msgbufinit(msgbufp, msgbufsize);
632 mutex_init();
633
634 /*
635 * Add the physical ram we have available.
636 *
637 * Exclude the kernel, and all the things we allocated which immediately
638 * follow the kernel, from the VM allocation pool but not from crash
639 * dumps. virtual_avail is a global variable which tracks the kva we've
640 * "allocated" while setting up pmaps.
641 *
642 * Prepare the list of physical memory available to the vm subsystem.
643 */
644 arm_physmem_hardware_region(PHYSADDR, memsize);
645 arm_physmem_exclude_region(abp->abp_physaddr,
646 virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
647 arm_physmem_init_kernel_globals();
648
649 init_param2(physmem);
650 kdb_init();
651 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
652 sizeof(struct pcb)));
653}
654
655/*
656 * These functions are handled elsewhere, so make them nops here.
657 */
658void
659cpu_startprofclock(void)
660{
661
662}
663
664void
665cpu_stopprofclock(void)
666{
667
668}
669
670void
671cpu_initclocks(void)
672{
673
674}
675
676void
677DELAY(int n)
678{
679
680 if (soc_info.soc_data)
681 soc_info.soc_data->soc_delay(n);
682}
683
684void
685cpu_reset(void)
686{
687
688 if (soc_info.soc_data)
689 soc_info.soc_data->soc_reset();
690 while (1)
691 continue;
692}
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * machdep.c
38 *
39 * Machine dependant functions for kernel setup
40 *
41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46#include <sys/cdefs.h>
47__FBSDID("$FreeBSD: stable/10/sys/arm/at91/at91_machdep.c 266311 2014-05-17 13:53:38Z ian $");
48
49#define _ARM32_BUS_DMA_PRIVATE
50#include <sys/param.h>
51#include <sys/systm.h>
52#include <sys/sysproto.h>
53#include <sys/signalvar.h>
54#include <sys/imgact.h>
55#include <sys/kernel.h>
56#include <sys/ktr.h>
57#include <sys/linker.h>
58#include <sys/lock.h>
59#include <sys/malloc.h>
60#include <sys/mutex.h>
61#include <sys/pcpu.h>
62#include <sys/proc.h>
63#include <sys/ptrace.h>
64#include <sys/cons.h>
65#include <sys/bio.h>
66#include <sys/bus.h>
67#include <sys/buf.h>
68#include <sys/exec.h>
69#include <sys/kdb.h>
70#include <sys/msgbuf.h>
71#include <machine/physmem.h>
72#include <machine/reg.h>
73#include <machine/cpu.h>
74#include <machine/board.h>
75
76#include <vm/vm.h>
77#include <vm/pmap.h>
78#include <vm/vm_object.h>
79#include <vm/vm_page.h>
80#include <vm/vm_map.h>
81#include <machine/devmap.h>
82#include <machine/vmparam.h>
83#include <machine/pcb.h>
84#include <machine/undefined.h>
85#include <machine/machdep.h>
86#include <machine/metadata.h>
87#include <machine/armreg.h>
88#include <machine/bus.h>
89#include <sys/reboot.h>
90
91#include <arm/at91/at91board.h>
92#include <arm/at91/at91var.h>
93#include <arm/at91/at91soc.h>
94#include <arm/at91/at91_usartreg.h>
95#include <arm/at91/at91rm92reg.h>
96#include <arm/at91/at91sam9g20reg.h>
97#include <arm/at91/at91sam9g45reg.h>
98
99#ifndef MAXCPU
100#define MAXCPU 1
101#endif
102
103/* Page table for mapping proc0 zero page */
104#define KERNEL_PT_SYS 0
105#define KERNEL_PT_KERN 1
106#define KERNEL_PT_KERN_NUM 22
107/* L2 table for mapping after kernel */
108#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM
109#define KERNEL_PT_AFKERNEL_NUM 5
110
111/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
112#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
113
114struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
115
116/* Static device mappings. */
117const struct arm_devmap_entry at91_devmap[] = {
118 /*
119 * Map the critical on-board devices. The interrupt vector at
120 * 0xffff0000 makes it impossible to map them PA == VA, so we map all
121 * 0xfffxxxxx addresses to 0xdffxxxxx. This covers all critical devices
122 * on all members of the AT91SAM9 and AT91RM9200 families.
123 */
124 {
125 0xdff00000,
126 0xfff00000,
127 0x00100000,
128 VM_PROT_READ|VM_PROT_WRITE,
129 PTE_NOCACHE,
130 },
131 /* There's a notion that we should do the rest of these lazily. */
132 /*
133 * We can't just map the OHCI registers VA == PA, because
134 * AT91xx_xxx_BASE belongs to the userland address space.
135 * We could just choose a different virtual address, but a better
136 * solution would probably be to just use pmap_mapdev() to allocate
137 * KVA, as we don't need the OHCI controller before the vm
138 * initialization is done. However, the AT91 resource allocation
139 * system doesn't know how to use pmap_mapdev() yet.
140 * Care must be taken to ensure PA and VM address do not overlap
141 * between entries.
142 */
143 {
144 /*
145 * Add the ohci controller, and anything else that might be
146 * on this chip select for a VA/PA mapping.
147 */
148 /* Internal Memory 1MB */
149 AT91RM92_OHCI_VA_BASE,
150 AT91RM92_OHCI_BASE,
151 0x00100000,
152 VM_PROT_READ|VM_PROT_WRITE,
153 PTE_NOCACHE,
154 },
155 {
156 /* CompactFlash controller. Portion of EBI CS4 1MB */
157 AT91RM92_CF_VA_BASE,
158 AT91RM92_CF_BASE,
159 0x00100000,
160 VM_PROT_READ|VM_PROT_WRITE,
161 PTE_NOCACHE,
162 },
163 /*
164 * The next two should be good for the 9260, 9261 and 9G20 since
165 * addresses mapping is the same.
166 */
167 {
168 /* Internal Memory 1MB */
169 AT91SAM9G20_OHCI_VA_BASE,
170 AT91SAM9G20_OHCI_BASE,
171 0x00100000,
172 VM_PROT_READ|VM_PROT_WRITE,
173 PTE_NOCACHE,
174 },
175 {
176 /* EBI CS3 256MB */
177 AT91SAM9G20_NAND_VA_BASE,
178 AT91SAM9G20_NAND_BASE,
179 AT91SAM9G20_NAND_SIZE,
180 VM_PROT_READ|VM_PROT_WRITE,
181 PTE_NOCACHE,
182 },
183 /*
184 * The next should be good for the 9G45.
185 */
186 {
187 /* Internal Memory 1MB */
188 AT91SAM9G45_OHCI_VA_BASE,
189 AT91SAM9G45_OHCI_BASE,
190 0x00100000,
191 VM_PROT_READ|VM_PROT_WRITE,
192 PTE_NOCACHE,
193 },
194 { 0, 0, 0, 0, 0, }
195};
196
197/* Physical and virtual addresses for some global pages */
198
199struct pv_addr systempage;
200struct pv_addr msgbufpv;
201struct pv_addr irqstack;
202struct pv_addr undstack;
203struct pv_addr abtstack;
204struct pv_addr kernelstack;
205
206#ifdef LINUX_BOOT_ABI
207extern int membanks;
208extern int memstart[];
209extern int memsize[];
210#endif
211
212long
213at91_ramsize(void)
214{
215 uint32_t cr, mdr, mr, *SDRAMC;
216 int banks, rows, cols, bw;
217#ifdef LINUX_BOOT_ABI
218 /*
219 * If we found any ATAGs that were for memory, return the first bank.
220 */
221 if (membanks > 0)
222 return (memsize[0]);
223#endif
224
225 if (at91_is_rm92()) {
226 SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
227 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
228 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
229 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
230 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
231 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
232 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
233 } else if (at91_cpu_is(AT91_T_SAM9G45)) {
234 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G45_DDRSDRC0_BASE);
235 cr = SDRAMC[AT91SAM9G45_DDRSDRC_CR / 4];
236 mdr = SDRAMC[AT91SAM9G45_DDRSDRC_MDR / 4];
237 banks = 0;
238 rows = ((cr & AT91SAM9G45_DDRSDRC_CR_NR_MASK) >> 2) + 11;
239 cols = (cr & AT91SAM9G45_DDRSDRC_CR_NC_MASK) + 8;
240 bw = (mdr & AT91SAM9G45_DDRSDRC_MDR_DBW_16) ? 1 : 2;
241
242 /* Fix the calculation for DDR memory */
243 mdr &= AT91SAM9G45_DDRSDRC_MDR_MASK;
244 if (mdr & AT91SAM9G45_DDRSDRC_MDR_LPDDR1 ||
245 mdr & AT91SAM9G45_DDRSDRC_MDR_DDR2) {
246 /* The cols value is 1 higher for DDR */
247 cols += 1;
248 /* DDR has 4 internal banks. */
249 banks = 2;
250 }
251 } else {
252 /*
253 * This should be good for the 9260, 9261, 9G20, 9G35 and 9X25
254 * as addresses and registers are the same.
255 */
256 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
257 cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
258 mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];
259 banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1;
260 rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
261 cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
262 bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
263 }
264
265 return (1 << (cols + rows + banks + bw));
266}
267
268static const char *soc_type_name[] = {
269 [AT91_T_CAP9] = "at91cap9",
270 [AT91_T_RM9200] = "at91rm9200",
271 [AT91_T_SAM9260] = "at91sam9260",
272 [AT91_T_SAM9261] = "at91sam9261",
273 [AT91_T_SAM9263] = "at91sam9263",
274 [AT91_T_SAM9G10] = "at91sam9g10",
275 [AT91_T_SAM9G20] = "at91sam9g20",
276 [AT91_T_SAM9G45] = "at91sam9g45",
277 [AT91_T_SAM9N12] = "at91sam9n12",
278 [AT91_T_SAM9RL] = "at91sam9rl",
279 [AT91_T_SAM9X5] = "at91sam9x5",
280 [AT91_T_NONE] = "UNKNOWN"
281};
282
283static const char *soc_subtype_name[] = {
284 [AT91_ST_NONE] = "UNKNOWN",
285 [AT91_ST_RM9200_BGA] = "at91rm9200_bga",
286 [AT91_ST_RM9200_PQFP] = "at91rm9200_pqfp",
287 [AT91_ST_SAM9XE] = "at91sam9xe",
288 [AT91_ST_SAM9G45] = "at91sam9g45",
289 [AT91_ST_SAM9M10] = "at91sam9m10",
290 [AT91_ST_SAM9G46] = "at91sam9g46",
291 [AT91_ST_SAM9M11] = "at91sam9m11",
292 [AT91_ST_SAM9G15] = "at91sam9g15",
293 [AT91_ST_SAM9G25] = "at91sam9g25",
294 [AT91_ST_SAM9G35] = "at91sam9g35",
295 [AT91_ST_SAM9X25] = "at91sam9x25",
296 [AT91_ST_SAM9X35] = "at91sam9x35",
297};
298
299struct at91_soc_info soc_info;
300
301/*
302 * Read the SoC ID from the CIDR register and try to match it against the
303 * values we know. If we find a good one, we return true. If not, we
304 * return false. When we find a good one, we also find the subtype
305 * and CPU family.
306 */
307static int
308at91_try_id(uint32_t dbgu_base)
309{
310 uint32_t socid;
311
312 soc_info.cidr = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
313 DBGU_C1R);
314 socid = soc_info.cidr & ~AT91_CPU_VERSION_MASK;
315
316 soc_info.type = AT91_T_NONE;
317 soc_info.subtype = AT91_ST_NONE;
318 soc_info.family = (soc_info.cidr & AT91_CPU_FAMILY_MASK) >> 20;
319 soc_info.exid = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
320 DBGU_C2R);
321
322 switch (socid) {
323 case AT91_CPU_CAP9:
324 soc_info.type = AT91_T_CAP9;
325 break;
326 case AT91_CPU_RM9200:
327 soc_info.type = AT91_T_RM9200;
328 break;
329 case AT91_CPU_SAM9XE128:
330 case AT91_CPU_SAM9XE256:
331 case AT91_CPU_SAM9XE512:
332 case AT91_CPU_SAM9260:
333 soc_info.type = AT91_T_SAM9260;
334 if (soc_info.family == AT91_FAMILY_SAM9XE)
335 soc_info.subtype = AT91_ST_SAM9XE;
336 break;
337 case AT91_CPU_SAM9261:
338 soc_info.type = AT91_T_SAM9261;
339 break;
340 case AT91_CPU_SAM9263:
341 soc_info.type = AT91_T_SAM9263;
342 break;
343 case AT91_CPU_SAM9G10:
344 soc_info.type = AT91_T_SAM9G10;
345 break;
346 case AT91_CPU_SAM9G20:
347 soc_info.type = AT91_T_SAM9G20;
348 break;
349 case AT91_CPU_SAM9G45:
350 soc_info.type = AT91_T_SAM9G45;
351 break;
352 case AT91_CPU_SAM9N12:
353 soc_info.type = AT91_T_SAM9N12;
354 break;
355 case AT91_CPU_SAM9RL64:
356 soc_info.type = AT91_T_SAM9RL;
357 break;
358 case AT91_CPU_SAM9X5:
359 soc_info.type = AT91_T_SAM9X5;
360 break;
361 default:
362 return (0);
363 }
364
365 switch (soc_info.type) {
366 case AT91_T_SAM9G45:
367 switch (soc_info.exid) {
368 case AT91_EXID_SAM9G45:
369 soc_info.subtype = AT91_ST_SAM9G45;
370 break;
371 case AT91_EXID_SAM9G46:
372 soc_info.subtype = AT91_ST_SAM9G46;
373 break;
374 case AT91_EXID_SAM9M10:
375 soc_info.subtype = AT91_ST_SAM9M10;
376 break;
377 case AT91_EXID_SAM9M11:
378 soc_info.subtype = AT91_ST_SAM9M11;
379 break;
380 }
381 break;
382 case AT91_T_SAM9X5:
383 switch (soc_info.exid) {
384 case AT91_EXID_SAM9G15:
385 soc_info.subtype = AT91_ST_SAM9G15;
386 break;
387 case AT91_EXID_SAM9G25:
388 soc_info.subtype = AT91_ST_SAM9G25;
389 break;
390 case AT91_EXID_SAM9G35:
391 soc_info.subtype = AT91_ST_SAM9G35;
392 break;
393 case AT91_EXID_SAM9X25:
394 soc_info.subtype = AT91_ST_SAM9X25;
395 break;
396 case AT91_EXID_SAM9X35:
397 soc_info.subtype = AT91_ST_SAM9X35;
398 break;
399 }
400 break;
401 default:
402 break;
403 }
404 /*
405 * Disable interrupts in the DBGU unit...
406 */
407 *(volatile uint32_t *)(AT91_BASE + dbgu_base + USART_IDR) = 0xffffffff;
408
409 /*
410 * Save the name for later...
411 */
412 snprintf(soc_info.name, sizeof(soc_info.name), "%s%s%s",
413 soc_type_name[soc_info.type],
414 soc_info.subtype == AT91_ST_NONE ? "" : " subtype ",
415 soc_info.subtype == AT91_ST_NONE ? "" :
416 soc_subtype_name[soc_info.subtype]);
417
418 /*
419 * try to get the matching CPU support.
420 */
421 soc_info.soc_data = at91_match_soc(soc_info.type, soc_info.subtype);
422 soc_info.dbgu_base = AT91_BASE + dbgu_base;
423
424 return (1);
425}
426
427static void
428at91_soc_id(void)
429{
430
431 if (!at91_try_id(AT91_DBGU0))
432 at91_try_id(AT91_DBGU1);
433}
434
435#ifdef ARM_MANY_BOARD
436/* likely belongs in arm/arm/machdep.c, but since board_init is still at91 only... */
437SET_DECLARE(arm_board_set, const struct arm_board);
438
439/* Not yet fully functional, but enough to build ATMEL config */
440static long
441board_init(void)
442{
443 return -1;
444}
445#endif
446
447void *
448initarm(struct arm_boot_params *abp)
449{
450 struct pv_addr kernel_l1pt;
451 struct pv_addr dpcpu;
452 int i;
453 u_int l1pagetable;
454 vm_offset_t freemempos;
455 vm_offset_t afterkern;
456 uint32_t memsize;
457 vm_offset_t lastaddr;
458
459 lastaddr = parse_boot_param(abp);
460 arm_physmem_kernaddr = abp->abp_physaddr;
461 set_cpufuncs();
462 pcpu0_init();
463
464 /* Do basic tuning, hz etc */
465 init_param1();
466
467 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
468 /* Define a macro to simplify memory allocation */
469#define valloc_pages(var, np) \
470 alloc_pages((var).pv_va, (np)); \
471 (var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR);
472
473#define alloc_pages(var, np) \
474 (var) = freemempos; \
475 freemempos += (np * PAGE_SIZE); \
476 memset((char *)(var), 0, ((np) * PAGE_SIZE));
477
478 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
479 freemempos += PAGE_SIZE;
480 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
481 for (i = 0; i < NUM_KERNEL_PTS; ++i) {
482 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
483 valloc_pages(kernel_pt_table[i],
484 L2_TABLE_SIZE / PAGE_SIZE);
485 } else {
486 kernel_pt_table[i].pv_va = freemempos -
487 (i % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
488 L2_TABLE_SIZE_REAL;
489 kernel_pt_table[i].pv_pa =
490 kernel_pt_table[i].pv_va - KERNVIRTADDR +
491 abp->abp_physaddr;
492 }
493 }
494 /*
495 * Allocate a page for the system page mapped to 0x00000000
496 * or 0xffff0000. This page will just contain the system vectors
497 * and can be shared by all processes.
498 */
499 valloc_pages(systempage, 1);
500
501 /* Allocate dynamic per-cpu area. */
502 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
503 dpcpu_init((void *)dpcpu.pv_va, 0);
504
505 /* Allocate stacks for all modes */
506 valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU);
507 valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU);
508 valloc_pages(undstack, UND_STACK_SIZE * MAXCPU);
509 valloc_pages(kernelstack, KSTACK_PAGES * MAXCPU);
510 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
511
512 /*
513 * Now we start construction of the L1 page table
514 * We start by mapping the L2 page tables into the L1.
515 * This means that we can replace L1 mappings later on if necessary
516 */
517 l1pagetable = kernel_l1pt.pv_va;
518
519 /* Map the L2 pages tables in the L1 page table */
520 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
521 &kernel_pt_table[KERNEL_PT_SYS]);
522 for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
523 pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
524 &kernel_pt_table[KERNEL_PT_KERN + i]);
525 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
526 (((uint32_t)lastaddr - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
527 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
528 afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1));
529 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
530 pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
531 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
532 }
533
534 /* Map the vector page. */
535 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
536 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
537
538 /* Map the DPCPU pages */
539 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE,
540 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
541
542 /* Map the stack pages */
543 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
544 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
545 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
546 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
547 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
548 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
549 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
550 KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
551
552 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
553 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
554 pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
555 msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
556
557 for (i = 0; i < NUM_KERNEL_PTS; ++i) {
558 pmap_map_chunk(l1pagetable, kernel_pt_table[i].pv_va,
559 kernel_pt_table[i].pv_pa, L2_TABLE_SIZE,
560 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
561 }
562
563 arm_devmap_bootstrap(l1pagetable, at91_devmap);
564 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT);
565 setttb(kernel_l1pt.pv_pa);
566 cpu_tlb_flushID();
567 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
568
569 at91_soc_id();
570
571 /*
572 * Initialize all the clocks, so that the console can work. We can only
573 * do this if at91_soc_id() was able to fill in the support data. Even
574 * if we can't init the clocks, still try to do a console init so we can
575 * try to print the error message about missing soc support. There's a
576 * chance the printf will work if the bootloader set up the DBGU.
577 */
578 if (soc_info.soc_data != NULL) {
579 soc_info.soc_data->soc_clock_init();
580 at91_pmc_init_clock();
581 }
582
583 cninit();
584
585 if (soc_info.soc_data == NULL)
586 printf("Warning: No soc support for %s found.\n", soc_info.name);
587
588 memsize = board_init();
589 if (memsize == -1) {
590 printf("board_init() failed, cannot determine ram size; "
591 "assuming 16MB\n");
592 memsize = 16 * 1024 * 1024;
593 }
594
595 /*
596 * Pages were allocated during the secondary bootstrap for the
597 * stacks for different CPU modes.
598 * We must now set the r13 registers in the different CPU modes to
599 * point to these stacks.
600 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
601 * of the stack memory.
602 */
603 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
604 cpu_setup("");
605
606 set_stackptrs(0);
607
608 /*
609 * We must now clean the cache again....
610 * Cleaning may be done by reading new data to displace any
611 * dirty data in the cache. This will have happened in setttb()
612 * but since we are boot strapping the addresses used for the read
613 * may have just been remapped and thus the cache could be out
614 * of sync. A re-clean after the switch will cure this.
615 * After booting there are no gross relocations of the kernel thus
616 * this problem will not occur after initarm().
617 */
618 cpu_idcache_wbinv_all();
619
620 undefined_init();
621
622 init_proc0(kernelstack.pv_va);
623
624 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
625
626 pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1);
627 /* Always use the 256MB of KVA we have available between the kernel and devices */
628 vm_max_kernel_address = KERNVIRTADDR + (256 << 20);
629 pmap_bootstrap(freemempos, &kernel_l1pt);
630 msgbufp = (void*)msgbufpv.pv_va;
631 msgbufinit(msgbufp, msgbufsize);
632 mutex_init();
633
634 /*
635 * Add the physical ram we have available.
636 *
637 * Exclude the kernel, and all the things we allocated which immediately
638 * follow the kernel, from the VM allocation pool but not from crash
639 * dumps. virtual_avail is a global variable which tracks the kva we've
640 * "allocated" while setting up pmaps.
641 *
642 * Prepare the list of physical memory available to the vm subsystem.
643 */
644 arm_physmem_hardware_region(PHYSADDR, memsize);
645 arm_physmem_exclude_region(abp->abp_physaddr,
646 virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
647 arm_physmem_init_kernel_globals();
648
649 init_param2(physmem);
650 kdb_init();
651 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
652 sizeof(struct pcb)));
653}
654
655/*
656 * These functions are handled elsewhere, so make them nops here.
657 */
658void
659cpu_startprofclock(void)
660{
661
662}
663
664void
665cpu_stopprofclock(void)
666{
667
668}
669
670void
671cpu_initclocks(void)
672{
673
674}
675
676void
677DELAY(int n)
678{
679
680 if (soc_info.soc_data)
681 soc_info.soc_data->soc_delay(n);
682}
683
684void
685cpu_reset(void)
686{
687
688 if (soc_info.soc_data)
689 soc_info.soc_data->soc_reset();
690 while (1)
691 continue;
692}