1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
26 * $FreeBSD: stable/10/sys/amd64/include/vmm_dev.h 262350 2014-02-23 00:46:05Z jhb $
| 26 * $FreeBSD: stable/10/sys/amd64/include/vmm_dev.h 267393 2014-06-12 13:13:15Z jhb $
|
27 */
28
29#ifndef _VMM_DEV_H_
30#define _VMM_DEV_H_
31
32#ifdef _KERNEL
33void vmmdev_init(void);
34int vmmdev_cleanup(void);
35#endif
36
37struct vm_memory_segment {
38 vm_paddr_t gpa; /* in */
39 size_t len;
40 int wired;
41};
42
43struct vm_register {
44 int cpuid;
45 int regnum; /* enum vm_reg_name */
46 uint64_t regval;
47};
48
49struct vm_seg_desc { /* data or code segment */
50 int cpuid;
51 int regnum; /* enum vm_reg_name */
52 struct seg_desc desc;
53};
54
55struct vm_run {
56 int cpuid;
57 uint64_t rip; /* start running here */
58 struct vm_exit vm_exit;
59};
60
61struct vm_event {
62 int cpuid;
63 enum vm_event_type type;
64 int vector;
65 uint32_t error_code;
66 int error_code_valid;
67};
68
69struct vm_lapic_msi {
70 uint64_t msg;
71 uint64_t addr;
72};
73
74struct vm_lapic_irq {
75 int cpuid;
76 int vector;
77};
78
79struct vm_ioapic_irq {
80 int irq;
81};
82
83struct vm_capability {
84 int cpuid;
85 enum vm_cap_type captype;
86 int capval;
87 int allcpus;
88};
89
90struct vm_pptdev {
91 int bus;
92 int slot;
93 int func;
94};
95
96struct vm_pptdev_mmio {
97 int bus;
98 int slot;
99 int func;
100 vm_paddr_t gpa;
101 vm_paddr_t hpa;
102 size_t len;
103};
104
105struct vm_pptdev_msi {
106 int vcpu;
107 int bus;
108 int slot;
109 int func;
110 int numvec; /* 0 means disabled */
111 uint64_t msg;
112 uint64_t addr;
113};
114
115struct vm_pptdev_msix {
116 int vcpu;
117 int bus;
118 int slot;
119 int func;
120 int idx;
121 uint64_t msg;
122 uint32_t vector_control;
123 uint64_t addr;
124};
125
126struct vm_nmi {
127 int cpuid;
128};
129
130#define MAX_VM_STATS 64
131struct vm_stats {
132 int cpuid; /* in */
133 int num_entries; /* out */
134 struct timeval tv;
135 uint64_t statbuf[MAX_VM_STATS];
136};
137
138struct vm_stat_desc {
139 int index; /* in */
140 char desc[128]; /* out */
141};
142
143struct vm_x2apic {
144 int cpuid;
145 enum x2apic_state state;
146};
147
148struct vm_gpa_pte {
149 uint64_t gpa; /* in */
150 uint64_t pte[4]; /* out */
151 int ptenum;
152};
153
154struct vm_hpet_cap {
155 uint32_t capabilities; /* lower 32 bits of HPET capabilities */
156};
157
158enum {
159 /* general routines */
160 IOCNUM_ABIVERS = 0,
161 IOCNUM_RUN = 1,
162 IOCNUM_SET_CAPABILITY = 2,
163 IOCNUM_GET_CAPABILITY = 3,
164
165 /* memory apis */
166 IOCNUM_MAP_MEMORY = 10,
167 IOCNUM_GET_MEMORY_SEG = 11,
168 IOCNUM_GET_GPA_PMAP = 12,
169
170 /* register/state accessors */
171 IOCNUM_SET_REGISTER = 20,
172 IOCNUM_GET_REGISTER = 21,
173 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
174 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
175
176 /* interrupt injection */
177 IOCNUM_INJECT_EVENT = 30,
178 IOCNUM_LAPIC_IRQ = 31,
179 IOCNUM_INJECT_NMI = 32,
180 IOCNUM_IOAPIC_ASSERT_IRQ = 33,
181 IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
182 IOCNUM_IOAPIC_PULSE_IRQ = 35,
183 IOCNUM_LAPIC_MSI = 36,
| 27 */
28
29#ifndef _VMM_DEV_H_
30#define _VMM_DEV_H_
31
32#ifdef _KERNEL
33void vmmdev_init(void);
34int vmmdev_cleanup(void);
35#endif
36
37struct vm_memory_segment {
38 vm_paddr_t gpa; /* in */
39 size_t len;
40 int wired;
41};
42
43struct vm_register {
44 int cpuid;
45 int regnum; /* enum vm_reg_name */
46 uint64_t regval;
47};
48
49struct vm_seg_desc { /* data or code segment */
50 int cpuid;
51 int regnum; /* enum vm_reg_name */
52 struct seg_desc desc;
53};
54
55struct vm_run {
56 int cpuid;
57 uint64_t rip; /* start running here */
58 struct vm_exit vm_exit;
59};
60
61struct vm_event {
62 int cpuid;
63 enum vm_event_type type;
64 int vector;
65 uint32_t error_code;
66 int error_code_valid;
67};
68
69struct vm_lapic_msi {
70 uint64_t msg;
71 uint64_t addr;
72};
73
74struct vm_lapic_irq {
75 int cpuid;
76 int vector;
77};
78
79struct vm_ioapic_irq {
80 int irq;
81};
82
83struct vm_capability {
84 int cpuid;
85 enum vm_cap_type captype;
86 int capval;
87 int allcpus;
88};
89
90struct vm_pptdev {
91 int bus;
92 int slot;
93 int func;
94};
95
96struct vm_pptdev_mmio {
97 int bus;
98 int slot;
99 int func;
100 vm_paddr_t gpa;
101 vm_paddr_t hpa;
102 size_t len;
103};
104
105struct vm_pptdev_msi {
106 int vcpu;
107 int bus;
108 int slot;
109 int func;
110 int numvec; /* 0 means disabled */
111 uint64_t msg;
112 uint64_t addr;
113};
114
115struct vm_pptdev_msix {
116 int vcpu;
117 int bus;
118 int slot;
119 int func;
120 int idx;
121 uint64_t msg;
122 uint32_t vector_control;
123 uint64_t addr;
124};
125
126struct vm_nmi {
127 int cpuid;
128};
129
130#define MAX_VM_STATS 64
131struct vm_stats {
132 int cpuid; /* in */
133 int num_entries; /* out */
134 struct timeval tv;
135 uint64_t statbuf[MAX_VM_STATS];
136};
137
138struct vm_stat_desc {
139 int index; /* in */
140 char desc[128]; /* out */
141};
142
143struct vm_x2apic {
144 int cpuid;
145 enum x2apic_state state;
146};
147
148struct vm_gpa_pte {
149 uint64_t gpa; /* in */
150 uint64_t pte[4]; /* out */
151 int ptenum;
152};
153
154struct vm_hpet_cap {
155 uint32_t capabilities; /* lower 32 bits of HPET capabilities */
156};
157
158enum {
159 /* general routines */
160 IOCNUM_ABIVERS = 0,
161 IOCNUM_RUN = 1,
162 IOCNUM_SET_CAPABILITY = 2,
163 IOCNUM_GET_CAPABILITY = 3,
164
165 /* memory apis */
166 IOCNUM_MAP_MEMORY = 10,
167 IOCNUM_GET_MEMORY_SEG = 11,
168 IOCNUM_GET_GPA_PMAP = 12,
169
170 /* register/state accessors */
171 IOCNUM_SET_REGISTER = 20,
172 IOCNUM_GET_REGISTER = 21,
173 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
174 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
175
176 /* interrupt injection */
177 IOCNUM_INJECT_EVENT = 30,
178 IOCNUM_LAPIC_IRQ = 31,
179 IOCNUM_INJECT_NMI = 32,
180 IOCNUM_IOAPIC_ASSERT_IRQ = 33,
181 IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
182 IOCNUM_IOAPIC_PULSE_IRQ = 35,
183 IOCNUM_LAPIC_MSI = 36,
|
184 IOCNUM_LAPIC_LOCAL_IRQ = 37,
| 184 IOCNUM_LAPIC_LOCAL_IRQ = 37,
185 IOCNUM_IOAPIC_PINCOUNT = 38,
|
185
186 /* PCI pass-thru */
187 IOCNUM_BIND_PPTDEV = 40,
188 IOCNUM_UNBIND_PPTDEV = 41,
189 IOCNUM_MAP_PPTDEV_MMIO = 42,
190 IOCNUM_PPTDEV_MSI = 43,
191 IOCNUM_PPTDEV_MSIX = 44,
192
193 /* statistics */
194 IOCNUM_VM_STATS = 50,
195 IOCNUM_VM_STAT_DESC = 51,
196
197 /* kernel device state */
198 IOCNUM_SET_X2APIC_STATE = 60,
199 IOCNUM_GET_X2APIC_STATE = 61,
200 IOCNUM_GET_HPET_CAPABILITIES = 62,
201};
202
203#define VM_RUN \
204 _IOWR('v', IOCNUM_RUN, struct vm_run)
205#define VM_MAP_MEMORY \
206 _IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment)
207#define VM_GET_MEMORY_SEG \
208 _IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment)
209#define VM_SET_REGISTER \
210 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
211#define VM_GET_REGISTER \
212 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
213#define VM_SET_SEGMENT_DESCRIPTOR \
214 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
215#define VM_GET_SEGMENT_DESCRIPTOR \
216 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
217#define VM_INJECT_EVENT \
218 _IOW('v', IOCNUM_INJECT_EVENT, struct vm_event)
219#define VM_LAPIC_IRQ \
220 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
221#define VM_LAPIC_LOCAL_IRQ \
222 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
223#define VM_LAPIC_MSI \
224 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
225#define VM_IOAPIC_ASSERT_IRQ \
226 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
227#define VM_IOAPIC_DEASSERT_IRQ \
228 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
229#define VM_IOAPIC_PULSE_IRQ \
230 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
| 186
187 /* PCI pass-thru */
188 IOCNUM_BIND_PPTDEV = 40,
189 IOCNUM_UNBIND_PPTDEV = 41,
190 IOCNUM_MAP_PPTDEV_MMIO = 42,
191 IOCNUM_PPTDEV_MSI = 43,
192 IOCNUM_PPTDEV_MSIX = 44,
193
194 /* statistics */
195 IOCNUM_VM_STATS = 50,
196 IOCNUM_VM_STAT_DESC = 51,
197
198 /* kernel device state */
199 IOCNUM_SET_X2APIC_STATE = 60,
200 IOCNUM_GET_X2APIC_STATE = 61,
201 IOCNUM_GET_HPET_CAPABILITIES = 62,
202};
203
204#define VM_RUN \
205 _IOWR('v', IOCNUM_RUN, struct vm_run)
206#define VM_MAP_MEMORY \
207 _IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment)
208#define VM_GET_MEMORY_SEG \
209 _IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment)
210#define VM_SET_REGISTER \
211 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
212#define VM_GET_REGISTER \
213 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
214#define VM_SET_SEGMENT_DESCRIPTOR \
215 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
216#define VM_GET_SEGMENT_DESCRIPTOR \
217 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
218#define VM_INJECT_EVENT \
219 _IOW('v', IOCNUM_INJECT_EVENT, struct vm_event)
220#define VM_LAPIC_IRQ \
221 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
222#define VM_LAPIC_LOCAL_IRQ \
223 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
224#define VM_LAPIC_MSI \
225 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
226#define VM_IOAPIC_ASSERT_IRQ \
227 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
228#define VM_IOAPIC_DEASSERT_IRQ \
229 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
230#define VM_IOAPIC_PULSE_IRQ \
231 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
|
| 232#define VM_IOAPIC_PINCOUNT \
233 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
|
231#define VM_SET_CAPABILITY \
232 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
233#define VM_GET_CAPABILITY \
234 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
235#define VM_BIND_PPTDEV \
236 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
237#define VM_UNBIND_PPTDEV \
238 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
239#define VM_MAP_PPTDEV_MMIO \
240 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
241#define VM_PPTDEV_MSI \
242 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
243#define VM_PPTDEV_MSIX \
244 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
245#define VM_INJECT_NMI \
246 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
247#define VM_STATS \
248 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
249#define VM_STAT_DESC \
250 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
251#define VM_SET_X2APIC_STATE \
252 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
253#define VM_GET_X2APIC_STATE \
254 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
255#define VM_GET_HPET_CAPABILITIES \
256 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
257#define VM_GET_GPA_PMAP \
258 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
259#endif
| 234#define VM_SET_CAPABILITY \
235 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
236#define VM_GET_CAPABILITY \
237 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
238#define VM_BIND_PPTDEV \
239 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
240#define VM_UNBIND_PPTDEV \
241 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
242#define VM_MAP_PPTDEV_MMIO \
243 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
244#define VM_PPTDEV_MSI \
245 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
246#define VM_PPTDEV_MSIX \
247 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
248#define VM_INJECT_NMI \
249 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
250#define VM_STATS \
251 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
252#define VM_STAT_DESC \
253 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
254#define VM_SET_X2APIC_STATE \
255 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
256#define VM_GET_X2APIC_STATE \
257 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
258#define VM_GET_HPET_CAPABILITIES \
259 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
260#define VM_GET_GPA_PMAP \
261 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
262#endif
|