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specialreg.h (177125) specialreg.h (181430)
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
30 * $FreeBSD: head/sys/amd64/include/specialreg.h 177125 2008-03-12 22:09:19Z jhb $
30 * $FreeBSD: head/sys/amd64/include/specialreg.h 181430 2008-08-08 16:26:53Z stas $
31 */
32
33#ifndef _MACHINE_SPECIALREG_H_
34#define _MACHINE_SPECIALREG_H_
35
36/*
37 * Bits in 386 special registers:
38 */

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161#define CPUID_LOCAL_APIC_ID 0xff000000
162
163/*
164 * AMD extended function 8000_0008h ecx info
165 */
166#define AMDID_CMP_CORES 0x000000ff
167
168/*
31 */
32
33#ifndef _MACHINE_SPECIALREG_H_
34#define _MACHINE_SPECIALREG_H_
35
36/*
37 * Bits in 386 special registers:
38 */

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161#define CPUID_LOCAL_APIC_ID 0xff000000
162
163/*
164 * AMD extended function 8000_0008h ecx info
165 */
166#define AMDID_CMP_CORES 0x000000ff
167
168/*
169 * CPUID manufacturers identifiers
170 */
171#define INTEL_VENDOR_ID "GenuineIntel"
172#define AMD_VENDOR_ID "AuthenticAMD"
173
174/*
169 * Model-specific registers for the i386 family
170 */
171#define MSR_P5_MC_ADDR 0x000
172#define MSR_P5_MC_TYPE 0x001
173#define MSR_TSC 0x010
174#define MSR_P5_CESR 0x011
175#define MSR_P5_CTR0 0x012
176#define MSR_P5_CTR1 0x013

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409#define MSR_PERFCTR3 0xc0010007
410#define MSR_SYSCFG 0xc0010010
411#define MSR_IORRBASE0 0xc0010016
412#define MSR_IORRMASK0 0xc0010017
413#define MSR_IORRBASE1 0xc0010018
414#define MSR_IORRMASK1 0xc0010019
415#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
416#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
175 * Model-specific registers for the i386 family
176 */
177#define MSR_P5_MC_ADDR 0x000
178#define MSR_P5_MC_TYPE 0x001
179#define MSR_TSC 0x010
180#define MSR_P5_CESR 0x011
181#define MSR_P5_CTR0 0x012
182#define MSR_P5_CTR1 0x013

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415#define MSR_PERFCTR3 0xc0010007
416#define MSR_SYSCFG 0xc0010010
417#define MSR_IORRBASE0 0xc0010016
418#define MSR_IORRMASK0 0xc0010017
419#define MSR_IORRBASE1 0xc0010018
420#define MSR_IORRMASK1 0xc0010019
421#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
422#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
423#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
417
418#endif /* !_MACHINE_SPECIALREG_H_ */
424
425#endif /* !_MACHINE_SPECIALREG_H_ */