1//===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "DisassemblerEmitter.h"
11#include "CodeGenTarget.h"
12#include "Record.h"
| 1//===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "DisassemblerEmitter.h"
11#include "CodeGenTarget.h"
12#include "Record.h"
|
| 13#include "X86DisassemblerTables.h"
14#include "X86RecognizableInstr.h"
|
13using namespace llvm;
| 15using namespace llvm;
|
| 16using namespace llvm::X86Disassembler;
|
14
| 17
|
| 18/// DisassemblerEmitter - Contains disassembler table emitters for various
19/// architectures.
20
21/// X86 Disassembler Emitter
22///
23/// *** IF YOU'RE HERE TO RESOLVE A "Primary decode conflict", LOOK DOWN NEAR
24/// THE END OF THIS COMMENT!
25///
26/// The X86 disassembler emitter is part of the X86 Disassembler, which is
27/// documented in lib/Target/X86/X86Disassembler.h.
28///
29/// The emitter produces the tables that the disassembler uses to translate
30/// instructions. The emitter generates the following tables:
31///
32/// - One table (CONTEXTS_SYM) that contains a mapping of attribute masks to
33/// instruction contexts. Although for each attribute there are cases where
34/// that attribute determines decoding, in the majority of cases decoding is
35/// the same whether or not an attribute is present. For example, a 64-bit
36/// instruction with an OPSIZE prefix and an XS prefix decodes the same way in
37/// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix
38/// may have effects on its execution, but does not change the instruction
39/// returned.) This allows considerable space savings in other tables.
40/// - Four tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, and
41/// THREEBYTE3A_SYM) contain the hierarchy that the decoder traverses while
42/// decoding an instruction. At the lowest level of this hierarchy are
43/// instruction UIDs, 16-bit integers that can be used to uniquely identify
44/// the instruction and correspond exactly to its position in the list of
45/// CodeGenInstructions for the target.
46/// - One table (INSTRUCTIONS_SYM) contains information about the operands of
47/// each instruction and how to decode them.
48///
49/// During table generation, there may be conflicts between instructions that
50/// occupy the same space in the decode tables. These conflicts are resolved as
51/// follows in setTableFields() (X86DisassemblerTables.cpp)
52///
53/// - If the current context is the native context for one of the instructions
54/// (that is, the attributes specified for it in the LLVM tables specify
55/// precisely the current context), then it has priority.
56/// - If the current context isn't native for either of the instructions, then
57/// the higher-priority context wins (that is, the one that is more specific).
58/// That hierarchy is determined by outranks() (X86DisassemblerTables.cpp)
59/// - If the current context is native for both instructions, then the table
60/// emitter reports a conflict and dies.
61///
62/// *** RESOLUTION FOR "Primary decode conflict"S
63///
64/// If two instructions collide, typically the solution is (in order of
65/// likelihood):
66///
67/// (1) to filter out one of the instructions by editing filter()
68/// (X86RecognizableInstr.cpp). This is the most common resolution, but
69/// check the Intel manuals first to make sure that (2) and (3) are not the
70/// problem.
71/// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are
72/// accurate. Sometimes they are not.
73/// (3) to fix the tables to reflect the actual context (for example, required
74/// prefixes), and possibly to add a new context by editing
75/// lib/Target/X86/X86DisassemblerDecoderCommon.h. This is unlikely to be
76/// the cause.
77///
78/// DisassemblerEmitter.cpp contains the implementation for the emitter,
79/// which simply pulls out instructions from the CodeGenTarget and pushes them
80/// into X86DisassemblerTables.
81/// X86DisassemblerTables.h contains the interface for the instruction tables,
82/// which manage and emit the structures discussed above.
83/// X86DisassemblerTables.cpp contains the implementation for the instruction
84/// tables.
85/// X86ModRMFilters.h contains filters that can be used to determine which
86/// ModR/M values are valid for a particular instruction. These are used to
87/// populate ModRMDecisions.
88/// X86RecognizableInstr.h contains the interface for a single instruction,
89/// which knows how to translate itself from a CodeGenInstruction and provide
90/// the information necessary for integration into the tables.
91/// X86RecognizableInstr.cpp contains the implementation for a single
92/// instruction.
93
|
15void DisassemblerEmitter::run(raw_ostream &OS) {
16 CodeGenTarget Target;
17
18 OS << "/*===- TableGen'erated file "
19 << "---------------------------------------*- C -*-===*\n"
20 << " *\n"
21 << " * " << Target.getName() << " Disassembler\n"
22 << " *\n"
23 << " * Automatically generated file, do not edit!\n"
24 << " *\n"
25 << " *===---------------------------------------------------------------"
26 << "-------===*/\n";
27
| 94void DisassemblerEmitter::run(raw_ostream &OS) {
95 CodeGenTarget Target;
96
97 OS << "/*===- TableGen'erated file "
98 << "---------------------------------------*- C -*-===*\n"
99 << " *\n"
100 << " * " << Target.getName() << " Disassembler\n"
101 << " *\n"
102 << " * Automatically generated file, do not edit!\n"
103 << " *\n"
104 << " *===---------------------------------------------------------------"
105 << "-------===*/\n";
106
|
| 107 // X86 uses a custom disassembler.
108 if (Target.getName() == "X86") {
109 DisassemblerTables Tables;
110
111 std::vector<const CodeGenInstruction*> numberedInstructions;
112 Target.getInstructionsByEnumValue(numberedInstructions);
113
114 for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i)
115 RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i);
116
117 // FIXME: As long as we are using exceptions, might as well drop this to the
118 // actual conflict site.
119 if (Tables.hasConflicts())
120 throw TGError(Target.getTargetRecord()->getLoc(),
121 "Primary decode conflict");
122
123 Tables.emit(OS);
124 return;
125 }
126
|
28 throw TGError(Target.getTargetRecord()->getLoc(),
29 "Unable to generate disassembler for this target");
30}
| 127 throw TGError(Target.getTargetRecord()->getLoc(),
128 "Unable to generate disassembler for this target");
129}
|