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X86Schedule.td (234353) X86Schedule.td (239462)
1//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
1//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Instruction Itinerary classes used for X86
11// Instruction Itinerary classes used for X86
12def IIC_DEFAULT : InstrItinClass;
13def IIC_ALU_MEM : InstrItinClass;
14def IIC_ALU_NONMEM : InstrItinClass;
15def IIC_LEA : InstrItinClass;
16def IIC_LEA_16 : InstrItinClass;
17def IIC_MUL8 : InstrItinClass;
18def IIC_MUL16_MEM : InstrItinClass;
19def IIC_MUL16_REG : InstrItinClass;

--- 228 unchanged lines hidden (view full) ---

248def IIC_SSE_CVT_Scalar_RM : InstrItinClass;
249def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass;
250def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass;
251def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass;
252def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
253def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
254def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
255
12def IIC_DEFAULT : InstrItinClass;
13def IIC_ALU_MEM : InstrItinClass;
14def IIC_ALU_NONMEM : InstrItinClass;
15def IIC_LEA : InstrItinClass;
16def IIC_LEA_16 : InstrItinClass;
17def IIC_MUL8 : InstrItinClass;
18def IIC_MUL16_MEM : InstrItinClass;
19def IIC_MUL16_REG : InstrItinClass;

--- 228 unchanged lines hidden (view full) ---

248def IIC_SSE_CVT_Scalar_RM : InstrItinClass;
249def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass;
250def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass;
251def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass;
252def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
253def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
254def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
255
256// MMX
257def IIC_MMX_MOV_MM_RM : InstrItinClass;
258def IIC_MMX_MOV_REG_MM : InstrItinClass;
259def IIC_MMX_MOVQ_RM : InstrItinClass;
260def IIC_MMX_MOVQ_RR : InstrItinClass;
261
262def IIC_MMX_ALU_RM : InstrItinClass;
263def IIC_MMX_ALU_RR : InstrItinClass;
264def IIC_MMX_ALUQ_RM : InstrItinClass;
265def IIC_MMX_ALUQ_RR : InstrItinClass;
266def IIC_MMX_PHADDSUBW_RM : InstrItinClass;
267def IIC_MMX_PHADDSUBW_RR : InstrItinClass;
268def IIC_MMX_PHADDSUBD_RM : InstrItinClass;
269def IIC_MMX_PHADDSUBD_RR : InstrItinClass;
270def IIC_MMX_PMUL : InstrItinClass;
271def IIC_MMX_MISC_FUNC_MEM : InstrItinClass;
272def IIC_MMX_MISC_FUNC_REG : InstrItinClass;
273def IIC_MMX_PSADBW : InstrItinClass;
274def IIC_MMX_SHIFT_RI : InstrItinClass;
275def IIC_MMX_SHIFT_RM : InstrItinClass;
276def IIC_MMX_SHIFT_RR : InstrItinClass;
277def IIC_MMX_UNPCK_H_RM : InstrItinClass;
278def IIC_MMX_UNPCK_H_RR : InstrItinClass;
279def IIC_MMX_UNPCK_L : InstrItinClass;
280def IIC_MMX_PCK_RM : InstrItinClass;
281def IIC_MMX_PCK_RR : InstrItinClass;
282def IIC_MMX_PSHUF : InstrItinClass;
283def IIC_MMX_PEXTR : InstrItinClass;
284def IIC_MMX_PINSRW : InstrItinClass;
285def IIC_MMX_MASKMOV : InstrItinClass;
286
287def IIC_MMX_CVT_PD_RR : InstrItinClass;
288def IIC_MMX_CVT_PD_RM : InstrItinClass;
289def IIC_MMX_CVT_PS_RR : InstrItinClass;
290def IIC_MMX_CVT_PS_RM : InstrItinClass;
291
256def IIC_CMPX_LOCK : InstrItinClass;
257def IIC_CMPX_LOCK_8 : InstrItinClass;
258def IIC_CMPX_LOCK_8B : InstrItinClass;
259def IIC_CMPX_LOCK_16B : InstrItinClass;
260
261def IIC_XADD_LOCK_MEM : InstrItinClass;
262def IIC_XADD_LOCK_MEM8 : InstrItinClass;
263
292def IIC_CMPX_LOCK : InstrItinClass;
293def IIC_CMPX_LOCK_8 : InstrItinClass;
294def IIC_CMPX_LOCK_8B : InstrItinClass;
295def IIC_CMPX_LOCK_16B : InstrItinClass;
296
297def IIC_XADD_LOCK_MEM : InstrItinClass;
298def IIC_XADD_LOCK_MEM8 : InstrItinClass;
299
300def IIC_FILD : InstrItinClass;
301def IIC_FLD : InstrItinClass;
302def IIC_FLD80 : InstrItinClass;
303def IIC_FST : InstrItinClass;
304def IIC_FST80 : InstrItinClass;
305def IIC_FIST : InstrItinClass;
306def IIC_FLDZ : InstrItinClass;
307def IIC_FUCOM : InstrItinClass;
308def IIC_FUCOMI : InstrItinClass;
309def IIC_FCOMI : InstrItinClass;
310def IIC_FNSTSW : InstrItinClass;
311def IIC_FNSTCW : InstrItinClass;
312def IIC_FLDCW : InstrItinClass;
313def IIC_FNINIT : InstrItinClass;
314def IIC_FFREE : InstrItinClass;
315def IIC_FNCLEX : InstrItinClass;
316def IIC_WAIT : InstrItinClass;
317def IIC_FXAM : InstrItinClass;
318def IIC_FNOP : InstrItinClass;
319def IIC_FLDL : InstrItinClass;
320def IIC_F2XM1 : InstrItinClass;
321def IIC_FYL2X : InstrItinClass;
322def IIC_FPTAN : InstrItinClass;
323def IIC_FPATAN : InstrItinClass;
324def IIC_FXTRACT : InstrItinClass;
325def IIC_FPREM1 : InstrItinClass;
326def IIC_FPSTP : InstrItinClass;
327def IIC_FPREM : InstrItinClass;
328def IIC_FYL2XP1 : InstrItinClass;
329def IIC_FSINCOS : InstrItinClass;
330def IIC_FRNDINT : InstrItinClass;
331def IIC_FSCALE : InstrItinClass;
332def IIC_FCOMPP : InstrItinClass;
333def IIC_FXSAVE : InstrItinClass;
334def IIC_FXRSTOR : InstrItinClass;
264
335
265//===----------------------------------------------------------------------===//
266// Processor instruction itineraries.
336def IIC_FXCH : InstrItinClass;
267
337
268def GenericItineraries : ProcessorItineraries<[], [], []>;
338// System instructions
339def IIC_CPUID : InstrItinClass;
340def IIC_INT : InstrItinClass;
341def IIC_INT3 : InstrItinClass;
342def IIC_INVD : InstrItinClass;
343def IIC_INVLPG : InstrItinClass;
344def IIC_IRET : InstrItinClass;
345def IIC_HLT : InstrItinClass;
346def IIC_LXS : InstrItinClass;
347def IIC_LTR : InstrItinClass;
348def IIC_RDTSC : InstrItinClass;
349def IIC_RSM : InstrItinClass;
350def IIC_SIDT : InstrItinClass;
351def IIC_SGDT : InstrItinClass;
352def IIC_SLDT : InstrItinClass;
353def IIC_STR : InstrItinClass;
354def IIC_SWAPGS : InstrItinClass;
355def IIC_SYSCALL : InstrItinClass;
356def IIC_SYS_ENTER_EXIT : InstrItinClass;
357def IIC_IN_RR : InstrItinClass;
358def IIC_IN_RI : InstrItinClass;
359def IIC_OUT_RR : InstrItinClass;
360def IIC_OUT_IR : InstrItinClass;
361def IIC_INS : InstrItinClass;
362def IIC_MOV_REG_DR : InstrItinClass;
363def IIC_MOV_DR_REG : InstrItinClass;
364def IIC_MOV_REG_CR : InstrItinClass;
365def IIC_MOV_CR_REG : InstrItinClass;
366def IIC_MOV_REG_SR : InstrItinClass;
367def IIC_MOV_MEM_SR : InstrItinClass;
368def IIC_MOV_SR_REG : InstrItinClass;
369def IIC_MOV_SR_MEM : InstrItinClass;
370def IIC_LAR_RM : InstrItinClass;
371def IIC_LAR_RR : InstrItinClass;
372def IIC_LSL_RM : InstrItinClass;
373def IIC_LSL_RR : InstrItinClass;
374def IIC_LGDT : InstrItinClass;
375def IIC_LIDT : InstrItinClass;
376def IIC_LLDT_REG : InstrItinClass;
377def IIC_LLDT_MEM : InstrItinClass;
378def IIC_PUSH_CS : InstrItinClass;
379def IIC_PUSH_SR : InstrItinClass;
380def IIC_POP_SR : InstrItinClass;
381def IIC_POP_SR_SS : InstrItinClass;
382def IIC_VERR : InstrItinClass;
383def IIC_VERW_REG : InstrItinClass;
384def IIC_VERW_MEM : InstrItinClass;
385def IIC_WRMSR : InstrItinClass;
386def IIC_RDMSR : InstrItinClass;
387def IIC_RDPMC : InstrItinClass;
388def IIC_SMSW : InstrItinClass;
389def IIC_LMSW_REG : InstrItinClass;
390def IIC_LMSW_MEM : InstrItinClass;
391def IIC_ENTER : InstrItinClass;
392def IIC_LEAVE : InstrItinClass;
393def IIC_POP_MEM : InstrItinClass;
394def IIC_POP_REG16 : InstrItinClass;
395def IIC_POP_REG : InstrItinClass;
396def IIC_POP_F : InstrItinClass;
397def IIC_POP_FD : InstrItinClass;
398def IIC_POP_A : InstrItinClass;
399def IIC_PUSH_IMM : InstrItinClass;
400def IIC_PUSH_MEM : InstrItinClass;
401def IIC_PUSH_REG : InstrItinClass;
402def IIC_PUSH_F : InstrItinClass;
403def IIC_PUSH_A : InstrItinClass;
404def IIC_BSWAP : InstrItinClass;
405def IIC_BSF : InstrItinClass;
406def IIC_BSR : InstrItinClass;
407def IIC_MOVS : InstrItinClass;
408def IIC_STOS : InstrItinClass;
409def IIC_SCAS : InstrItinClass;
410def IIC_CMPS : InstrItinClass;
411def IIC_MOV : InstrItinClass;
412def IIC_MOV_MEM : InstrItinClass;
413def IIC_AHF : InstrItinClass;
414def IIC_BT_MI : InstrItinClass;
415def IIC_BT_MR : InstrItinClass;
416def IIC_BT_RI : InstrItinClass;
417def IIC_BT_RR : InstrItinClass;
418def IIC_BTX_MI : InstrItinClass;
419def IIC_BTX_MR : InstrItinClass;
420def IIC_BTX_RI : InstrItinClass;
421def IIC_BTX_RR : InstrItinClass;
422def IIC_XCHG_REG : InstrItinClass;
423def IIC_XCHG_MEM : InstrItinClass;
424def IIC_XADD_REG : InstrItinClass;
425def IIC_XADD_MEM : InstrItinClass;
426def IIC_CMPXCHG_MEM : InstrItinClass;
427def IIC_CMPXCHG_REG : InstrItinClass;
428def IIC_CMPXCHG_MEM8 : InstrItinClass;
429def IIC_CMPXCHG_REG8 : InstrItinClass;
430def IIC_CMPXCHG_8B : InstrItinClass;
431def IIC_CMPXCHG_16B : InstrItinClass;
432def IIC_LODS : InstrItinClass;
433def IIC_OUTS : InstrItinClass;
434def IIC_CLC : InstrItinClass;
435def IIC_CLD : InstrItinClass;
436def IIC_CLI : InstrItinClass;
437def IIC_CMC : InstrItinClass;
438def IIC_CLTS : InstrItinClass;
439def IIC_STC : InstrItinClass;
440def IIC_STI : InstrItinClass;
441def IIC_STD : InstrItinClass;
442def IIC_XLAT : InstrItinClass;
443def IIC_AAA : InstrItinClass;
444def IIC_AAD : InstrItinClass;
445def IIC_AAM : InstrItinClass;
446def IIC_AAS : InstrItinClass;
447def IIC_DAA : InstrItinClass;
448def IIC_DAS : InstrItinClass;
449def IIC_BOUND : InstrItinClass;
450def IIC_ARPL_REG : InstrItinClass;
451def IIC_ARPL_MEM : InstrItinClass;
452def IIC_MOVBE : InstrItinClass;
269
453
270include "X86ScheduleAtom.td"
454def IIC_NOP : InstrItinClass;
271
455
456//===----------------------------------------------------------------------===//
457// Processor instruction itineraries.
272
458
459// IssueWidth is analagous to the number of decode units. Core and its
460// descendents, including Nehalem and SandyBridge have 4 decoders.
461// Resources beyond the decoder operate on micro-ops and are bufferred
462// so adjacent micro-ops don't directly compete.
463//
464// MinLatency=0 indicates that RAW dependencies can be decoded in the
465// same cycle.
466//
467// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
468// indicates high latency opcodes. Alternatively, InstrItinData
469// entries may be included here to define specific operand
470// latencies. Since these latencies are not used for pipeline hazards,
471// they do not need to be exact.
472//
473// The GenericModel contains no instruciton itineraries.
474def GenericModel : SchedMachineModel {
475 let IssueWidth = 4;
476 let MinLatency = 0;
477 let LoadLatency = 4;
478 let HighLatency = 10;
479}
273
480
481include "X86ScheduleAtom.td"