SparcTargetMachine.cpp (199481) | SparcTargetMachine.cpp (203954) |
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1//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 5 unchanged lines hidden (view full) --- 14#include "SparcTargetMachine.h" 15#include "Sparc.h" 16#include "llvm/PassManager.h" 17#include "llvm/Target/TargetRegistry.h" 18using namespace llvm; 19 20extern "C" void LLVMInitializeSparcTarget() { 21 // Register the target. | 1//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 5 unchanged lines hidden (view full) --- 14#include "SparcTargetMachine.h" 15#include "Sparc.h" 16#include "llvm/PassManager.h" 17#include "llvm/Target/TargetRegistry.h" 18using namespace llvm; 19 20extern "C" void LLVMInitializeSparcTarget() { 21 // Register the target. |
22 RegisterTargetMachine 23 RegisterAsmInfo<SparcELFMCAsmInfo> Y(TheSparcTarget); | 22 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); 23 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); |
24 | 24 |
25 RegisterAsmInfo<SparcELFMCAsmInfo> A(TheSparcTarget); 26 RegisterAsmInfo<SparcELFMCAsmInfo> B(TheSparcV9Target); 27 |
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25} 26 27/// SparcTargetMachine ctor - Create an ILP32 architecture model 28/// 29SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, | 28} 29 30/// SparcTargetMachine ctor - Create an ILP32 architecture model 31/// 32SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, |
30 const std::string &FS) | 33 const std::string &FS, bool is64bit) |
31 : LLVMTargetMachine(T, TT), | 34 : LLVMTargetMachine(T, TT), |
32 DataLayout("E-p:32:32-f128:128:128-n32"), 33 Subtarget(TT, FS), TLInfo(*this), InstrInfo(Subtarget), | 35 Subtarget(TT, FS, is64bit), 36 DataLayout(Subtarget.getDataLayout()), 37 TLInfo(*this), InstrInfo(Subtarget), |
34 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) { 35} 36 37bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, 38 CodeGenOpt::Level OptLevel) { 39 PM.add(createSparcISelDag(*this)); 40 return false; 41} 42 43/// addPreEmitPass - This pass may be implemented by targets that want to run 44/// passes immediately before machine code is emitted. This should return 45/// true if -print-machineinstrs should print out the code after the passes. 46bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, 47 CodeGenOpt::Level OptLevel){ 48 PM.add(createSparcFPMoverPass(*this)); 49 PM.add(createSparcDelaySlotFillerPass(*this)); 50 return true; 51} | 38 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) { 39} 40 41bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, 42 CodeGenOpt::Level OptLevel) { 43 PM.add(createSparcISelDag(*this)); 44 return false; 45} 46 47/// addPreEmitPass - This pass may be implemented by targets that want to run 48/// passes immediately before machine code is emitted. This should return 49/// true if -print-machineinstrs should print out the code after the passes. 50bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, 51 CodeGenOpt::Level OptLevel){ 52 PM.add(createSparcFPMoverPass(*this)); 53 PM.add(createSparcDelaySlotFillerPass(*this)); 54 return true; 55} |
56 57SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, 58 const std::string &TT, 59 const std::string &FS) 60 : SparcTargetMachine(T, TT, FS, false) { 61} 62 63SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, 64 const std::string &TT, 65 const std::string &FS) 66 : SparcTargetMachine(T, TT, FS, true) { 67} |
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