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PPCRegisterInfo.cpp (193574) PPCRegisterInfo.cpp (195340)
1//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 135 unchanged lines hidden (view full) ---

144 return &PPC::G8RCRegClass;
145 else
146 return &PPC::GPRCRegClass;
147}
148
149const unsigned*
150PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151 // 32-bit Darwin calling convention.
1//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 135 unchanged lines hidden (view full) ---

144 return &PPC::G8RCRegClass;
145 else
146 return &PPC::GPRCRegClass;
147}
148
149const unsigned*
150PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151 // 32-bit Darwin calling convention.
152 static const unsigned Macho32_CalleeSavedRegs[] = {
152 static const unsigned Darwin32_CalleeSavedRegs[] = {
153 PPC::R13, PPC::R14, PPC::R15,
154 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
155 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
156 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
157 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
158
159 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
160 PPC::F18, PPC::F19, PPC::F20, PPC::F21,

--- 8 unchanged lines hidden (view full) ---

169
170 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
171 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
172 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
173
174 PPC::LR, 0
175 };
176
153 PPC::R13, PPC::R14, PPC::R15,
154 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
155 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
156 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
157 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
158
159 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
160 PPC::F18, PPC::F19, PPC::F20, PPC::F21,

--- 8 unchanged lines hidden (view full) ---

169
170 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
171 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
172 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
173
174 PPC::LR, 0
175 };
176
177 static const unsigned ELF32_CalleeSavedRegs[] = {
178 PPC::R13, PPC::R14, PPC::R15,
177 static const unsigned SVR4_CalleeSavedRegs[] = {
178 PPC::R14, PPC::R15,
179 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
180 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
182 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
183
179 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
180 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
182 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
183
184 PPC::F9,
185 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
186 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
187 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
188 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
189 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
190 PPC::F30, PPC::F31,
191
192 PPC::CR2, PPC::CR3, PPC::CR4,
184 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
185 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
186 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
187 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
188 PPC::F30, PPC::F31,
189
190 PPC::CR2, PPC::CR3, PPC::CR4,
191
192 PPC::VRSAVE,
193
193 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
194 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
195 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
196
197 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
198 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
199 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
200
201 PPC::LR, 0
202 };
203 // 64-bit Darwin calling convention.
194 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
195 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
196 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
197
198 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
199 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
200 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
201
202 PPC::LR, 0
203 };
204 // 64-bit Darwin calling convention.
204 static const unsigned Macho64_CalleeSavedRegs[] = {
205 static const unsigned Darwin64_CalleeSavedRegs[] = {
205 PPC::X14, PPC::X15,
206 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
207 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
208 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
209 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
210
211 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
212 PPC::F18, PPC::F19, PPC::F20, PPC::F21,

--- 8 unchanged lines hidden (view full) ---

221
222 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
223 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
224 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
225
226 PPC::LR8, 0
227 };
228
206 PPC::X14, PPC::X15,
207 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
208 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
209 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
210 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
211
212 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
213 PPC::F18, PPC::F19, PPC::F20, PPC::F21,

--- 8 unchanged lines hidden (view full) ---

222
223 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
224 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
225 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
226
227 PPC::LR8, 0
228 };
229
229 if (Subtarget.isMachoABI())
230 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
231 Macho32_CalleeSavedRegs;
230 if (Subtarget.isDarwinABI())
231 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
232 Darwin32_CalleeSavedRegs;
232
233
233 // ELF 32.
234 return ELF32_CalleeSavedRegs;
234 return SVR4_CalleeSavedRegs;
235}
236
237const TargetRegisterClass* const*
238PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
235}
236
237const TargetRegisterClass* const*
238PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
239 // 32-bit Macho calling convention.
240 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
239 // 32-bit Darwin calling convention.
240 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
241 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
242 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
243 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
244 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
245 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
246
247 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
248 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,

--- 12 unchanged lines hidden (view full) ---

261 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
262 &PPC::CRBITRCRegClass,
263 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
264 &PPC::CRBITRCRegClass,
265
266 &PPC::GPRCRegClass, 0
267 };
268
241 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
242 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
243 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
244 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
245 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
246
247 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
248 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,

--- 12 unchanged lines hidden (view full) ---

261 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
262 &PPC::CRBITRCRegClass,
263 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
264 &PPC::CRBITRCRegClass,
265
266 &PPC::GPRCRegClass, 0
267 };
268
269 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
270 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
269 static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = {
270 &PPC::GPRCRegClass,&PPC::GPRCRegClass,
271 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
272 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
273 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
274 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
275
271 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
272 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
273 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
274 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
275
276 &PPC::F8RCRegClass,
277 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
278 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
279 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
280 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
276 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
277 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
278 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
279 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
281 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
282 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
283
284 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
285
280 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
281
282 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
283
284 &PPC::VRSAVERCRegClass,
285
286 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
287 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
288 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
289
290 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
291 &PPC::CRBITRCRegClass,
292 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
293 &PPC::CRBITRCRegClass,
294 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
295 &PPC::CRBITRCRegClass,
296
297 &PPC::GPRCRegClass, 0
298 };
299
286 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
287 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
288 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
289
290 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
291 &PPC::CRBITRCRegClass,
292 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
293 &PPC::CRBITRCRegClass,
294 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
295 &PPC::CRBITRCRegClass,
296
297 &PPC::GPRCRegClass, 0
298 };
299
300 // 64-bit Macho calling convention.
301 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
300 // 64-bit Darwin calling convention.
301 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
302 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
303 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
304 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
305 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
306 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
307
308 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
309 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,

--- 12 unchanged lines hidden (view full) ---

322 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
323 &PPC::CRBITRCRegClass,
324 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
325 &PPC::CRBITRCRegClass,
326
327 &PPC::G8RCRegClass, 0
328 };
329
302 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
303 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
304 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
305 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
306 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
307
308 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
309 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,

--- 12 unchanged lines hidden (view full) ---

322 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
323 &PPC::CRBITRCRegClass,
324 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
325 &PPC::CRBITRCRegClass,
326
327 &PPC::G8RCRegClass, 0
328 };
329
330 if (Subtarget.isMachoABI())
331 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
332 Macho32_CalleeSavedRegClasses;
330 if (Subtarget.isDarwinABI())
331 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
332 Darwin32_CalleeSavedRegClasses;
333
333
334 // ELF 32.
335 return ELF32_CalleeSavedRegClasses;
334 return SVR4_CalleeSavedRegClasses;
336}
337
338// needsFP - Return true if the specified function should have a dedicated frame
339// pointer register. This is true if the function has variable sized allocas or
340// if frame pointer elimination is disabled.
341//
342static bool needsFP(const MachineFunction &MF) {
343 const MachineFrameInfo *MFI = MF.getFrameInfo();

--- 9 unchanged lines hidden (view full) ---

353BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
354 BitVector Reserved(getNumRegs());
355 Reserved.set(PPC::R0);
356 Reserved.set(PPC::R1);
357 Reserved.set(PPC::LR);
358 Reserved.set(PPC::LR8);
359 Reserved.set(PPC::RM);
360
335}
336
337// needsFP - Return true if the specified function should have a dedicated frame
338// pointer register. This is true if the function has variable sized allocas or
339// if frame pointer elimination is disabled.
340//
341static bool needsFP(const MachineFunction &MF) {
342 const MachineFrameInfo *MFI = MF.getFrameInfo();

--- 9 unchanged lines hidden (view full) ---

352BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
353 BitVector Reserved(getNumRegs());
354 Reserved.set(PPC::R0);
355 Reserved.set(PPC::R1);
356 Reserved.set(PPC::LR);
357 Reserved.set(PPC::LR8);
358 Reserved.set(PPC::RM);
359
361 // In Linux, r2 is reserved for the OS.
362 if (!Subtarget.isDarwin())
363 Reserved.set(PPC::R2);
364
360 // The SVR4 ABI reserves r2 and r13
361 if (Subtarget.isSVR4ABI()) {
362 Reserved.set(PPC::R2); // System-reserved register
363 Reserved.set(PPC::R13); // Small Data Area pointer register
364 }
365
365 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
366 // that this is over conservative, as it also prevents allocation of R31 when
367 // the FP is not needed.
368 if (Subtarget.isPPC64()) {
369 Reserved.set(PPC::R13);
370 Reserved.set(PPC::R31);
371
372 if (!EnableRegisterScavenging)

--- 531 unchanged lines hidden (view full) ---

904 unsigned MaxAlign = MFI->getMaxAlignment();
905 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
906 unsigned AlignMask = TargetAlign - 1; //
907
908 // If we are a leaf function, and use up to 224 bytes of stack space,
909 // don't have a frame pointer, calls, or dynamic alloca then we do not need
910 // to adjust the stack pointer (we fit in the Red Zone).
911 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
366 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
367 // that this is over conservative, as it also prevents allocation of R31 when
368 // the FP is not needed.
369 if (Subtarget.isPPC64()) {
370 Reserved.set(PPC::R13);
371 Reserved.set(PPC::R31);
372
373 if (!EnableRegisterScavenging)

--- 531 unchanged lines hidden (view full) ---

905 unsigned MaxAlign = MFI->getMaxAlignment();
906 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
907 unsigned AlignMask = TargetAlign - 1; //
908
909 // If we are a leaf function, and use up to 224 bytes of stack space,
910 // don't have a frame pointer, calls, or dynamic alloca then we do not need
911 // to adjust the stack pointer (we fit in the Red Zone).
912 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
913 // FIXME SVR4 The SVR4 ABI has no red zone.
912 if (!DisableRedZone &&
913 FrameSize <= 224 && // Fits in red zone.
914 !MFI->hasVarSizedObjects() && // No dynamic alloca.
915 !MFI->hasCalls() && // No calls.
916 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
917 // No need for frame
918 MFI->setStackSize(0);
919 return;
920 }
921
922 // Get the maximum call frame size of all the calls.
923 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
924
925 // Maximum call frame needs to be at least big enough for linkage and 8 args.
926 unsigned minCallFrameSize =
927 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
914 if (!DisableRedZone &&
915 FrameSize <= 224 && // Fits in red zone.
916 !MFI->hasVarSizedObjects() && // No dynamic alloca.
917 !MFI->hasCalls() && // No calls.
918 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
919 // No need for frame
920 MFI->setStackSize(0);
921 return;
922 }
923
924 // Get the maximum call frame size of all the calls.
925 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
926
927 // Maximum call frame needs to be at least big enough for linkage and 8 args.
928 unsigned minCallFrameSize =
929 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
928 Subtarget.isMachoABI());
930 Subtarget.isDarwinABI());
929 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
930
931 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
932 // that allocations will be aligned.
933 if (MFI->hasVarSizedObjects())
934 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
935
936 // Update maximum call frame size.

--- 16 unchanged lines hidden (view full) ---

953 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
954 unsigned LR = getRARegister();
955 FI->setMustSaveLR(MustSaveLR(MF, LR));
956 MF.getRegInfo().setPhysRegUnused(LR);
957
958 // Save R31 if necessary
959 int FPSI = FI->getFramePointerSaveIndex();
960 bool IsPPC64 = Subtarget.isPPC64();
931 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
932
933 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
934 // that allocations will be aligned.
935 if (MFI->hasVarSizedObjects())
936 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
937
938 // Update maximum call frame size.

--- 16 unchanged lines hidden (view full) ---

955 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
956 unsigned LR = getRARegister();
957 FI->setMustSaveLR(MustSaveLR(MF, LR));
958 MF.getRegInfo().setPhysRegUnused(LR);
959
960 // Save R31 if necessary
961 int FPSI = FI->getFramePointerSaveIndex();
962 bool IsPPC64 = Subtarget.isPPC64();
961 bool IsELF32_ABI = Subtarget.isELF32_ABI();
962 bool IsMachoABI = Subtarget.isMachoABI();
963 bool IsSVR4ABI = Subtarget.isSVR4ABI();
964 bool isDarwinABI = Subtarget.isDarwinABI();
963 MachineFrameInfo *MFI = MF.getFrameInfo();
964
965 // If the frame pointer save index hasn't been defined yet.
965 MachineFrameInfo *MFI = MF.getFrameInfo();
966
967 // If the frame pointer save index hasn't been defined yet.
966 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
967 IsELF32_ABI) {
968 if (!FPSI && needsFP(MF) && IsSVR4ABI) {
968 // Find out what the fix offset of the frame pointer save area.
969 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
969 // Find out what the fix offset of the frame pointer save area.
970 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
970 IsMachoABI);
971 isDarwinABI);
971 // Allocate the frame index for frame pointer save area.
972 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
973 // Save the result.
974 FI->setFramePointerSaveIndex(FPSI);
975 }
976
977 // Reserve stack space to move the linkage area to in case of a tail call.
978 int TCSPDelta = 0;
972 // Allocate the frame index for frame pointer save area.
973 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
974 // Save the result.
975 FI->setFramePointerSaveIndex(FPSI);
976 }
977
978 // Reserve stack space to move the linkage area to in case of a tail call.
979 int TCSPDelta = 0;
979 if (PerformTailCallOpt && (TCSPDelta=FI->getTailCallSPDelta()) < 0) {
980 int AddFPOffsetAmount = IsELF32_ABI ? -4 : 0;
981 MF.getFrameInfo()->CreateFixedObject( -1 * TCSPDelta,
982 AddFPOffsetAmount + TCSPDelta);
980 if (PerformTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
981 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta);
983 }
982 }
983
984 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
985 // a large stack, which will require scavenging a register to materialize a
986 // large offset.
987 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
988 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
989 // r0 for now.
990
991 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
992 if (needsFP(MF) || spillsCR(MF)) {
993 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
994 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
995 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
996 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
997 RC->getAlignment()));
998 }
999}
1000
1001void
984 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
985 // a large stack, which will require scavenging a register to materialize a
986 // large offset.
987 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
988 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
989 // r0 for now.
990
991 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
992 if (needsFP(MF) || spillsCR(MF)) {
993 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
994 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
995 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
996 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
997 RC->getAlignment()));
998 }
999}
1000
1001void
1002PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
1003 const {
1004 // Early exit if not using the SVR4 ABI.
1005 if (!Subtarget.isSVR4ABI()) {
1006 return;
1007 }
1008
1009 // Get callee saved register information.
1010 MachineFrameInfo *FFI = MF.getFrameInfo();
1011 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1012
1013 // Early exit if no callee saved registers are modified!
1014 if (CSI.empty() && !needsFP(MF)) {
1015 return;
1016 }
1017
1018 unsigned MinGPR = PPC::R31;
1019 unsigned MinFPR = PPC::F31;
1020 unsigned MinVR = PPC::V31;
1021
1022 bool HasGPSaveArea = false;
1023 bool HasFPSaveArea = false;
1024 bool HasCRSaveArea = false;
1025 bool HasVRSAVESaveArea = false;
1026 bool HasVRSaveArea = false;
1027
1028 SmallVector<CalleeSavedInfo, 18> GPRegs;
1029 SmallVector<CalleeSavedInfo, 18> FPRegs;
1030 SmallVector<CalleeSavedInfo, 18> VRegs;
1031
1032 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1033 unsigned Reg = CSI[i].getReg();
1034 const TargetRegisterClass *RC = CSI[i].getRegClass();
1035
1036 if (RC == PPC::GPRCRegisterClass) {
1037 HasGPSaveArea = true;
1038
1039 GPRegs.push_back(CSI[i]);
1040
1041 if (Reg < MinGPR) {
1042 MinGPR = Reg;
1043 }
1044 } else if (RC == PPC::F8RCRegisterClass) {
1045 HasFPSaveArea = true;
1046
1047 FPRegs.push_back(CSI[i]);
1048
1049 if (Reg < MinFPR) {
1050 MinFPR = Reg;
1051 }
1052// FIXME SVR4: Disable CR save area for now.
1053 } else if ( RC == PPC::CRBITRCRegisterClass
1054 || RC == PPC::CRRCRegisterClass) {
1055// HasCRSaveArea = true;
1056 } else if (RC == PPC::VRSAVERCRegisterClass) {
1057 HasVRSAVESaveArea = true;
1058 } else if (RC == PPC::VRRCRegisterClass) {
1059 HasVRSaveArea = true;
1060
1061 VRegs.push_back(CSI[i]);
1062
1063 if (Reg < MinVR) {
1064 MinVR = Reg;
1065 }
1066 } else {
1067 assert(0 && "Unknown RegisterClass!");
1068 }
1069 }
1070
1071 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1072
1073 int64_t LowerBound = 0;
1074
1075 // Take into account stack space reserved for tail calls.
1076 int TCSPDelta = 0;
1077 if (PerformTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1078 LowerBound = TCSPDelta;
1079 }
1080
1081 // The Floating-point register save area is right below the back chain word
1082 // of the previous stack frame.
1083 if (HasFPSaveArea) {
1084 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1085 int FI = FPRegs[i].getFrameIdx();
1086
1087 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1088 }
1089
1090 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8;
1091 }
1092
1093 // Check whether the frame pointer register is allocated. If so, make sure it
1094 // is spilled to the correct offset.
1095 if (needsFP(MF)) {
1096 HasGPSaveArea = true;
1097
1098 int FI = PFI->getFramePointerSaveIndex();
1099 assert(FI && "No Frame Pointer Save Slot!");
1100
1101 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1102 }
1103
1104 // General register save area starts right below the Floating-point
1105 // register save area.
1106 if (HasGPSaveArea) {
1107 // Move general register save area spill slots down, taking into account
1108 // the size of the Floating-point register save area.
1109 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1110 int FI = GPRegs[i].getFrameIdx();
1111
1112 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1113 }
1114
1115 LowerBound -= (31 - getRegisterNumbering(MinGPR) + 1) * 4;
1116 }
1117
1118 // The CR save area is below the general register save area.
1119 if (HasCRSaveArea) {
1120 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1121 // which have the CR/CRBIT register class?
1122 // Adjust the frame index of the CR spill slot.
1123 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1124 const TargetRegisterClass *RC = CSI[i].getRegClass();
1125
1126 if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) {
1127 int FI = CSI[i].getFrameIdx();
1128
1129 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1130 }
1131 }
1132
1133 LowerBound -= 4; // The CR save area is always 4 bytes long.
1134 }
1135
1136 if (HasVRSAVESaveArea) {
1137 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1138 // which have the VRSAVE register class?
1139 // Adjust the frame index of the VRSAVE spill slot.
1140 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1141 const TargetRegisterClass *RC = CSI[i].getRegClass();
1142
1143 if (RC == PPC::VRSAVERCRegisterClass) {
1144 int FI = CSI[i].getFrameIdx();
1145
1146 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1147 }
1148 }
1149
1150 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1151 }
1152
1153 if (HasVRSaveArea) {
1154 // Insert alignment padding, we need 16-byte alignment.
1155 LowerBound = (LowerBound - 15) & ~(15);
1156
1157 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1158 int FI = VRegs[i].getFrameIdx();
1159
1160 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1161 }
1162 }
1163}
1164
1165void
1002PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
1003 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1004 MachineBasicBlock::iterator MBBI = MBB.begin();
1005 MachineFrameInfo *MFI = MF.getFrameInfo();
1006 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1007 DebugLoc dl = DebugLoc::getUnknownLoc();
1008 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
1009 !MF.getFunction()->doesNotThrow() ||

--- 18 unchanged lines hidden (view full) ---

1028 determineFrameLayout(MF);
1029 unsigned FrameSize = MFI->getStackSize();
1030
1031 int NegFrameSize = -FrameSize;
1032
1033 // Get processor type.
1034 bool IsPPC64 = Subtarget.isPPC64();
1035 // Get operating system
1166PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
1167 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1168 MachineBasicBlock::iterator MBBI = MBB.begin();
1169 MachineFrameInfo *MFI = MF.getFrameInfo();
1170 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1171 DebugLoc dl = DebugLoc::getUnknownLoc();
1172 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
1173 !MF.getFunction()->doesNotThrow() ||

--- 18 unchanged lines hidden (view full) ---

1192 determineFrameLayout(MF);
1193 unsigned FrameSize = MFI->getStackSize();
1194
1195 int NegFrameSize = -FrameSize;
1196
1197 // Get processor type.
1198 bool IsPPC64 = Subtarget.isPPC64();
1199 // Get operating system
1036 bool IsMachoABI = Subtarget.isMachoABI();
1200 bool isDarwinABI = Subtarget.isDarwinABI();
1037 // Check if the link register (LR) must be saved.
1038 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1039 bool MustSaveLR = FI->mustSaveLR();
1040 // Do we have a frame pointer for this function?
1041 bool HasFP = hasFP(MF) && FrameSize;
1042
1201 // Check if the link register (LR) must be saved.
1202 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1203 bool MustSaveLR = FI->mustSaveLR();
1204 // Do we have a frame pointer for this function?
1205 bool HasFP = hasFP(MF) && FrameSize;
1206
1043 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1044 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1207 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
1045
1208
1209 int FPOffset = 0;
1210 if (HasFP) {
1211 if (Subtarget.isSVR4ABI()) {
1212 MachineFrameInfo *FFI = MF.getFrameInfo();
1213 int FPIndex = FI->getFramePointerSaveIndex();
1214 assert(FPIndex && "No Frame Pointer Save Slot!");
1215 FPOffset = FFI->getObjectOffset(FPIndex);
1216 } else {
1217 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
1218 }
1219 }
1220
1046 if (IsPPC64) {
1047 if (MustSaveLR)
1048 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
1049
1050 if (HasFP)
1051 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1052 .addReg(PPC::X31)
1053 .addImm(FPOffset/4)

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1237 unsigned MaxAlign = MFI->getMaxAlignment();
1238
1239 // Get the number of bytes allocated from the FrameInfo.
1240 int FrameSize = MFI->getStackSize();
1241
1242 // Get processor type.
1243 bool IsPPC64 = Subtarget.isPPC64();
1244 // Get operating system
1221 if (IsPPC64) {
1222 if (MustSaveLR)
1223 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
1224
1225 if (HasFP)
1226 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1227 .addReg(PPC::X31)
1228 .addImm(FPOffset/4)

--- 183 unchanged lines hidden (view full) ---

1412 unsigned MaxAlign = MFI->getMaxAlignment();
1413
1414 // Get the number of bytes allocated from the FrameInfo.
1415 int FrameSize = MFI->getStackSize();
1416
1417 // Get processor type.
1418 bool IsPPC64 = Subtarget.isPPC64();
1419 // Get operating system
1245 bool IsMachoABI = Subtarget.isMachoABI();
1420 bool isDarwinABI = Subtarget.isDarwinABI();
1246 // Check if the link register (LR) has been saved.
1247 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1248 bool MustSaveLR = FI->mustSaveLR();
1249 // Do we have a frame pointer for this function?
1250 bool HasFP = hasFP(MF) && FrameSize;
1251
1421 // Check if the link register (LR) has been saved.
1422 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1423 bool MustSaveLR = FI->mustSaveLR();
1424 // Do we have a frame pointer for this function?
1425 bool HasFP = hasFP(MF) && FrameSize;
1426
1252 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1253 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1427 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
1428
1429 int FPOffset = 0;
1430 if (HasFP) {
1431 if (Subtarget.isSVR4ABI()) {
1432 MachineFrameInfo *FFI = MF.getFrameInfo();
1433 int FPIndex = FI->getFramePointerSaveIndex();
1434 assert(FPIndex && "No Frame Pointer Save Slot!");
1435 FPOffset = FFI->getObjectOffset(FPIndex);
1436 } else {
1437 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
1438 }
1439 }
1254
1255 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1256 RetOpcode == PPC::TCRETURNdi ||
1257 RetOpcode == PPC::TCRETURNai ||
1258 RetOpcode == PPC::TCRETURNri8 ||
1259 RetOpcode == PPC::TCRETURNdi8 ||
1260 RetOpcode == PPC::TCRETURNai8;
1261

--- 186 unchanged lines hidden --- 		1440
1441 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1442 RetOpcode == PPC::TCRETURNdi ||
1443 RetOpcode == PPC::TCRETURNai ||
1444 RetOpcode == PPC::TCRETURNri8 ||
1445 RetOpcode == PPC::TCRETURNdi8 ||
1446 RetOpcode == PPC::TCRETURNai8;
1447

--- 186 unchanged lines hidden ---