1//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "reginfo"
16#include "PPC.h"
17#include "PPCInstrBuilder.h"
18#include "PPCMachineFunctionInfo.h"
19#include "PPCRegisterInfo.h"
20#include "PPCFrameInfo.h"
21#include "PPCSubtarget.h"
22#include "llvm/CallingConv.h"
23#include "llvm/Constants.h"
24#include "llvm/Function.h"
25#include "llvm/Type.h"
26#include "llvm/CodeGen/ValueTypes.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineFrameInfo.h"
31#include "llvm/CodeGen/MachineLocation.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/RegisterScavenging.h"
34#include "llvm/Target/TargetFrameInfo.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/Support/CommandLine.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/MathExtras.h"
41#include "llvm/ADT/BitVector.h"
42#include "llvm/ADT/STLExtras.h"
43#include <cstdlib>
44using namespace llvm;
45
46// FIXME This disables some code that aligns the stack to a boundary
47// bigger than the default (16 bytes on Darwin) when there is a stack local
48// of greater alignment. This does not currently work, because the delta
49// between old and new stack pointers is added to offsets that reference
50// incoming parameters after the prolog is generated, and the code that
51// does that doesn't handle a variable delta. You don't want to do that
52// anyway; a better approach is to reserve another register that retains
53// to the incoming stack pointer, and reference parameters relative to that.
54#define ALIGN_STACK 0
55
56// FIXME (64-bit): Eventually enable by default.
57cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
58 cl::init(false),
59 cl::desc("Enable PPC32 register scavenger"),
60 cl::Hidden);
61cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
62 cl::init(false),
63 cl::desc("Enable PPC64 register scavenger"),
64 cl::Hidden);
65#define EnableRegisterScavenging \
66 ((EnablePPC32RS && !Subtarget.isPPC64()) || \
67 (EnablePPC64RS && Subtarget.isPPC64()))
68
69// FIXME (64-bit): Should be inlined.
70bool
71PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
72 return EnableRegisterScavenging;
73}
74
75/// getRegisterNumbering - Given the enum value for some register, e.g.
76/// PPC::F14, return the number that it corresponds to (e.g. 14).
77unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
78 using namespace PPC;
79 switch (RegEnum) {
80 case 0: return 0;
81 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
82 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
83 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
84 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
85 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
86 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
87 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
88 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
89 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
90 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
91 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
92 case R11: case X11: case F11: case V11: case CR2UN: return 11;
93 case R12: case X12: case F12: case V12: case CR3LT: return 12;
94 case R13: case X13: case F13: case V13: case CR3GT: return 13;
95 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
96 case R15: case X15: case F15: case V15: case CR3UN: return 15;
97 case R16: case X16: case F16: case V16: case CR4LT: return 16;
98 case R17: case X17: case F17: case V17: case CR4GT: return 17;
99 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
100 case R19: case X19: case F19: case V19: case CR4UN: return 19;
101 case R20: case X20: case F20: case V20: case CR5LT: return 20;
102 case R21: case X21: case F21: case V21: case CR5GT: return 21;
103 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
104 case R23: case X23: case F23: case V23: case CR5UN: return 23;
105 case R24: case X24: case F24: case V24: case CR6LT: return 24;
106 case R25: case X25: case F25: case V25: case CR6GT: return 25;
107 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
108 case R27: case X27: case F27: case V27: case CR6UN: return 27;
109 case R28: case X28: case F28: case V28: case CR7LT: return 28;
110 case R29: case X29: case F29: case V29: case CR7GT: return 29;
111 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
112 case R31: case X31: case F31: case V31: case CR7UN: return 31;
113 default:
114 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
115 abort();
116 }
117}
118
119PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
120 const TargetInstrInfo &tii)
121 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
122 Subtarget(ST), TII(tii) {
123 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
124 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
125 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
126 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
127 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
128 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
129 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
130 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
131
132 // 64-bit
133 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
134 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
135 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
136 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
137 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
138}
139
140/// getPointerRegClass - Return the register class to use to hold pointers.
141/// This is used for addressing modes.
142const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const {
143 if (Subtarget.isPPC64())
144 return &PPC::G8RCRegClass;
145 else
146 return &PPC::GPRCRegClass;
147}
148
149const unsigned*
150PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151 // 32-bit Darwin calling convention.
152 static const unsigned Darwin32_CalleeSavedRegs[] = {
153 PPC::R13, PPC::R14, PPC::R15,
154 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
155 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
156 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
157 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
158
159 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
160 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
161 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
162 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
163 PPC::F30, PPC::F31,
164
165 PPC::CR2, PPC::CR3, PPC::CR4,
166 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
167 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
168 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
169
170 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
171 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
172 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
173
174 PPC::LR, 0
175 };
176
177 static const unsigned SVR4_CalleeSavedRegs[] = {
178 PPC::R14, PPC::R15,
179 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
180 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
182 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
183
184 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
185 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
186 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
187 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
188 PPC::F30, PPC::F31,
189
190 PPC::CR2, PPC::CR3, PPC::CR4,
191
192 PPC::VRSAVE,
193
194 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
195 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
196 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
197
198 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
199 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
200 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
201
202 PPC::LR, 0
203 };
204 // 64-bit Darwin calling convention.
205 static const unsigned Darwin64_CalleeSavedRegs[] = {
206 PPC::X14, PPC::X15,
207 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
208 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
209 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
210 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
211
212 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
213 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
214 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
215 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
216 PPC::F30, PPC::F31,
217
218 PPC::CR2, PPC::CR3, PPC::CR4,
219 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
220 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
221 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
222
223 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
224 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
225 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
226
227 PPC::LR8, 0
228 };
229
230 if (Subtarget.isDarwinABI())
231 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
232 Darwin32_CalleeSavedRegs;
233
234 return SVR4_CalleeSavedRegs;
235}
236
237const TargetRegisterClass* const*
238PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
239 // 32-bit Darwin calling convention.
240 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
241 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
242 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
243 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
244 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
245 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
246
247 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
248 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
249 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
250 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
251 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
252
253 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
254
255 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
256 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
257 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
258
259 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
260 &PPC::CRBITRCRegClass,
261 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
262 &PPC::CRBITRCRegClass,
263 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
264 &PPC::CRBITRCRegClass,
265
266 &PPC::GPRCRegClass, 0
267 };
268
269 static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = {
270 &PPC::GPRCRegClass,&PPC::GPRCRegClass,
271 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
272 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
273 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
274 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
275
276 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
277 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
278 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
279 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
280 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
281
282 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
283
284 &PPC::VRSAVERCRegClass,
285
286 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
287 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
288 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
289
290 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
291 &PPC::CRBITRCRegClass,
292 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
293 &PPC::CRBITRCRegClass,
294 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
295 &PPC::CRBITRCRegClass,
296
297 &PPC::GPRCRegClass, 0
298 };
299
300 // 64-bit Darwin calling convention.
301 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
302 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
303 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
304 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
305 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
306 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
307
308 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
309 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
310 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
311 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
312 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
313
314 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
315
316 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
317 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
318 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
319
320 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
321 &PPC::CRBITRCRegClass,
322 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
323 &PPC::CRBITRCRegClass,
324 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
325 &PPC::CRBITRCRegClass,
326
327 &PPC::G8RCRegClass, 0
328 };
329
330 if (Subtarget.isDarwinABI())
331 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
332 Darwin32_CalleeSavedRegClasses;
333
334 return SVR4_CalleeSavedRegClasses;
335}
336
337// needsFP - Return true if the specified function should have a dedicated frame
338// pointer register. This is true if the function has variable sized allocas or
339// if frame pointer elimination is disabled.
340//
341static bool needsFP(const MachineFunction &MF) {
342 const MachineFrameInfo *MFI = MF.getFrameInfo();
343 return NoFramePointerElim || MFI->hasVarSizedObjects() ||
344 (PerformTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall());
345}
346
347static bool spillsCR(const MachineFunction &MF) {
348 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
349 return FuncInfo->isCRSpilled();
350}
351
352BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
353 BitVector Reserved(getNumRegs());
354 Reserved.set(PPC::R0);
355 Reserved.set(PPC::R1);
356 Reserved.set(PPC::LR);
357 Reserved.set(PPC::LR8);
358 Reserved.set(PPC::RM);
359
360 // The SVR4 ABI reserves r2 and r13
361 if (Subtarget.isSVR4ABI()) {
362 Reserved.set(PPC::R2); // System-reserved register
363 Reserved.set(PPC::R13); // Small Data Area pointer register
364 }
365
366 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
367 // that this is over conservative, as it also prevents allocation of R31 when
368 // the FP is not needed.
369 if (Subtarget.isPPC64()) {
370 Reserved.set(PPC::R13);
371 Reserved.set(PPC::R31);
372
373 if (!EnableRegisterScavenging)
374 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
375
376 Reserved.set(PPC::X0);
377 Reserved.set(PPC::X1);
378 Reserved.set(PPC::X13);
379 Reserved.set(PPC::X31);
380 }
381
382 if (needsFP(MF))
383 Reserved.set(PPC::R31);
384
385 return Reserved;
386}
387
388//===----------------------------------------------------------------------===//
389// Stack Frame Processing methods
390//===----------------------------------------------------------------------===//
391
392// hasFP - Return true if the specified function actually has a dedicated frame
393// pointer register. This is true if the function needs a frame pointer and has
394// a non-zero stack size.
395bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
396 const MachineFrameInfo *MFI = MF.getFrameInfo();
397 return MFI->getStackSize() && needsFP(MF);
398}
399
400/// MustSaveLR - Return true if this function requires that we save the LR
401/// register onto the stack in the prolog and restore it in the epilog of the
402/// function.
403static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
404 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
405
406 // We need a save/restore of LR if there is any def of LR (which is
407 // defined by calls, including the PIC setup sequence), or if there is
408 // some use of the LR stack slot (e.g. for builtin_return_address).
409 // (LR comes in 32 and 64 bit versions.)
410 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
411 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
412}
413
414
415
416void PPCRegisterInfo::
417eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
418 MachineBasicBlock::iterator I) const {
419 if (PerformTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) {
420 // Add (actually subtract) back the amount the callee popped on return.
421 if (int CalleeAmt = I->getOperand(1).getImm()) {
422 bool is64Bit = Subtarget.isPPC64();
423 CalleeAmt *= -1;
424 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
425 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
426 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
427 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
428 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
429 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
430 MachineInstr *MI = I;
431 DebugLoc dl = MI->getDebugLoc();
432
433 if (isInt16(CalleeAmt)) {
434 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
435 addImm(CalleeAmt);
436 } else {
437 MachineBasicBlock::iterator MBBI = I;
438 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
439 .addImm(CalleeAmt >> 16);
440 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
441 .addReg(TmpReg, RegState::Kill)
442 .addImm(CalleeAmt & 0xFFFF);
443 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
444 .addReg(StackReg)
445 .addReg(StackReg)
446 .addReg(TmpReg);
447 }
448 }
449 }
450 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
451 MBB.erase(I);
452}
453
454/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
455/// register first and then a spilled callee-saved register if that fails.
456static
457unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
458 const TargetRegisterClass *RC, int SPAdj) {
459 assert(RS && "Register scavenging must be on");
460 unsigned Reg = RS->FindUnusedReg(RC, true);
461 // FIXME: move ARM callee-saved reg scan to target independent code, then
462 // search for already spilled CS register here.
463 if (Reg == 0)
464 Reg = RS->scavengeRegister(RC, II, SPAdj);
465 return Reg;
466}
467
468/// lowerDynamicAlloc - Generate the code for allocating an object in the
469/// current frame. The sequence of code with be in the general form
470///
471/// addi R0, SP, \#frameSize ; get the address of the previous frame
472/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
473/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
474///
475void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
476 int SPAdj, RegScavenger *RS) const {
477 // Get the instruction.
478 MachineInstr &MI = *II;
479 // Get the instruction's basic block.
480 MachineBasicBlock &MBB = *MI.getParent();
481 // Get the basic block's function.
482 MachineFunction &MF = *MBB.getParent();
483 // Get the frame info.
484 MachineFrameInfo *MFI = MF.getFrameInfo();
485 // Determine whether 64-bit pointers are used.
486 bool LP64 = Subtarget.isPPC64();
487 DebugLoc dl = MI.getDebugLoc();
488
489 // Get the maximum call stack size.
490 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
491 // Get the total frame size.
492 unsigned FrameSize = MFI->getStackSize();
493
494 // Get stack alignments.
495 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
496 unsigned MaxAlign = MFI->getMaxAlignment();
497 assert(MaxAlign <= TargetAlign &&
498 "Dynamic alloca with large aligns not supported");
499
500 // Determine the previous frame's address. If FrameSize can't be
501 // represented as 16 bits or we need special alignment, then we load the
502 // previous frame's address from 0(SP). Why not do an addis of the hi?
503 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
504 // Constructing the constant and adding would take 3 instructions.
505 // Fortunately, a frame greater than 32K is rare.
506 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
507 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
508 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
509
510 // FIXME (64-bit): Use "findScratchRegister"
511 unsigned Reg;
512 if (EnableRegisterScavenging)
513 Reg = findScratchRegister(II, RS, RC, SPAdj);
514 else
515 Reg = PPC::R0;
516
517 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
518 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
519 .addReg(PPC::R31)
520 .addImm(FrameSize);
521 } else if (LP64) {
522 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
523 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
524 .addImm(0)
525 .addReg(PPC::X1);
526 else
527 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
528 .addImm(0)
529 .addReg(PPC::X1);
530 } else {
531 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
532 .addImm(0)
533 .addReg(PPC::R1);
534 }
535
536 // Grow the stack and update the stack pointer link, then determine the
537 // address of new allocated space.
538 if (LP64) {
539 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
540 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
541 .addReg(Reg, RegState::Kill)
542 .addReg(PPC::X1)
543 .addReg(MI.getOperand(1).getReg());
544 else
545 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
546 .addReg(PPC::X0, RegState::Kill)
547 .addReg(PPC::X1)
548 .addReg(MI.getOperand(1).getReg());
549
550 if (!MI.getOperand(1).isKill())
551 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
552 .addReg(PPC::X1)
553 .addImm(maxCallFrameSize);
554 else
555 // Implicitly kill the register.
556 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
557 .addReg(PPC::X1)
558 .addImm(maxCallFrameSize)
559 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
560 } else {
561 BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
562 .addReg(Reg, RegState::Kill)
563 .addReg(PPC::R1)
564 .addReg(MI.getOperand(1).getReg());
565
566 if (!MI.getOperand(1).isKill())
567 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
568 .addReg(PPC::R1)
569 .addImm(maxCallFrameSize);
570 else
571 // Implicitly kill the register.
572 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
573 .addReg(PPC::R1)
574 .addImm(maxCallFrameSize)
575 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
576 }
577
578 // Discard the DYNALLOC instruction.
579 MBB.erase(II);
580}
581
582/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
583/// reserving a whole register (R0), we scrounge for one here. This generates
584/// code like this:
585///
586/// mfcr rA ; Move the conditional register into GPR rA.
587/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
588/// stw rA, FI ; Store rA to the frame.
589///
590void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
591 unsigned FrameIndex, int SPAdj,
592 RegScavenger *RS) const {
593 // Get the instruction.
594 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
595 // Get the instruction's basic block.
596 MachineBasicBlock &MBB = *MI.getParent();
597 DebugLoc dl = MI.getDebugLoc();
598
599 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
600 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
601 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
602 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
603
604 // We need to store the CR in the low 4-bits of the saved value. First, issue
605 // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
606 if (!MI.getOperand(0).isKill())
607 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg);
608 else
609 // Implicitly kill the CR register.
610 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg)
611 .addReg(MI.getOperand(0).getReg(), RegState::ImplicitKill);
612
613 // If the saved register wasn't CR0, shift the bits left so that they are in
614 // CR0's slot.
615 unsigned SrcReg = MI.getOperand(0).getReg();
616 if (SrcReg != PPC::CR0)
617 // rlwinm rA, rA, ShiftBits, 0, 31.
618 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
619 .addReg(Reg, RegState::Kill)
620 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
621 .addImm(0)
622 .addImm(31);
623
624 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
625 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
626 FrameIndex);
627
628 // Discard the pseudo instruction.
629 MBB.erase(II);
630}
631
632void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
633 int SPAdj, RegScavenger *RS) const {
634 assert(SPAdj == 0 && "Unexpected");
635
636 // Get the instruction.
637 MachineInstr &MI = *II;
638 // Get the instruction's basic block.
639 MachineBasicBlock &MBB = *MI.getParent();
640 // Get the basic block's function.
641 MachineFunction &MF = *MBB.getParent();
642 // Get the frame info.
643 MachineFrameInfo *MFI = MF.getFrameInfo();
644 DebugLoc dl = MI.getDebugLoc();
645
646 // Find out which operand is the frame index.
647 unsigned FIOperandNo = 0;
648 while (!MI.getOperand(FIOperandNo).isFI()) {
649 ++FIOperandNo;
650 assert(FIOperandNo != MI.getNumOperands() &&
651 "Instr doesn't have FrameIndex operand!");
652 }
653 // Take into account whether it's an add or mem instruction
654 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
655 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
656 OffsetOperandNo = FIOperandNo-1;
657
658 // Get the frame index.
659 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
660
661 // Get the frame pointer save index. Users of this index are primarily
662 // DYNALLOC instructions.
663 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
664 int FPSI = FI->getFramePointerSaveIndex();
665 // Get the instruction opcode.
666 unsigned OpC = MI.getOpcode();
667
668 // Special case for dynamic alloca.
669 if (FPSI && FrameIndex == FPSI &&
670 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
671 lowerDynamicAlloc(II, SPAdj, RS);
672 return;
673 }
674
675 // Special case for pseudo-op SPILL_CR.
676 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
677 if (OpC == PPC::SPILL_CR) {
678 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
679 return;
680 }
681
682 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
683 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
684 false);
685
686 // Figure out if the offset in the instruction is shifted right two bits. This
687 // is true for instructions like "STD", which the machine implicitly adds two
688 // low zeros to.
689 bool isIXAddr = false;
690 switch (OpC) {
691 case PPC::LWA:
692 case PPC::LD:
693 case PPC::STD:
694 case PPC::STD_32:
695 isIXAddr = true;
696 break;
697 }
698
699 // Now add the frame object offset to the offset from r1.
700 int Offset = MFI->getObjectOffset(FrameIndex);
701 if (!isIXAddr)
702 Offset += MI.getOperand(OffsetOperandNo).getImm();
703 else
704 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
705
706 // If we're not using a Frame Pointer that has been set to the value of the
707 // SP before having the stack size subtracted from it, then add the stack size
708 // to Offset to get the correct offset.
709 Offset += MFI->getStackSize();
710
711 // If we can, encode the offset directly into the instruction. If this is a
712 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
713 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
714 // clear can be encoded. This is extremely uncommon, because normally you
715 // only "std" to a stack slot that is at least 4-byte aligned, but it can
716 // happen in invalid code.
717 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
718 if (isIXAddr)
719 Offset >>= 2; // The actual encoded value has the low two bits zero.
720 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
721 return;
722 }
723
724 // The offset doesn't fit into a single register, scavenge one to build the
725 // offset in.
726 // FIXME: figure out what SPAdj is doing here.
727
728 // FIXME (64-bit): Use "findScratchRegister".
729 unsigned SReg;
730 if (EnableRegisterScavenging)
731 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
732 else
733 SReg = PPC::R0;
734
735 // Insert a set of rA with the full offset value before the ld, st, or add
736 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
737 .addImm(Offset >> 16);
738 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
739 .addReg(SReg, RegState::Kill)
740 .addImm(Offset);
741
742 // Convert into indexed form of the instruction:
743 //
744 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
745 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
746 unsigned OperandBase;
747
748 if (OpC != TargetInstrInfo::INLINEASM) {
749 assert(ImmToIdxMap.count(OpC) &&
750 "No indexed form of load or store available!");
751 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
752 MI.setDesc(TII.get(NewOpcode));
753 OperandBase = 1;
754 } else {
755 OperandBase = OffsetOperandNo;
756 }
757
758 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
759 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
760 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
761}
762
763/// VRRegNo - Map from a numbered VR register to its enum value.
764///
765static const unsigned short VRRegNo[] = {
766 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
767 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
768 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
769 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
770};
771
772/// RemoveVRSaveCode - We have found that this function does not need any code
773/// to manipulate the VRSAVE register, even though it uses vector registers.
774/// This can happen when the only registers used are known to be live in or out
775/// of the function. Remove all of the VRSAVE related code from the function.
776static void RemoveVRSaveCode(MachineInstr *MI) {
777 MachineBasicBlock *Entry = MI->getParent();
778 MachineFunction *MF = Entry->getParent();
779
780 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
781 MachineBasicBlock::iterator MBBI = MI;
782 ++MBBI;
783 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
784 MBBI->eraseFromParent();
785
786 bool RemovedAllMTVRSAVEs = true;
787 // See if we can find and remove the MTVRSAVE instruction from all of the
788 // epilog blocks.
789 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
790 // If last instruction is a return instruction, add an epilogue
791 if (!I->empty() && I->back().getDesc().isReturn()) {
792 bool FoundIt = false;
793 for (MBBI = I->end(); MBBI != I->begin(); ) {
794 --MBBI;
795 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
796 MBBI->eraseFromParent(); // remove it.
797 FoundIt = true;
798 break;
799 }
800 }
801 RemovedAllMTVRSAVEs &= FoundIt;
802 }
803 }
804
805 // If we found and removed all MTVRSAVE instructions, remove the read of
806 // VRSAVE as well.
807 if (RemovedAllMTVRSAVEs) {
808 MBBI = MI;
809 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
810 --MBBI;
811 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
812 MBBI->eraseFromParent();
813 }
814
815 // Finally, nuke the UPDATE_VRSAVE.
816 MI->eraseFromParent();
817}
818
819// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
820// instruction selector. Based on the vector registers that have been used,
821// transform this into the appropriate ORI instruction.
822static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
823 MachineFunction *MF = MI->getParent()->getParent();
824 DebugLoc dl = MI->getDebugLoc();
825
826 unsigned UsedRegMask = 0;
827 for (unsigned i = 0; i != 32; ++i)
828 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
829 UsedRegMask |= 1 << (31-i);
830
831 // Live in and live out values already must be in the mask, so don't bother
832 // marking them.
833 for (MachineRegisterInfo::livein_iterator
834 I = MF->getRegInfo().livein_begin(),
835 E = MF->getRegInfo().livein_end(); I != E; ++I) {
836 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
837 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
838 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
839 }
840 for (MachineRegisterInfo::liveout_iterator
841 I = MF->getRegInfo().liveout_begin(),
842 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
843 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
844 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
845 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
846 }
847
848 // If no registers are used, turn this into a copy.
849 if (UsedRegMask == 0) {
850 // Remove all VRSAVE code.
851 RemoveVRSaveCode(MI);
852 return;
853 }
854
855 unsigned SrcReg = MI->getOperand(1).getReg();
856 unsigned DstReg = MI->getOperand(0).getReg();
857
858 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
859 if (DstReg != SrcReg)
860 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
861 .addReg(SrcReg)
862 .addImm(UsedRegMask);
863 else
864 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
865 .addReg(SrcReg, RegState::Kill)
866 .addImm(UsedRegMask);
867 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
868 if (DstReg != SrcReg)
869 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
870 .addReg(SrcReg)
871 .addImm(UsedRegMask >> 16);
872 else
873 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
874 .addReg(SrcReg, RegState::Kill)
875 .addImm(UsedRegMask >> 16);
876 } else {
877 if (DstReg != SrcReg)
878 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
879 .addReg(SrcReg)
880 .addImm(UsedRegMask >> 16);
881 else
882 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
883 .addReg(SrcReg, RegState::Kill)
884 .addImm(UsedRegMask >> 16);
885
886 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
887 .addReg(DstReg, RegState::Kill)
888 .addImm(UsedRegMask & 0xFFFF);
889 }
890
891 // Remove the old UPDATE_VRSAVE instruction.
892 MI->eraseFromParent();
893}
894
895/// determineFrameLayout - Determine the size of the frame and maximum call
896/// frame size.
897void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
898 MachineFrameInfo *MFI = MF.getFrameInfo();
899
900 // Get the number of bytes to allocate from the FrameInfo
901 unsigned FrameSize = MFI->getStackSize();
902
903 // Get the alignments provided by the target, and the maximum alignment
904 // (if any) of the fixed frame objects.
905 unsigned MaxAlign = MFI->getMaxAlignment();
906 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
907 unsigned AlignMask = TargetAlign - 1; //
908
909 // If we are a leaf function, and use up to 224 bytes of stack space,
910 // don't have a frame pointer, calls, or dynamic alloca then we do not need
911 // to adjust the stack pointer (we fit in the Red Zone).
912 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
913 // FIXME SVR4 The SVR4 ABI has no red zone.
914 if (!DisableRedZone &&
915 FrameSize <= 224 && // Fits in red zone.
916 !MFI->hasVarSizedObjects() && // No dynamic alloca.
917 !MFI->hasCalls() && // No calls.
918 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
919 // No need for frame
920 MFI->setStackSize(0);
921 return;
922 }
923
924 // Get the maximum call frame size of all the calls.
925 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
926
927 // Maximum call frame needs to be at least big enough for linkage and 8 args.
928 unsigned minCallFrameSize =
929 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
930 Subtarget.isDarwinABI());
931 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
932
933 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
934 // that allocations will be aligned.
935 if (MFI->hasVarSizedObjects())
936 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
937
938 // Update maximum call frame size.
939 MFI->setMaxCallFrameSize(maxCallFrameSize);
940
941 // Include call frame size in total.
942 FrameSize += maxCallFrameSize;
943
944 // Make sure the frame is aligned.
945 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
946
947 // Update frame info.
948 MFI->setStackSize(FrameSize);
949}
950
951void
952PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
953 RegScavenger *RS) const {
954 // Save and clear the LR state.
955 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
956 unsigned LR = getRARegister();
957 FI->setMustSaveLR(MustSaveLR(MF, LR));
958 MF.getRegInfo().setPhysRegUnused(LR);
959
960 // Save R31 if necessary
961 int FPSI = FI->getFramePointerSaveIndex();
962 bool IsPPC64 = Subtarget.isPPC64();
963 bool IsSVR4ABI = Subtarget.isSVR4ABI();
964 bool isDarwinABI = Subtarget.isDarwinABI();
965 MachineFrameInfo *MFI = MF.getFrameInfo();
966
967 // If the frame pointer save index hasn't been defined yet.
968 if (!FPSI && needsFP(MF) && IsSVR4ABI) {
969 // Find out what the fix offset of the frame pointer save area.
970 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
971 isDarwinABI);
972 // Allocate the frame index for frame pointer save area.
973 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
974 // Save the result.
975 FI->setFramePointerSaveIndex(FPSI);
976 }
977
978 // Reserve stack space to move the linkage area to in case of a tail call.
979 int TCSPDelta = 0;
980 if (PerformTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
981 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta);
982 }
983
984 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
985 // a large stack, which will require scavenging a register to materialize a
986 // large offset.
987 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
988 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
989 // r0 for now.
990
991 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
992 if (needsFP(MF) || spillsCR(MF)) {
993 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
994 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
995 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
996 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
997 RC->getAlignment()));
998 }
999}
1000
1001void
1002PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
1003 const {
1004 // Early exit if not using the SVR4 ABI.
1005 if (!Subtarget.isSVR4ABI()) {
1006 return;
1007 }
1008
1009 // Get callee saved register information.
1010 MachineFrameInfo *FFI = MF.getFrameInfo();
1011 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1012
1013 // Early exit if no callee saved registers are modified!
1014 if (CSI.empty() && !needsFP(MF)) {
1015 return;
1016 }
1017
1018 unsigned MinGPR = PPC::R31;
1019 unsigned MinFPR = PPC::F31;
1020 unsigned MinVR = PPC::V31;
1021
1022 bool HasGPSaveArea = false;
1023 bool HasFPSaveArea = false;
1024 bool HasCRSaveArea = false;
1025 bool HasVRSAVESaveArea = false;
1026 bool HasVRSaveArea = false;
1027
1028 SmallVector<CalleeSavedInfo, 18> GPRegs;
1029 SmallVector<CalleeSavedInfo, 18> FPRegs;
1030 SmallVector<CalleeSavedInfo, 18> VRegs;
1031
1032 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1033 unsigned Reg = CSI[i].getReg();
1034 const TargetRegisterClass *RC = CSI[i].getRegClass();
1035
1036 if (RC == PPC::GPRCRegisterClass) {
1037 HasGPSaveArea = true;
1038
1039 GPRegs.push_back(CSI[i]);
1040
1041 if (Reg < MinGPR) {
1042 MinGPR = Reg;
1043 }
1044 } else if (RC == PPC::F8RCRegisterClass) {
1045 HasFPSaveArea = true;
1046
1047 FPRegs.push_back(CSI[i]);
1048
1049 if (Reg < MinFPR) {
1050 MinFPR = Reg;
1051 }
1052// FIXME SVR4: Disable CR save area for now.
1053 } else if ( RC == PPC::CRBITRCRegisterClass
1054 || RC == PPC::CRRCRegisterClass) {
1055// HasCRSaveArea = true;
1056 } else if (RC == PPC::VRSAVERCRegisterClass) {
1057 HasVRSAVESaveArea = true;
1058 } else if (RC == PPC::VRRCRegisterClass) {
1059 HasVRSaveArea = true;
1060
1061 VRegs.push_back(CSI[i]);
1062
1063 if (Reg < MinVR) {
1064 MinVR = Reg;
1065 }
1066 } else {
1067 assert(0 && "Unknown RegisterClass!");
1068 }
1069 }
1070
1071 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1072
1073 int64_t LowerBound = 0;
1074
1075 // Take into account stack space reserved for tail calls.
1076 int TCSPDelta = 0;
1077 if (PerformTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1078 LowerBound = TCSPDelta;
1079 }
1080
1081 // The Floating-point register save area is right below the back chain word
1082 // of the previous stack frame.
1083 if (HasFPSaveArea) {
1084 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1085 int FI = FPRegs[i].getFrameIdx();
1086
1087 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1088 }
1089
1090 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8;
1091 }
1092
1093 // Check whether the frame pointer register is allocated. If so, make sure it
1094 // is spilled to the correct offset.
1095 if (needsFP(MF)) {
1096 HasGPSaveArea = true;
1097
1098 int FI = PFI->getFramePointerSaveIndex();
1099 assert(FI && "No Frame Pointer Save Slot!");
1100
1101 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1102 }
1103
1104 // General register save area starts right below the Floating-point
1105 // register save area.
1106 if (HasGPSaveArea) {
1107 // Move general register save area spill slots down, taking into account
1108 // the size of the Floating-point register save area.
1109 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1110 int FI = GPRegs[i].getFrameIdx();
1111
1112 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1113 }
1114
1115 LowerBound -= (31 - getRegisterNumbering(MinGPR) + 1) * 4;
1116 }
1117
1118 // The CR save area is below the general register save area.
1119 if (HasCRSaveArea) {
1120 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1121 // which have the CR/CRBIT register class?
1122 // Adjust the frame index of the CR spill slot.
1123 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1124 const TargetRegisterClass *RC = CSI[i].getRegClass();
1125
1126 if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) {
1127 int FI = CSI[i].getFrameIdx();
1128
1129 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1130 }
1131 }
1132
1133 LowerBound -= 4; // The CR save area is always 4 bytes long.
1134 }
1135
1136 if (HasVRSAVESaveArea) {
1137 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1138 // which have the VRSAVE register class?
1139 // Adjust the frame index of the VRSAVE spill slot.
1140 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1141 const TargetRegisterClass *RC = CSI[i].getRegClass();
1142
1143 if (RC == PPC::VRSAVERCRegisterClass) {
1144 int FI = CSI[i].getFrameIdx();
1145
1146 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1147 }
1148 }
1149
1150 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1151 }
1152
1153 if (HasVRSaveArea) {
1154 // Insert alignment padding, we need 16-byte alignment.
1155 LowerBound = (LowerBound - 15) & ~(15);
1156
1157 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1158 int FI = VRegs[i].getFrameIdx();
1159
1160 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1161 }
1162 }
1163}
1164
1165void
1166PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
1167 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1168 MachineBasicBlock::iterator MBBI = MBB.begin();
1169 MachineFrameInfo *MFI = MF.getFrameInfo();
1170 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1171 DebugLoc dl = DebugLoc::getUnknownLoc();
1172 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
1173 !MF.getFunction()->doesNotThrow() ||
1174 UnwindTablesMandatory;
1175
1176 // Prepare for frame info.
1177 unsigned FrameLabelId = 0;
1178
1179 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
1180 // process it.
1181 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
1182 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
1183 HandleVRSaveUpdate(MBBI, TII);
1184 break;
1185 }
1186 }
1187
1188 // Move MBBI back to the beginning of the function.
1189 MBBI = MBB.begin();
1190
1191 // Work out frame sizes.
1192 determineFrameLayout(MF);
1193 unsigned FrameSize = MFI->getStackSize();
1194
1195 int NegFrameSize = -FrameSize;
1196
1197 // Get processor type.
1198 bool IsPPC64 = Subtarget.isPPC64();
1199 // Get operating system
1200 bool isDarwinABI = Subtarget.isDarwinABI();
1201 // Check if the link register (LR) must be saved.
1202 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1203 bool MustSaveLR = FI->mustSaveLR();
1204 // Do we have a frame pointer for this function?
1205 bool HasFP = hasFP(MF) && FrameSize;
1206
1207 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
1208
1209 int FPOffset = 0;
1210 if (HasFP) {
1211 if (Subtarget.isSVR4ABI()) {
1212 MachineFrameInfo *FFI = MF.getFrameInfo();
1213 int FPIndex = FI->getFramePointerSaveIndex();
1214 assert(FPIndex && "No Frame Pointer Save Slot!");
1215 FPOffset = FFI->getObjectOffset(FPIndex);
1216 } else {
1217 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
1218 }
1219 }
1220
1221 if (IsPPC64) {
1222 if (MustSaveLR)
1223 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
1224
1225 if (HasFP)
1226 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1227 .addReg(PPC::X31)
1228 .addImm(FPOffset/4)
1229 .addReg(PPC::X1);
1230
1231 if (MustSaveLR)
1232 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1233 .addReg(PPC::X0)
1234 .addImm(LROffset / 4)
1235 .addReg(PPC::X1);
1236 } else {
1237 if (MustSaveLR)
1238 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
1239
1240 if (HasFP)
1241 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
1242 .addReg(PPC::R31)
1243 .addImm(FPOffset)
1244 .addReg(PPC::R1);
1245
1246 if (MustSaveLR)
1247 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
1248 .addReg(PPC::R0)
1249 .addImm(LROffset)
1250 .addReg(PPC::R1);
1251 }
1252
1253 // Skip if a leaf routine.
1254 if (!FrameSize) return;
1255
1256 // Get stack alignments.
1257 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1258 unsigned MaxAlign = MFI->getMaxAlignment();
1259
1260 if (needsFrameMoves) {
1261 // Mark effective beginning of when frame pointer becomes valid.
1262 FrameLabelId = MMI->NextLabelID();
1263 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
1264 }
1265
1266 // Adjust stack pointer: r1 += NegFrameSize.
1267 // If there is a preferred stack alignment, align R1 now
1268 if (!IsPPC64) {
1269 // PPC32.
1270 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1271 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1272 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1273
1274 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
1275 .addReg(PPC::R1)
1276 .addImm(0)
1277 .addImm(32 - Log2_32(MaxAlign))
1278 .addImm(31);
1279 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
1280 .addReg(PPC::R0, RegState::Kill)
1281 .addImm(NegFrameSize);
1282 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
1283 .addReg(PPC::R1)
1284 .addReg(PPC::R1)
1285 .addReg(PPC::R0);
1286 } else if (isInt16(NegFrameSize)) {
1287 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
1288 .addReg(PPC::R1)
1289 .addImm(NegFrameSize)
1290 .addReg(PPC::R1);
1291 } else {
1292 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
1293 .addImm(NegFrameSize >> 16);
1294 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
1295 .addReg(PPC::R0, RegState::Kill)
1296 .addImm(NegFrameSize & 0xFFFF);
1297 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
1298 .addReg(PPC::R1)
1299 .addReg(PPC::R1)
1300 .addReg(PPC::R0);
1301 }
1302 } else { // PPC64.
1303 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1304 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1305 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1306
1307 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
1308 .addReg(PPC::X1)
1309 .addImm(0)
1310 .addImm(64 - Log2_32(MaxAlign));
1311 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
1312 .addReg(PPC::X0)
1313 .addImm(NegFrameSize);
1314 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
1315 .addReg(PPC::X1)
1316 .addReg(PPC::X1)
1317 .addReg(PPC::X0);
1318 } else if (isInt16(NegFrameSize)) {
1319 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
1320 .addReg(PPC::X1)
1321 .addImm(NegFrameSize / 4)
1322 .addReg(PPC::X1);
1323 } else {
1324 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
1325 .addImm(NegFrameSize >> 16);
1326 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
1327 .addReg(PPC::X0, RegState::Kill)
1328 .addImm(NegFrameSize & 0xFFFF);
1329 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
1330 .addReg(PPC::X1)
1331 .addReg(PPC::X1)
1332 .addReg(PPC::X0);
1333 }
1334 }
1335
1336 if (needsFrameMoves) {
1337 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1338
1339 if (NegFrameSize) {
1340 // Show update of SP.
1341 MachineLocation SPDst(MachineLocation::VirtualFP);
1342 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1343 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1344 } else {
1345 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1346 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1347 }
1348
1349 if (HasFP) {
1350 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1351 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1352 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1353 }
1354
1355 // Add callee saved registers to move list.
1356 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1357 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1358 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1359 unsigned Reg = CSI[I].getReg();
1360 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1361 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1362 MachineLocation CSSrc(Reg);
1363 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1364 }
1365
1366 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1367 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1368 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1369
1370 // Mark effective beginning of when frame pointer is ready.
1371 unsigned ReadyLabelId = MMI->NextLabelID();
1372 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
1373
1374 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1375 (IsPPC64 ? PPC::X1 : PPC::R1));
1376 MachineLocation FPSrc(MachineLocation::VirtualFP);
1377 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1378 }
1379
1380 // If there is a frame pointer, copy R1 into R31
1381 if (HasFP) {
1382 if (!IsPPC64) {
1383 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
1384 .addReg(PPC::R1)
1385 .addReg(PPC::R1);
1386 } else {
1387 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
1388 .addReg(PPC::X1)
1389 .addReg(PPC::X1);
1390 }
1391 }
1392}
1393
1394void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1395 MachineBasicBlock &MBB) const {
1396 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1397 unsigned RetOpcode = MBBI->getOpcode();
1398 DebugLoc dl = DebugLoc::getUnknownLoc();
1399
1400 assert( (RetOpcode == PPC::BLR ||
1401 RetOpcode == PPC::TCRETURNri ||
1402 RetOpcode == PPC::TCRETURNdi ||
1403 RetOpcode == PPC::TCRETURNai ||
1404 RetOpcode == PPC::TCRETURNri8 ||
1405 RetOpcode == PPC::TCRETURNdi8 ||
1406 RetOpcode == PPC::TCRETURNai8) &&
1407 "Can only insert epilog into returning blocks");
1408
1409 // Get alignment info so we know how to restore r1
1410 const MachineFrameInfo *MFI = MF.getFrameInfo();
1411 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1412 unsigned MaxAlign = MFI->getMaxAlignment();
1413
1414 // Get the number of bytes allocated from the FrameInfo.
1415 int FrameSize = MFI->getStackSize();
1416
1417 // Get processor type.
1418 bool IsPPC64 = Subtarget.isPPC64();
1419 // Get operating system
1420 bool isDarwinABI = Subtarget.isDarwinABI();
1421 // Check if the link register (LR) has been saved.
1422 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1423 bool MustSaveLR = FI->mustSaveLR();
1424 // Do we have a frame pointer for this function?
1425 bool HasFP = hasFP(MF) && FrameSize;
1426
1427 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
1428
1429 int FPOffset = 0;
1430 if (HasFP) {
1431 if (Subtarget.isSVR4ABI()) {
1432 MachineFrameInfo *FFI = MF.getFrameInfo();
1433 int FPIndex = FI->getFramePointerSaveIndex();
1434 assert(FPIndex && "No Frame Pointer Save Slot!");
1435 FPOffset = FFI->getObjectOffset(FPIndex);
1436 } else {
1437 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
1438 }
1439 }
1440
1441 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1442 RetOpcode == PPC::TCRETURNdi ||
1443 RetOpcode == PPC::TCRETURNai ||
1444 RetOpcode == PPC::TCRETURNri8 ||
1445 RetOpcode == PPC::TCRETURNdi8 ||
1446 RetOpcode == PPC::TCRETURNai8;
1447
1448 if (UsesTCRet) {
1449 int MaxTCRetDelta = FI->getTailCallSPDelta();
1450 MachineOperand &StackAdjust = MBBI->getOperand(1);
1451 assert(StackAdjust.isImm() && "Expecting immediate value.");
1452 // Adjust stack pointer.
1453 int StackAdj = StackAdjust.getImm();
1454 int Delta = StackAdj - MaxTCRetDelta;
1455 assert((Delta >= 0) && "Delta must be positive");
1456 if (MaxTCRetDelta>0)
1457 FrameSize += (StackAdj +Delta);
1458 else
1459 FrameSize += StackAdj;
1460 }
1461
1462 if (FrameSize) {
1463 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1464 // on entry to the function. Add this offset back now.
1465 if (!IsPPC64) {
1466 // If this function contained a fastcc call and PerformTailCallOpt is
1467 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1468 // call which invalidates the stack pointer value in SP(0). So we use the
1469 // value of R31 in this case.
1470 if (FI->hasFastCall() && isInt16(FrameSize)) {
1471 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1472 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
1473 .addReg(PPC::R31).addImm(FrameSize);
1474 } else if(FI->hasFastCall()) {
1475 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
1476 .addImm(FrameSize >> 16);
1477 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
1478 .addReg(PPC::R0, RegState::Kill)
1479 .addImm(FrameSize & 0xFFFF);
1480 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
1481 .addReg(PPC::R1)
1482 .addReg(PPC::R31)
1483 .addReg(PPC::R0);
1484 } else if (isInt16(FrameSize) &&
1485 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
1486 !MFI->hasVarSizedObjects()) {
1487 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
1488 .addReg(PPC::R1).addImm(FrameSize);
1489 } else {
1490 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
1491 .addImm(0).addReg(PPC::R1);
1492 }
1493 } else {
1494 if (FI->hasFastCall() && isInt16(FrameSize)) {
1495 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1496 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
1497 .addReg(PPC::X31).addImm(FrameSize);
1498 } else if(FI->hasFastCall()) {
1499 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
1500 .addImm(FrameSize >> 16);
1501 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
1502 .addReg(PPC::X0, RegState::Kill)
1503 .addImm(FrameSize & 0xFFFF);
1504 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
1505 .addReg(PPC::X1)
1506 .addReg(PPC::X31)
1507 .addReg(PPC::X0);
1508 } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1509 !MFI->hasVarSizedObjects()) {
1510 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
1511 .addReg(PPC::X1).addImm(FrameSize);
1512 } else {
1513 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
1514 .addImm(0).addReg(PPC::X1);
1515 }
1516 }
1517 }
1518
1519 if (IsPPC64) {
1520 if (MustSaveLR)
1521 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
1522 .addImm(LROffset/4).addReg(PPC::X1);
1523
1524 if (HasFP)
1525 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
1526 .addImm(FPOffset/4).addReg(PPC::X1);
1527
1528 if (MustSaveLR)
1529 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1530 } else {
1531 if (MustSaveLR)
1532 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
1533 .addImm(LROffset).addReg(PPC::R1);
1534
1535 if (HasFP)
1536 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
1537 .addImm(FPOffset).addReg(PPC::R1);
1538
1539 if (MustSaveLR)
1540 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
1541 }
1542
1543 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1544 // call optimization
1545 if (PerformTailCallOpt && RetOpcode == PPC::BLR &&
1546 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1547 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1548 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1549 unsigned StackReg = IsPPC64 ? PPC::X1 : PPC::R1;
1550 unsigned FPReg = IsPPC64 ? PPC::X31 : PPC::R31;
1551 unsigned TmpReg = IsPPC64 ? PPC::X0 : PPC::R0;
1552 unsigned ADDIInstr = IsPPC64 ? PPC::ADDI8 : PPC::ADDI;
1553 unsigned ADDInstr = IsPPC64 ? PPC::ADD8 : PPC::ADD4;
1554 unsigned LISInstr = IsPPC64 ? PPC::LIS8 : PPC::LIS;
1555 unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI;
1556
1557 if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) {
1558 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
1559 .addReg(StackReg).addImm(CallerAllocatedAmt);
1560 } else {
1561 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1562 .addImm(CallerAllocatedAmt >> 16);
1563 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1564 .addReg(TmpReg, RegState::Kill)
1565 .addImm(CallerAllocatedAmt & 0xFFFF);
1566 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
1567 .addReg(StackReg)
1568 .addReg(FPReg)
1569 .addReg(TmpReg);
1570 }
1571 } else if (RetOpcode == PPC::TCRETURNdi) {
1572 MBBI = prior(MBB.end());
1573 MachineOperand &JumpTarget = MBBI->getOperand(0);
1574 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1575 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1576 } else if (RetOpcode == PPC::TCRETURNri) {
1577 MBBI = prior(MBB.end());
1578 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1579 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1580 } else if (RetOpcode == PPC::TCRETURNai) {
1581 MBBI = prior(MBB.end());
1582 MachineOperand &JumpTarget = MBBI->getOperand(0);
1583 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1584 } else if (RetOpcode == PPC::TCRETURNdi8) {
1585 MBBI = prior(MBB.end());
1586 MachineOperand &JumpTarget = MBBI->getOperand(0);
1587 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1588 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1589 } else if (RetOpcode == PPC::TCRETURNri8) {
1590 MBBI = prior(MBB.end());
1591 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1592 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1593 } else if (RetOpcode == PPC::TCRETURNai8) {
1594 MBBI = prior(MBB.end());
1595 MachineOperand &JumpTarget = MBBI->getOperand(0);
1596 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1597 }
1598}
1599
1600unsigned PPCRegisterInfo::getRARegister() const {
1601 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1602}
1603
1604unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1605 if (!Subtarget.isPPC64())
1606 return hasFP(MF) ? PPC::R31 : PPC::R1;
1607 else
1608 return hasFP(MF) ? PPC::X31 : PPC::X1;
1609}
1610
1611void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1612 const {
1613 // Initial state of the frame pointer is R1.
1614 MachineLocation Dst(MachineLocation::VirtualFP);
1615 MachineLocation Src(PPC::R1, 0);
1616 Moves.push_back(MachineMove(0, Dst, Src));
1617}
1618
1619unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1620 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1621}
1622
1623unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1624 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1625}
1626
1627int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1628 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1629 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1630}
1631
1632#include "PPCGenRegisterInfo.inc"
1633