1//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MIPS implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-reg-info"
15
16#include "Mips.h"
17#include "MipsSubtarget.h"
18#include "MipsRegisterInfo.h"
19#include "MipsMachineFunction.h"
20#include "llvm/Constants.h"
21#include "llvm/Type.h"
22#include "llvm/Function.h"
23#include "llvm/CodeGen/ValueTypes.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineLocation.h"
28#include "llvm/Target/TargetFrameInfo.h"
29#include "llvm/Target/TargetMachine.h"
30#include "llvm/Target/TargetOptions.h"
31#include "llvm/Target/TargetInstrInfo.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
36#include "llvm/ADT/BitVector.h"
37#include "llvm/ADT/STLExtras.h"
38
39using namespace llvm;
40
41MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
42 const TargetInstrInfo &tii)
43 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44 Subtarget(ST), TII(tii) {}
45
46/// getRegisterNumbering - Given the enum value for some register, e.g.
47/// Mips::RA, return the number that it corresponds to (e.g. 31).
48unsigned MipsRegisterInfo::
49getRegisterNumbering(unsigned RegEnum)
50{
51 switch (RegEnum) {
52 case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
53 case Mips::AT : case Mips::F1 : return 1;
54 case Mips::V0 : case Mips::F2 : case Mips::D1 : return 2;
55 case Mips::V1 : case Mips::F3 : return 3;
56 case Mips::A0 : case Mips::F4 : case Mips::D2 : return 4;
57 case Mips::A1 : case Mips::F5 : return 5;
58 case Mips::A2 : case Mips::F6 : case Mips::D3 : return 6;
59 case Mips::A3 : case Mips::F7 : return 7;
60 case Mips::T0 : case Mips::F8 : case Mips::D4 : return 8;
61 case Mips::T1 : case Mips::F9 : return 9;
62 case Mips::T2 : case Mips::F10: case Mips::D5: return 10;
63 case Mips::T3 : case Mips::F11: return 11;
64 case Mips::T4 : case Mips::F12: case Mips::D6: return 12;
65 case Mips::T5 : case Mips::F13: return 13;
66 case Mips::T6 : case Mips::F14: case Mips::D7: return 14;
67 case Mips::T7 : case Mips::F15: return 15;
68 case Mips::T8 : case Mips::F16: case Mips::D8: return 16;
69 case Mips::T9 : case Mips::F17: return 17;
70 case Mips::S0 : case Mips::F18: case Mips::D9: return 18;
71 case Mips::S1 : case Mips::F19: return 19;
72 case Mips::S2 : case Mips::F20: case Mips::D10: return 20;
73 case Mips::S3 : case Mips::F21: return 21;
74 case Mips::S4 : case Mips::F22: case Mips::D11: return 22;
75 case Mips::S5 : case Mips::F23: return 23;
76 case Mips::S6 : case Mips::F24: case Mips::D12: return 24;
77 case Mips::S7 : case Mips::F25: return 25;
78 case Mips::K0 : case Mips::F26: case Mips::D13: return 26;
79 case Mips::K1 : case Mips::F27: return 27;
80 case Mips::GP : case Mips::F28: case Mips::D14: return 28;
81 case Mips::SP : case Mips::F29: return 29;
82 case Mips::FP : case Mips::F30: case Mips::D15: return 30;
83 case Mips::RA : case Mips::F31: return 31;
84 default: llvm_unreachable("Unknown register number!");
85 }
86 return 0; // Not reached
87}
88
89unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
90
91//===----------------------------------------------------------------------===//
92// Callee Saved Registers methods
93//===----------------------------------------------------------------------===//
94
95/// Mips Callee Saved Registers
96const unsigned* MipsRegisterInfo::
97getCalleeSavedRegs(const MachineFunction *MF) const
98{
99 // Mips callee-save register range is $16-$23, $f20-$f30
100 static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
101 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
102 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
103 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
104 Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
105 };
106
107 static const unsigned BitMode32CalleeSavedRegs[] = {
108 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
109 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
110 Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 0
111 };
112
113 if (Subtarget.isSingleFloat())
114 return SingleFloatOnlyCalleeSavedRegs;
115 else
116 return BitMode32CalleeSavedRegs;
117}
118
119/// Mips Callee Saved Register Classes
120const TargetRegisterClass* const*
121MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
122{
123 static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC[] = {
124 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
125 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
126 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
127 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
128 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
129 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
130 &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
131 };
132
133 static const TargetRegisterClass * const BitMode32CalleeSavedRC[] = {
134 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
135 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
136 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
137 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
138 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
139 };
140
141 if (Subtarget.isSingleFloat())
142 return SingleFloatOnlyCalleeSavedRC;
143 else
144 return BitMode32CalleeSavedRC;
145}
146
147BitVector MipsRegisterInfo::
148getReservedRegs(const MachineFunction &MF) const
149{
150 BitVector Reserved(getNumRegs());
151 Reserved.set(Mips::ZERO);
152 Reserved.set(Mips::AT);
153 Reserved.set(Mips::K0);
154 Reserved.set(Mips::K1);
155 Reserved.set(Mips::GP);
156 Reserved.set(Mips::SP);
157 Reserved.set(Mips::FP);
158 Reserved.set(Mips::RA);
159
160 // SRV4 requires that odd register can't be used.
161 if (!Subtarget.isSingleFloat())
162 for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
163 Reserved.set(FReg);
164
165 return Reserved;
166}
167
168//===----------------------------------------------------------------------===//
169//
170// Stack Frame Processing methods
171// +----------------------------+
172//
173// The stack is allocated decrementing the stack pointer on
174// the first instruction of a function prologue. Once decremented,
175// all stack references are done thought a positive offset
176// from the stack/frame pointer, so the stack is considering
177// to grow up! Otherwise terrible hacks would have to be made
178// to get this stack ABI compliant :)
179//
180// The stack frame required by the ABI (after call):
181// Offset
182//
183// 0 ----------
184// 4 Args to pass
185// . saved $GP (used in PIC)
186// . Alloca allocations
187// . Local Area
188// . CPU "Callee Saved" Registers
189// . saved FP
190// . saved RA
191// . FPU "Callee Saved" Registers
192// StackSize -----------
193//
194// Offset - offset from sp after stack allocation on function prologue
195//
196// The sp is the stack pointer subtracted/added from the stack size
197// at the Prologue/Epilogue
198//
199// References to the previous stack (to obtain arguments) are done
200// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
201//
202// Examples:
203// - reference to the actual stack frame
204// for any local area var there is smt like : FI >= 0, StackOffset: 4
205// sw REGX, 4(SP)
206//
207// - reference to previous stack frame
208// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
209// The emitted instruction will be something like:
210// lw REGX, 16+StackSize(SP)
211//
212// Since the total stack size is unknown on LowerFormalArguments, all
213// stack references (ObjectOffset) created to reference the function
214// arguments, are negative numbers. This way, on eliminateFrameIndex it's
215// possible to detect those references and the offsets are adjusted to
216// their real location.
217//
218//===----------------------------------------------------------------------===//
219
220void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
221{
222 MachineFrameInfo *MFI = MF.getFrameInfo();
223 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
224 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
225 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
| 1//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MIPS implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-reg-info"
15
16#include "Mips.h"
17#include "MipsSubtarget.h"
18#include "MipsRegisterInfo.h"
19#include "MipsMachineFunction.h"
20#include "llvm/Constants.h"
21#include "llvm/Type.h"
22#include "llvm/Function.h"
23#include "llvm/CodeGen/ValueTypes.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineLocation.h"
28#include "llvm/Target/TargetFrameInfo.h"
29#include "llvm/Target/TargetMachine.h"
30#include "llvm/Target/TargetOptions.h"
31#include "llvm/Target/TargetInstrInfo.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
36#include "llvm/ADT/BitVector.h"
37#include "llvm/ADT/STLExtras.h"
38
39using namespace llvm;
40
41MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
42 const TargetInstrInfo &tii)
43 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44 Subtarget(ST), TII(tii) {}
45
46/// getRegisterNumbering - Given the enum value for some register, e.g.
47/// Mips::RA, return the number that it corresponds to (e.g. 31).
48unsigned MipsRegisterInfo::
49getRegisterNumbering(unsigned RegEnum)
50{
51 switch (RegEnum) {
52 case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
53 case Mips::AT : case Mips::F1 : return 1;
54 case Mips::V0 : case Mips::F2 : case Mips::D1 : return 2;
55 case Mips::V1 : case Mips::F3 : return 3;
56 case Mips::A0 : case Mips::F4 : case Mips::D2 : return 4;
57 case Mips::A1 : case Mips::F5 : return 5;
58 case Mips::A2 : case Mips::F6 : case Mips::D3 : return 6;
59 case Mips::A3 : case Mips::F7 : return 7;
60 case Mips::T0 : case Mips::F8 : case Mips::D4 : return 8;
61 case Mips::T1 : case Mips::F9 : return 9;
62 case Mips::T2 : case Mips::F10: case Mips::D5: return 10;
63 case Mips::T3 : case Mips::F11: return 11;
64 case Mips::T4 : case Mips::F12: case Mips::D6: return 12;
65 case Mips::T5 : case Mips::F13: return 13;
66 case Mips::T6 : case Mips::F14: case Mips::D7: return 14;
67 case Mips::T7 : case Mips::F15: return 15;
68 case Mips::T8 : case Mips::F16: case Mips::D8: return 16;
69 case Mips::T9 : case Mips::F17: return 17;
70 case Mips::S0 : case Mips::F18: case Mips::D9: return 18;
71 case Mips::S1 : case Mips::F19: return 19;
72 case Mips::S2 : case Mips::F20: case Mips::D10: return 20;
73 case Mips::S3 : case Mips::F21: return 21;
74 case Mips::S4 : case Mips::F22: case Mips::D11: return 22;
75 case Mips::S5 : case Mips::F23: return 23;
76 case Mips::S6 : case Mips::F24: case Mips::D12: return 24;
77 case Mips::S7 : case Mips::F25: return 25;
78 case Mips::K0 : case Mips::F26: case Mips::D13: return 26;
79 case Mips::K1 : case Mips::F27: return 27;
80 case Mips::GP : case Mips::F28: case Mips::D14: return 28;
81 case Mips::SP : case Mips::F29: return 29;
82 case Mips::FP : case Mips::F30: case Mips::D15: return 30;
83 case Mips::RA : case Mips::F31: return 31;
84 default: llvm_unreachable("Unknown register number!");
85 }
86 return 0; // Not reached
87}
88
89unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
90
91//===----------------------------------------------------------------------===//
92// Callee Saved Registers methods
93//===----------------------------------------------------------------------===//
94
95/// Mips Callee Saved Registers
96const unsigned* MipsRegisterInfo::
97getCalleeSavedRegs(const MachineFunction *MF) const
98{
99 // Mips callee-save register range is $16-$23, $f20-$f30
100 static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
101 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
102 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
103 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
104 Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
105 };
106
107 static const unsigned BitMode32CalleeSavedRegs[] = {
108 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
109 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
110 Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 0
111 };
112
113 if (Subtarget.isSingleFloat())
114 return SingleFloatOnlyCalleeSavedRegs;
115 else
116 return BitMode32CalleeSavedRegs;
117}
118
119/// Mips Callee Saved Register Classes
120const TargetRegisterClass* const*
121MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
122{
123 static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC[] = {
124 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
125 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
126 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
127 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
128 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
129 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
130 &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
131 };
132
133 static const TargetRegisterClass * const BitMode32CalleeSavedRC[] = {
134 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
135 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
136 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
137 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
138 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
139 };
140
141 if (Subtarget.isSingleFloat())
142 return SingleFloatOnlyCalleeSavedRC;
143 else
144 return BitMode32CalleeSavedRC;
145}
146
147BitVector MipsRegisterInfo::
148getReservedRegs(const MachineFunction &MF) const
149{
150 BitVector Reserved(getNumRegs());
151 Reserved.set(Mips::ZERO);
152 Reserved.set(Mips::AT);
153 Reserved.set(Mips::K0);
154 Reserved.set(Mips::K1);
155 Reserved.set(Mips::GP);
156 Reserved.set(Mips::SP);
157 Reserved.set(Mips::FP);
158 Reserved.set(Mips::RA);
159
160 // SRV4 requires that odd register can't be used.
161 if (!Subtarget.isSingleFloat())
162 for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
163 Reserved.set(FReg);
164
165 return Reserved;
166}
167
168//===----------------------------------------------------------------------===//
169//
170// Stack Frame Processing methods
171// +----------------------------+
172//
173// The stack is allocated decrementing the stack pointer on
174// the first instruction of a function prologue. Once decremented,
175// all stack references are done thought a positive offset
176// from the stack/frame pointer, so the stack is considering
177// to grow up! Otherwise terrible hacks would have to be made
178// to get this stack ABI compliant :)
179//
180// The stack frame required by the ABI (after call):
181// Offset
182//
183// 0 ----------
184// 4 Args to pass
185// . saved $GP (used in PIC)
186// . Alloca allocations
187// . Local Area
188// . CPU "Callee Saved" Registers
189// . saved FP
190// . saved RA
191// . FPU "Callee Saved" Registers
192// StackSize -----------
193//
194// Offset - offset from sp after stack allocation on function prologue
195//
196// The sp is the stack pointer subtracted/added from the stack size
197// at the Prologue/Epilogue
198//
199// References to the previous stack (to obtain arguments) are done
200// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
201//
202// Examples:
203// - reference to the actual stack frame
204// for any local area var there is smt like : FI >= 0, StackOffset: 4
205// sw REGX, 4(SP)
206//
207// - reference to previous stack frame
208// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
209// The emitted instruction will be something like:
210// lw REGX, 16+StackSize(SP)
211//
212// Since the total stack size is unknown on LowerFormalArguments, all
213// stack references (ObjectOffset) created to reference the function
214// arguments, are negative numbers. This way, on eliminateFrameIndex it's
215// possible to detect those references and the offsets are adjusted to
216// their real location.
217//
218//===----------------------------------------------------------------------===//
219
220void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
221{
222 MachineFrameInfo *MFI = MF.getFrameInfo();
223 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
224 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
225 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
| 226 unsigned RegSize = Subtarget.isGP32bit() ? 4 : 8;
227 bool HasGP = MipsFI->needGPSaveRestore();
|
226
227 // Min and Max CSI FrameIndex.
228 int MinCSFI = -1, MaxCSFI = -1;
229
230 // See the description at MipsMachineFunction.h
231 int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
232
233 // Replace the dummy '0' SPOffset by the negative offsets, as explained on
234 // LowerFormalArguments. Leaving '0' for while is necessary to avoid
235 // the approach done by calculateFrameObjectOffsets to the stack frame.
236 MipsFI->adjustLoadArgsFI(MFI);
237 MipsFI->adjustStoreVarArgsFI(MFI);
238
239 // It happens that the default stack frame allocation order does not directly
240 // map to the convention used for mips. So we must fix it. We move the callee
241 // save register slots after the local variables area, as described in the
242 // stack frame above.
243 unsigned CalleeSavedAreaSize = 0;
244 if (!CSI.empty()) {
245 MinCSFI = CSI[0].getFrameIdx();
246 MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
247 }
248 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
249 CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
250
| 228
229 // Min and Max CSI FrameIndex.
230 int MinCSFI = -1, MaxCSFI = -1;
231
232 // See the description at MipsMachineFunction.h
233 int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
234
235 // Replace the dummy '0' SPOffset by the negative offsets, as explained on
236 // LowerFormalArguments. Leaving '0' for while is necessary to avoid
237 // the approach done by calculateFrameObjectOffsets to the stack frame.
238 MipsFI->adjustLoadArgsFI(MFI);
239 MipsFI->adjustStoreVarArgsFI(MFI);
240
241 // It happens that the default stack frame allocation order does not directly
242 // map to the convention used for mips. So we must fix it. We move the callee
243 // save register slots after the local variables area, as described in the
244 // stack frame above.
245 unsigned CalleeSavedAreaSize = 0;
246 if (!CSI.empty()) {
247 MinCSFI = CSI[0].getFrameIdx();
248 MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
249 }
250 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
251 CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
252
|
| 253 unsigned StackOffset = HasGP ? (MipsFI->getGPStackOffset()+RegSize)
254 : (Subtarget.isABI_O32() ? 16 : 0);
255
|
251 // Adjust local variables. They should come on the stack right
252 // after the arguments.
253 int LastOffsetFI = -1;
254 for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
255 if (i >= MinCSFI && i <= MaxCSFI)
256 continue;
257 if (MFI->isDeadObjectIndex(i))
258 continue;
| 256 // Adjust local variables. They should come on the stack right
257 // after the arguments.
258 int LastOffsetFI = -1;
259 for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
260 if (i >= MinCSFI && i <= MaxCSFI)
261 continue;
262 if (MFI->isDeadObjectIndex(i))
263 continue;
|
259 unsigned Offset = MFI->getObjectOffset(i) - CalleeSavedAreaSize;
| 264 unsigned Offset =
265 StackOffset + MFI->getObjectOffset(i) - CalleeSavedAreaSize;
|
260 if (LastOffsetFI == -1)
261 LastOffsetFI = i;
262 if (Offset > MFI->getObjectOffset(LastOffsetFI))
263 LastOffsetFI = i;
264 MFI->setObjectOffset(i, Offset);
265 }
266
267 // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
| 266 if (LastOffsetFI == -1)
267 LastOffsetFI = i;
268 if (Offset > MFI->getObjectOffset(LastOffsetFI))
269 LastOffsetFI = i;
270 MFI->setObjectOffset(i, Offset);
271 }
272
273 // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
|
268 // be saved in this CPU Area there is the need. This whole Area must
269 // be aligned to the default Stack Alignment requirements.
270 unsigned StackOffset = 0;
271 unsigned RegSize = Subtarget.isGP32bit() ? 4 : 8;
272
| 274 // be saved in this CPU Area. This whole area must be aligned to the
275 // default Stack Alignment requirements.
|
273 if (LastOffsetFI >= 0)
274 StackOffset = MFI->getObjectOffset(LastOffsetFI)+
275 MFI->getObjectSize(LastOffsetFI);
276 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
277
278 for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
279 if (CSI[i].getRegClass() != Mips::CPURegsRegisterClass)
280 break;
281 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
282 TopCPUSavedRegOff = StackOffset;
283 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
284 }
285
| 276 if (LastOffsetFI >= 0)
277 StackOffset = MFI->getObjectOffset(LastOffsetFI)+
278 MFI->getObjectSize(LastOffsetFI);
279 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
280
281 for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
282 if (CSI[i].getRegClass() != Mips::CPURegsRegisterClass)
283 break;
284 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
285 TopCPUSavedRegOff = StackOffset;
286 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
287 }
288
|
286 if (hasFP(MF)) {
| 289 // Stack locations for FP and RA. If only one of them is used,
290 // the space must be allocated for both, otherwise no space at all.
291 if (hasFP(MF) || MFI->hasCalls()) {
292 // FP stack location
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287 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
288 StackOffset);
289 MipsFI->setFPStackOffset(StackOffset);
290 TopCPUSavedRegOff = StackOffset;
291 StackOffset += RegSize;
| 293 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
294 StackOffset);
295 MipsFI->setFPStackOffset(StackOffset);
296 TopCPUSavedRegOff = StackOffset;
297 StackOffset += RegSize;
|
292 }
| |
293
| 298
|
294 if (MFI->hasCalls()) {
| 299 // SP stack location
|
295 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
296 StackOffset);
297 MipsFI->setRAStackOffset(StackOffset);
| 300 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
301 StackOffset);
302 MipsFI->setRAStackOffset(StackOffset);
|
298 TopCPUSavedRegOff = StackOffset;
| |
299 StackOffset += RegSize;
| 303 StackOffset += RegSize;
|
| 304
305 if (MFI->hasCalls())
306 TopCPUSavedRegOff += RegSize;
|
300 }
| 307 }
|
| 308
|
301 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
302
303 // Adjust FPU Callee Saved Registers Area. This Area must be
304 // aligned to the default Stack Alignment requirements.
305 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
306 if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
307 continue;
308 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
309 TopFPUSavedRegOff = StackOffset;
310 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
311 }
312 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
313
314 // Update frame info
315 MFI->setStackSize(StackOffset);
316
317 // Recalculate the final tops offset. The final values must be '0'
318 // if there isn't a callee saved register for CPU or FPU, otherwise
319 // a negative offset is needed.
320 if (TopCPUSavedRegOff >= 0)
321 MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
322
323 if (TopFPUSavedRegOff >= 0)
324 MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
325}
326
327// hasFP - Return true if the specified function should have a dedicated frame
328// pointer register. This is true if the function has variable sized allocas or
329// if frame pointer elimination is disabled.
330bool MipsRegisterInfo::
331hasFP(const MachineFunction &MF) const {
332 const MachineFrameInfo *MFI = MF.getFrameInfo();
333 return NoFramePointerElim || MFI->hasVarSizedObjects();
334}
335
336// This function eliminate ADJCALLSTACKDOWN,
337// ADJCALLSTACKUP pseudo instructions
338void MipsRegisterInfo::
339eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
340 MachineBasicBlock::iterator I) const {
341 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
342 MBB.erase(I);
343}
344
345// FrameIndex represent objects inside a abstract stack.
346// We must replace FrameIndex with an stack/frame pointer
347// direct reference.
348unsigned MipsRegisterInfo::
349eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
350 int *Value, RegScavenger *RS) const
351{
352 MachineInstr &MI = *II;
353 MachineFunction &MF = *MI.getParent()->getParent();
354
355 unsigned i = 0;
356 while (!MI.getOperand(i).isFI()) {
357 ++i;
358 assert(i < MI.getNumOperands() &&
359 "Instr doesn't have FrameIndex operand!");
360 }
361
362 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
363 errs() << "<--------->\n" << MI);
364
365 int FrameIndex = MI.getOperand(i).getIndex();
366 int stackSize = MF.getFrameInfo()->getStackSize();
367 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
368
369 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
370 << "spOffset : " << spOffset << "\n"
371 << "stackSize : " << stackSize << "\n");
372
373 // as explained on LowerFormalArguments, detect negative offsets
374 // and adjust SPOffsets considering the final stack size.
375 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
376 Offset += MI.getOperand(i-1).getImm();
377
378 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
379
380 MI.getOperand(i-1).ChangeToImmediate(Offset);
381 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
382 return 0;
383}
384
385void MipsRegisterInfo::
386emitPrologue(MachineFunction &MF) const
387{
388 MachineBasicBlock &MBB = MF.front();
389 MachineFrameInfo *MFI = MF.getFrameInfo();
390 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
391 MachineBasicBlock::iterator MBBI = MBB.begin();
392 DebugLoc dl = (MBBI != MBB.end() ?
393 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
394 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
395
396 // Get the right frame order for Mips.
397 adjustMipsStackFrame(MF);
398
399 // Get the number of bytes to allocate from the FrameInfo.
400 unsigned StackSize = MFI->getStackSize();
401
402 // No need to allocate space on the stack.
403 if (StackSize == 0 && !MFI->hasCalls()) return;
404
405 int FPOffset = MipsFI->getFPStackOffset();
406 int RAOffset = MipsFI->getRAStackOffset();
407
408 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
409
410 // TODO: check need from GP here.
411 if (isPIC && Subtarget.isABI_O32())
412 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
413 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
414
415 // Adjust stack : addi sp, sp, (-imm)
416 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
417 .addReg(Mips::SP).addImm(-StackSize);
418
419 // Save the return address only if the function isnt a leaf one.
420 // sw $ra, stack_loc($sp)
421 if (MFI->hasCalls()) {
422 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
423 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
424 }
425
426 // if framepointer enabled, save it and set it
427 // to point to the stack pointer
428 if (hasFP(MF)) {
429 // sw $fp,stack_loc($sp)
430 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
431 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
432
433 // move $fp, $sp
434 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
435 .addReg(Mips::SP).addReg(Mips::ZERO);
436 }
437
438 // Restore GP from the saved stack location
439 if (MipsFI->needGPSaveRestore())
440 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
441 .addImm(MipsFI->getGPStackOffset());
442}
443
444void MipsRegisterInfo::
445emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
446{
447 MachineBasicBlock::iterator MBBI = prior(MBB.end());
448 MachineFrameInfo *MFI = MF.getFrameInfo();
449 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
450 DebugLoc dl = MBBI->getDebugLoc();
451
452 // Get the number of bytes from FrameInfo
453 int NumBytes = (int) MFI->getStackSize();
454
455 // Get the FI's where RA and FP are saved.
456 int FPOffset = MipsFI->getFPStackOffset();
457 int RAOffset = MipsFI->getRAStackOffset();
458
459 // if framepointer enabled, restore it and restore the
460 // stack pointer
461 if (hasFP(MF)) {
462 // move $sp, $fp
463 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
464 .addReg(Mips::FP).addReg(Mips::ZERO);
465
466 // lw $fp,stack_loc($sp)
467 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::FP)
468 .addImm(FPOffset).addReg(Mips::SP);
469 }
470
471 // Restore the return address only if the function isnt a leaf one.
472 // lw $ra, stack_loc($sp)
473 if (MFI->hasCalls()) {
474 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::RA)
475 .addImm(RAOffset).addReg(Mips::SP);
476 }
477
478 // adjust stack : insert addi sp, sp, (imm)
479 if (NumBytes) {
480 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
481 .addReg(Mips::SP).addImm(NumBytes);
482 }
483}
484
485
486void MipsRegisterInfo::
487processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
488 // Set the stack offset where GP must be saved/loaded from.
489 MachineFrameInfo *MFI = MF.getFrameInfo();
490 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
491 if (MipsFI->needGPSaveRestore())
492 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
493}
494
495unsigned MipsRegisterInfo::
496getRARegister() const {
497 return Mips::RA;
498}
499
500unsigned MipsRegisterInfo::
501getFrameRegister(const MachineFunction &MF) const {
502 return hasFP(MF) ? Mips::FP : Mips::SP;
503}
504
505unsigned MipsRegisterInfo::
506getEHExceptionRegister() const {
507 llvm_unreachable("What is the exception register");
508 return 0;
509}
510
511unsigned MipsRegisterInfo::
512getEHHandlerRegister() const {
513 llvm_unreachable("What is the exception handler register");
514 return 0;
515}
516
517int MipsRegisterInfo::
518getDwarfRegNum(unsigned RegNum, bool isEH) const {
519 llvm_unreachable("What is the dwarf register number");
520 return -1;
521}
522
523#include "MipsGenRegisterInfo.inc"
524
| 309 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
310
311 // Adjust FPU Callee Saved Registers Area. This Area must be
312 // aligned to the default Stack Alignment requirements.
313 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
314 if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
315 continue;
316 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
317 TopFPUSavedRegOff = StackOffset;
318 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
319 }
320 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
321
322 // Update frame info
323 MFI->setStackSize(StackOffset);
324
325 // Recalculate the final tops offset. The final values must be '0'
326 // if there isn't a callee saved register for CPU or FPU, otherwise
327 // a negative offset is needed.
328 if (TopCPUSavedRegOff >= 0)
329 MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
330
331 if (TopFPUSavedRegOff >= 0)
332 MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
333}
334
335// hasFP - Return true if the specified function should have a dedicated frame
336// pointer register. This is true if the function has variable sized allocas or
337// if frame pointer elimination is disabled.
338bool MipsRegisterInfo::
339hasFP(const MachineFunction &MF) const {
340 const MachineFrameInfo *MFI = MF.getFrameInfo();
341 return NoFramePointerElim || MFI->hasVarSizedObjects();
342}
343
344// This function eliminate ADJCALLSTACKDOWN,
345// ADJCALLSTACKUP pseudo instructions
346void MipsRegisterInfo::
347eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
348 MachineBasicBlock::iterator I) const {
349 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
350 MBB.erase(I);
351}
352
353// FrameIndex represent objects inside a abstract stack.
354// We must replace FrameIndex with an stack/frame pointer
355// direct reference.
356unsigned MipsRegisterInfo::
357eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
358 int *Value, RegScavenger *RS) const
359{
360 MachineInstr &MI = *II;
361 MachineFunction &MF = *MI.getParent()->getParent();
362
363 unsigned i = 0;
364 while (!MI.getOperand(i).isFI()) {
365 ++i;
366 assert(i < MI.getNumOperands() &&
367 "Instr doesn't have FrameIndex operand!");
368 }
369
370 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
371 errs() << "<--------->\n" << MI);
372
373 int FrameIndex = MI.getOperand(i).getIndex();
374 int stackSize = MF.getFrameInfo()->getStackSize();
375 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
376
377 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
378 << "spOffset : " << spOffset << "\n"
379 << "stackSize : " << stackSize << "\n");
380
381 // as explained on LowerFormalArguments, detect negative offsets
382 // and adjust SPOffsets considering the final stack size.
383 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
384 Offset += MI.getOperand(i-1).getImm();
385
386 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
387
388 MI.getOperand(i-1).ChangeToImmediate(Offset);
389 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
390 return 0;
391}
392
393void MipsRegisterInfo::
394emitPrologue(MachineFunction &MF) const
395{
396 MachineBasicBlock &MBB = MF.front();
397 MachineFrameInfo *MFI = MF.getFrameInfo();
398 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
399 MachineBasicBlock::iterator MBBI = MBB.begin();
400 DebugLoc dl = (MBBI != MBB.end() ?
401 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
402 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
403
404 // Get the right frame order for Mips.
405 adjustMipsStackFrame(MF);
406
407 // Get the number of bytes to allocate from the FrameInfo.
408 unsigned StackSize = MFI->getStackSize();
409
410 // No need to allocate space on the stack.
411 if (StackSize == 0 && !MFI->hasCalls()) return;
412
413 int FPOffset = MipsFI->getFPStackOffset();
414 int RAOffset = MipsFI->getRAStackOffset();
415
416 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
417
418 // TODO: check need from GP here.
419 if (isPIC && Subtarget.isABI_O32())
420 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
421 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
422
423 // Adjust stack : addi sp, sp, (-imm)
424 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
425 .addReg(Mips::SP).addImm(-StackSize);
426
427 // Save the return address only if the function isnt a leaf one.
428 // sw $ra, stack_loc($sp)
429 if (MFI->hasCalls()) {
430 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
431 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
432 }
433
434 // if framepointer enabled, save it and set it
435 // to point to the stack pointer
436 if (hasFP(MF)) {
437 // sw $fp,stack_loc($sp)
438 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
439 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
440
441 // move $fp, $sp
442 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
443 .addReg(Mips::SP).addReg(Mips::ZERO);
444 }
445
446 // Restore GP from the saved stack location
447 if (MipsFI->needGPSaveRestore())
448 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
449 .addImm(MipsFI->getGPStackOffset());
450}
451
452void MipsRegisterInfo::
453emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
454{
455 MachineBasicBlock::iterator MBBI = prior(MBB.end());
456 MachineFrameInfo *MFI = MF.getFrameInfo();
457 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
458 DebugLoc dl = MBBI->getDebugLoc();
459
460 // Get the number of bytes from FrameInfo
461 int NumBytes = (int) MFI->getStackSize();
462
463 // Get the FI's where RA and FP are saved.
464 int FPOffset = MipsFI->getFPStackOffset();
465 int RAOffset = MipsFI->getRAStackOffset();
466
467 // if framepointer enabled, restore it and restore the
468 // stack pointer
469 if (hasFP(MF)) {
470 // move $sp, $fp
471 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
472 .addReg(Mips::FP).addReg(Mips::ZERO);
473
474 // lw $fp,stack_loc($sp)
475 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::FP)
476 .addImm(FPOffset).addReg(Mips::SP);
477 }
478
479 // Restore the return address only if the function isnt a leaf one.
480 // lw $ra, stack_loc($sp)
481 if (MFI->hasCalls()) {
482 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::RA)
483 .addImm(RAOffset).addReg(Mips::SP);
484 }
485
486 // adjust stack : insert addi sp, sp, (imm)
487 if (NumBytes) {
488 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
489 .addReg(Mips::SP).addImm(NumBytes);
490 }
491}
492
493
494void MipsRegisterInfo::
495processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
496 // Set the stack offset where GP must be saved/loaded from.
497 MachineFrameInfo *MFI = MF.getFrameInfo();
498 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
499 if (MipsFI->needGPSaveRestore())
500 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
501}
502
503unsigned MipsRegisterInfo::
504getRARegister() const {
505 return Mips::RA;
506}
507
508unsigned MipsRegisterInfo::
509getFrameRegister(const MachineFunction &MF) const {
510 return hasFP(MF) ? Mips::FP : Mips::SP;
511}
512
513unsigned MipsRegisterInfo::
514getEHExceptionRegister() const {
515 llvm_unreachable("What is the exception register");
516 return 0;
517}
518
519unsigned MipsRegisterInfo::
520getEHHandlerRegister() const {
521 llvm_unreachable("What is the exception handler register");
522 return 0;
523}
524
525int MipsRegisterInfo::
526getDwarfRegNum(unsigned RegNum, bool isEH) const {
527 llvm_unreachable("What is the dwarf register number");
528 return -1;
529}
530
531#include "MipsGenRegisterInfo.inc"
532
|