| MipsInstrFPU.td (199481) | MipsInstrFPU.td (203954) |
|---|---|
| 1//===- MipsInstrFPU.td - Mips FPU Instruction Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 99 unchanged lines hidden (view full) --- 108//===----------------------------------------------------------------------===// 109 110let ft = 0 in { 111 defm FLOOR_W : FFR1_1<0b001111, "floor.w">; 112 defm CEIL_W : FFR1_1<0b001110, "ceil.w">; 113 defm ROUND_W : FFR1_1<0b001100, "round.w">; 114 defm TRUNC_W : FFR1_1<0b001101, "trunc.w">; 115 defm CVTW : FFR1_1<0b100100, "cvt.w">; | 1//===- MipsInstrFPU.td - Mips FPU Instruction Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 99 unchanged lines hidden (view full) --- 108//===----------------------------------------------------------------------===// 109 110let ft = 0 in { 111 defm FLOOR_W : FFR1_1<0b001111, "floor.w">; 112 defm CEIL_W : FFR1_1<0b001110, "ceil.w">; 113 defm ROUND_W : FFR1_1<0b001100, "round.w">; 114 defm TRUNC_W : FFR1_1<0b001101, "trunc.w">; 115 defm CVTW : FFR1_1<0b100100, "cvt.w">; |
| 116 defm FMOV : FFR1_1<0b000110, "mov">; | |
| 117 118 defm FABS : FFR1_2<0b000101, "abs", fabs>; 119 defm FNEG : FFR1_2<0b000111, "neg", fneg>; 120 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>; 121 122 /// Convert to Single Precison 123 def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">; 124 --- 43 unchanged lines hidden (view full) --- 168 169 def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs), 170 "mfc1 $rt, $fs", []>; 171 172 def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt), 173 "mtc1 $rt, $fs", []>; 174} 175 | 116 117 defm FABS : FFR1_2<0b000101, "abs", fabs>; 118 defm FNEG : FFR1_2<0b000111, "neg", fneg>; 119 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>; 120 121 /// Convert to Single Precison 122 def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">; 123 --- 43 unchanged lines hidden (view full) --- 167 168 def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs), 169 "mfc1 $rt, $fs", []>; 170 171 def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt), 172 "mtc1 $rt, $fs", []>; 173} 174 |
| 175def FMOV_S32 : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), 176 "mov.s $fd, $fs", []>; 177def FMOV_D32 : FFR<0x11, 0b000110, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs), 178 "mov.d $fd, $fs", []>; 179 |
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| 176/// Floating Point Memory Instructions 177let Predicates = [IsNotSingleFloat, IsNotMipsI] in { 178 def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr), 179 "ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>; 180 181 def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr), 182 "sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>; 183} --- 127 unchanged lines hidden --- | 180/// Floating Point Memory Instructions 181let Predicates = [IsNotSingleFloat, IsNotMipsI] in { 182 def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr), 183 "ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>; 184 185 def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr), 186 "sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>; 187} --- 127 unchanged lines hidden --- |