1//==-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ------*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that MSP430 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_MSP430_ISELLOWERING_H
16#define LLVM_TARGET_MSP430_ISELLOWERING_H
17
18#include "MSP430.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/Target/TargetLowering.h"
21
22namespace llvm {
23 namespace MSP430ISD {
24 enum {
25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
26
27 /// Return with a flag operand. Operand 0 is the chain operand.
28 RET_FLAG,
29
30 /// Same as RET_FLAG, but used for returning from ISRs.
31 RETI_FLAG,
32
33 /// Y = R{R,L}A X, rotate right (left) arithmetically
34 RRA, RLA,
35
36 /// Y = RRC X, rotate right via carry
37 RRC,
38
39 /// CALL - These operations represent an abstract call
40 /// instruction, which includes a bunch of information.
41 CALL,
42
43 /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
44 /// and TargetGlobalAddress.
45 Wrapper,
46
47 /// CMP - Compare instruction.
48 CMP,
49
50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
51 /// operand produced by a CMP instruction.
52 SETCC,
53
54 /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
55 /// is the block to branch if condition is true, operand 2 is the
56 /// condition code, and operand 3 is the flag operand produced by a CMP
57 /// instruction.
58 BR_CC,
59
60 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
61 /// is condition code and operand 4 is flag operand.
62 SELECT_CC,
63
64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
66 };
67 }
68
69 class MSP430Subtarget;
70 class MSP430TargetMachine;
71
72 class MSP430TargetLowering : public TargetLowering {
73 public:
74 explicit MSP430TargetLowering(MSP430TargetMachine &TM);
75
76 /// LowerOperation - Provide custom lowering hooks for some operations.
77 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
78
79 /// getTargetNodeName - This method returns the name of a target specific
80 /// DAG node.
81 virtual const char *getTargetNodeName(unsigned Opcode) const;
82
83 /// getFunctionAlignment - Return the Log2 alignment of this function.
84 virtual unsigned getFunctionAlignment(const Function *F) const;
85
86 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG);
87 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
91 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
92 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG);
93 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
94 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
95 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
96
97 TargetLowering::ConstraintType
98 getConstraintType(const std::string &Constraint) const;
99 std::pair<unsigned, const TargetRegisterClass*>
100 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
101
102 /// isTruncateFree - Return true if it's free to truncate a value of type
103 /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
104 /// register R15W to i8 by referencing its sub-register R15B.
105 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
106 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
107
108 /// isZExtFree - Return true if any actual instruction that defines a value
109 /// of type Ty1 implicit zero-extends the value to Ty2 in the result
110 /// register. This does not necessarily include registers defined in unknown
111 /// ways, such as incoming arguments, or copies from unknown virtual
112 /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
113 /// necessarily apply to truncate instructions. e.g. on msp430, all
114 /// instructions that define 8-bit values implicit zero-extend the result
115 /// out to 16 bits.
116 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
117 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
118
119 MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
120 MachineBasicBlock *BB,
121 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
122 MachineBasicBlock* EmitShiftInstr(MachineInstr *MI,
123 MachineBasicBlock *BB,
124 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
125
126 private:
127 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
128 CallingConv::ID CallConv, bool isVarArg,
129 bool isTailCall,
130 const SmallVectorImpl<ISD::OutputArg> &Outs,
131 const SmallVectorImpl<ISD::InputArg> &Ins,
132 DebugLoc dl, SelectionDAG &DAG,
133 SmallVectorImpl<SDValue> &InVals);
134
135 SDValue LowerCCCArguments(SDValue Chain,
136 CallingConv::ID CallConv,
137 bool isVarArg,
138 const SmallVectorImpl<ISD::InputArg> &Ins,
139 DebugLoc dl,
140 SelectionDAG &DAG,
141 SmallVectorImpl<SDValue> &InVals);
142
143 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
144 CallingConv::ID CallConv, bool isVarArg,
145 const SmallVectorImpl<ISD::InputArg> &Ins,
146 DebugLoc dl, SelectionDAG &DAG,
147 SmallVectorImpl<SDValue> &InVals);
148
149 virtual SDValue
150 LowerFormalArguments(SDValue Chain,
151 CallingConv::ID CallConv, bool isVarArg,
152 const SmallVectorImpl<ISD::InputArg> &Ins,
153 DebugLoc dl, SelectionDAG &DAG,
154 SmallVectorImpl<SDValue> &InVals);
155 virtual SDValue
156 LowerCall(SDValue Chain, SDValue Callee,
| 1//==-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ------*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that MSP430 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_MSP430_ISELLOWERING_H
16#define LLVM_TARGET_MSP430_ISELLOWERING_H
17
18#include "MSP430.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/Target/TargetLowering.h"
21
22namespace llvm {
23 namespace MSP430ISD {
24 enum {
25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
26
27 /// Return with a flag operand. Operand 0 is the chain operand.
28 RET_FLAG,
29
30 /// Same as RET_FLAG, but used for returning from ISRs.
31 RETI_FLAG,
32
33 /// Y = R{R,L}A X, rotate right (left) arithmetically
34 RRA, RLA,
35
36 /// Y = RRC X, rotate right via carry
37 RRC,
38
39 /// CALL - These operations represent an abstract call
40 /// instruction, which includes a bunch of information.
41 CALL,
42
43 /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
44 /// and TargetGlobalAddress.
45 Wrapper,
46
47 /// CMP - Compare instruction.
48 CMP,
49
50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
51 /// operand produced by a CMP instruction.
52 SETCC,
53
54 /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
55 /// is the block to branch if condition is true, operand 2 is the
56 /// condition code, and operand 3 is the flag operand produced by a CMP
57 /// instruction.
58 BR_CC,
59
60 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
61 /// is condition code and operand 4 is flag operand.
62 SELECT_CC,
63
64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
66 };
67 }
68
69 class MSP430Subtarget;
70 class MSP430TargetMachine;
71
72 class MSP430TargetLowering : public TargetLowering {
73 public:
74 explicit MSP430TargetLowering(MSP430TargetMachine &TM);
75
76 /// LowerOperation - Provide custom lowering hooks for some operations.
77 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
78
79 /// getTargetNodeName - This method returns the name of a target specific
80 /// DAG node.
81 virtual const char *getTargetNodeName(unsigned Opcode) const;
82
83 /// getFunctionAlignment - Return the Log2 alignment of this function.
84 virtual unsigned getFunctionAlignment(const Function *F) const;
85
86 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG);
87 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
91 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
92 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG);
93 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
94 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
95 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
96
97 TargetLowering::ConstraintType
98 getConstraintType(const std::string &Constraint) const;
99 std::pair<unsigned, const TargetRegisterClass*>
100 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
101
102 /// isTruncateFree - Return true if it's free to truncate a value of type
103 /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
104 /// register R15W to i8 by referencing its sub-register R15B.
105 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
106 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
107
108 /// isZExtFree - Return true if any actual instruction that defines a value
109 /// of type Ty1 implicit zero-extends the value to Ty2 in the result
110 /// register. This does not necessarily include registers defined in unknown
111 /// ways, such as incoming arguments, or copies from unknown virtual
112 /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
113 /// necessarily apply to truncate instructions. e.g. on msp430, all
114 /// instructions that define 8-bit values implicit zero-extend the result
115 /// out to 16 bits.
116 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
117 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
118
119 MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
120 MachineBasicBlock *BB,
121 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
122 MachineBasicBlock* EmitShiftInstr(MachineInstr *MI,
123 MachineBasicBlock *BB,
124 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
125
126 private:
127 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
128 CallingConv::ID CallConv, bool isVarArg,
129 bool isTailCall,
130 const SmallVectorImpl<ISD::OutputArg> &Outs,
131 const SmallVectorImpl<ISD::InputArg> &Ins,
132 DebugLoc dl, SelectionDAG &DAG,
133 SmallVectorImpl<SDValue> &InVals);
134
135 SDValue LowerCCCArguments(SDValue Chain,
136 CallingConv::ID CallConv,
137 bool isVarArg,
138 const SmallVectorImpl<ISD::InputArg> &Ins,
139 DebugLoc dl,
140 SelectionDAG &DAG,
141 SmallVectorImpl<SDValue> &InVals);
142
143 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
144 CallingConv::ID CallConv, bool isVarArg,
145 const SmallVectorImpl<ISD::InputArg> &Ins,
146 DebugLoc dl, SelectionDAG &DAG,
147 SmallVectorImpl<SDValue> &InVals);
148
149 virtual SDValue
150 LowerFormalArguments(SDValue Chain,
151 CallingConv::ID CallConv, bool isVarArg,
152 const SmallVectorImpl<ISD::InputArg> &Ins,
153 DebugLoc dl, SelectionDAG &DAG,
154 SmallVectorImpl<SDValue> &InVals);
155 virtual SDValue
156 LowerCall(SDValue Chain, SDValue Callee,
|
158 const SmallVectorImpl<ISD::OutputArg> &Outs,
159 const SmallVectorImpl<ISD::InputArg> &Ins,
160 DebugLoc dl, SelectionDAG &DAG,
161 SmallVectorImpl<SDValue> &InVals);
162
163 virtual SDValue
164 LowerReturn(SDValue Chain,
165 CallingConv::ID CallConv, bool isVarArg,
166 const SmallVectorImpl<ISD::OutputArg> &Outs,
167 DebugLoc dl, SelectionDAG &DAG);
168
169 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
170 SDValue &Base,
171 SDValue &Offset,
172 ISD::MemIndexedMode &AM,
173 SelectionDAG &DAG) const;
174
175 const MSP430Subtarget &Subtarget;
176 const MSP430TargetMachine &TM;
177 const TargetData *TD;
178 };
179} // namespace llvm
180
181#endif // LLVM_TARGET_MSP430_ISELLOWERING_H
| 158 const SmallVectorImpl<ISD::OutputArg> &Outs,
159 const SmallVectorImpl<ISD::InputArg> &Ins,
160 DebugLoc dl, SelectionDAG &DAG,
161 SmallVectorImpl<SDValue> &InVals);
162
163 virtual SDValue
164 LowerReturn(SDValue Chain,
165 CallingConv::ID CallConv, bool isVarArg,
166 const SmallVectorImpl<ISD::OutputArg> &Outs,
167 DebugLoc dl, SelectionDAG &DAG);
168
169 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
170 SDValue &Base,
171 SDValue &Offset,
172 ISD::MemIndexedMode &AM,
173 SelectionDAG &DAG) const;
174
175 const MSP430Subtarget &Subtarget;
176 const MSP430TargetMachine &TM;
177 const TargetData *TD;
178 };
179} // namespace llvm
180
181#endif // LLVM_TARGET_MSP430_ISELLOWERING_H
|