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ARMExpandPseudoInsts.cpp (263508) ARMExpandPseudoInsts.cpp (266715)
1//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 122 unchanged lines hidden (view full) ---

131{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
132{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
133{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
134{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
135{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
136{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
137
138{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
1//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 122 unchanged lines hidden (view full) ---

131{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
132{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
133{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
134{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
135{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
136{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
137
138{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
139{ ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
139{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
140{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
141{ ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
140
141{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
142{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
143{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
144{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
145{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
146{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
147{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},

--- 918 unchanged lines hidden (view full) ---

1066 case ARM::VLD2q32PseudoWB_fixed:
1067 case ARM::VLD2q8PseudoWB_register:
1068 case ARM::VLD2q16PseudoWB_register:
1069 case ARM::VLD2q32PseudoWB_register:
1070 case ARM::VLD3d8Pseudo:
1071 case ARM::VLD3d16Pseudo:
1072 case ARM::VLD3d32Pseudo:
1073 case ARM::VLD1d64TPseudo:
142
143{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
144{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
145{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
146{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
147{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
148{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
149{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},

--- 918 unchanged lines hidden (view full) ---

1068 case ARM::VLD2q32PseudoWB_fixed:
1069 case ARM::VLD2q8PseudoWB_register:
1070 case ARM::VLD2q16PseudoWB_register:
1071 case ARM::VLD2q32PseudoWB_register:
1072 case ARM::VLD3d8Pseudo:
1073 case ARM::VLD3d16Pseudo:
1074 case ARM::VLD3d32Pseudo:
1075 case ARM::VLD1d64TPseudo:
1076 case ARM::VLD1d64TPseudoWB_fixed:
1074 case ARM::VLD3d8Pseudo_UPD:
1075 case ARM::VLD3d16Pseudo_UPD:
1076 case ARM::VLD3d32Pseudo_UPD:
1077 case ARM::VLD3q8Pseudo_UPD:
1078 case ARM::VLD3q16Pseudo_UPD:
1079 case ARM::VLD3q32Pseudo_UPD:
1080 case ARM::VLD3q8oddPseudo:
1081 case ARM::VLD3q16oddPseudo:
1082 case ARM::VLD3q32oddPseudo:
1083 case ARM::VLD3q8oddPseudo_UPD:
1084 case ARM::VLD3q16oddPseudo_UPD:
1085 case ARM::VLD3q32oddPseudo_UPD:
1086 case ARM::VLD4d8Pseudo:
1087 case ARM::VLD4d16Pseudo:
1088 case ARM::VLD4d32Pseudo:
1089 case ARM::VLD1d64QPseudo:
1077 case ARM::VLD3d8Pseudo_UPD:
1078 case ARM::VLD3d16Pseudo_UPD:
1079 case ARM::VLD3d32Pseudo_UPD:
1080 case ARM::VLD3q8Pseudo_UPD:
1081 case ARM::VLD3q16Pseudo_UPD:
1082 case ARM::VLD3q32Pseudo_UPD:
1083 case ARM::VLD3q8oddPseudo:
1084 case ARM::VLD3q16oddPseudo:
1085 case ARM::VLD3q32oddPseudo:
1086 case ARM::VLD3q8oddPseudo_UPD:
1087 case ARM::VLD3q16oddPseudo_UPD:
1088 case ARM::VLD3q32oddPseudo_UPD:
1089 case ARM::VLD4d8Pseudo:
1090 case ARM::VLD4d16Pseudo:
1091 case ARM::VLD4d32Pseudo:
1092 case ARM::VLD1d64QPseudo:
1093 case ARM::VLD1d64QPseudoWB_fixed:
1090 case ARM::VLD4d8Pseudo_UPD:
1091 case ARM::VLD4d16Pseudo_UPD:
1092 case ARM::VLD4d32Pseudo_UPD:
1093 case ARM::VLD4q8Pseudo_UPD:
1094 case ARM::VLD4q16Pseudo_UPD:
1095 case ARM::VLD4q32Pseudo_UPD:
1096 case ARM::VLD4q8oddPseudo:
1097 case ARM::VLD4q16oddPseudo:

--- 183 unchanged lines hidden --- 		1094 case ARM::VLD4d8Pseudo_UPD:
1095 case ARM::VLD4d16Pseudo_UPD:
1096 case ARM::VLD4d32Pseudo_UPD:
1097 case ARM::VLD4q8Pseudo_UPD:
1098 case ARM::VLD4q16Pseudo_UPD:
1099 case ARM::VLD4q32Pseudo_UPD:
1100 case ARM::VLD4q8oddPseudo:
1101 case ARM::VLD4q16oddPseudo:

--- 183 unchanged lines hidden ---