1//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a pass that expands pseudo instructions into target
11// instructions to allow proper scheduling, if-conversion, and other late
12// optimizations. This pass should be run after register allocation but before
13// the post-regalloc scheduling pass.
14//
15//===----------------------------------------------------------------------===//
16
17#define DEBUG_TYPE "arm-pseudo"
18#include "ARM.h"
19#include "ARMBaseInstrInfo.h"
20#include "ARMBaseRegisterInfo.h"
21#include "ARMMachineFunctionInfo.h"
22#include "MCTargetDesc/ARMAddressingModes.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunctionPass.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/Support/CommandLine.h"
27#include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
28#include "llvm/Target/TargetFrameLowering.h"
29#include "llvm/Target/TargetRegisterInfo.h"
30using namespace llvm;
31
32static cl::opt<bool>
33VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34 cl::desc("Verify machine code after expanding ARM pseudos"));
35
36namespace {
37 class ARMExpandPseudo : public MachineFunctionPass {
38 public:
39 static char ID;
40 ARMExpandPseudo() : MachineFunctionPass(ID) {}
41
42 const ARMBaseInstrInfo *TII;
43 const TargetRegisterInfo *TRI;
44 const ARMSubtarget *STI;
45 ARMFunctionInfo *AFI;
46
47 virtual bool runOnMachineFunction(MachineFunction &Fn);
48
49 virtual const char *getPassName() const {
50 return "ARM pseudo instruction expansion pass";
51 }
52
53 private:
54 void TransferImpOps(MachineInstr &OldMI,
55 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
56 bool ExpandMI(MachineBasicBlock &MBB,
57 MachineBasicBlock::iterator MBBI);
58 bool ExpandMBB(MachineBasicBlock &MBB);
59 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
60 void ExpandVST(MachineBasicBlock::iterator &MBBI);
61 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
62 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
63 unsigned Opc, bool IsExt);
64 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator &MBBI);
66 };
67 char ARMExpandPseudo::ID = 0;
68}
69
70/// TransferImpOps - Transfer implicit operands on the pseudo instruction to
71/// the instructions created from the expansion.
72void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
73 MachineInstrBuilder &UseMI,
74 MachineInstrBuilder &DefMI) {
75 const MCInstrDesc &Desc = OldMI.getDesc();
76 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
77 i != e; ++i) {
78 const MachineOperand &MO = OldMI.getOperand(i);
79 assert(MO.isReg() && MO.getReg());
80 if (MO.isUse())
81 UseMI.addOperand(MO);
82 else
83 DefMI.addOperand(MO);
84 }
85}
86
87namespace {
88 // Constants for register spacing in NEON load/store instructions.
89 // For quad-register load-lane and store-lane pseudo instructors, the
90 // spacing is initially assumed to be EvenDblSpc, and that is changed to
91 // OddDblSpc depending on the lane number operand.
92 enum NEONRegSpacing {
93 SingleSpc,
94 EvenDblSpc,
95 OddDblSpc
96 };
97
98 // Entries for NEON load/store information table. The table is sorted by
99 // PseudoOpc for fast binary-search lookups.
100 struct NEONLdStTableEntry {
101 uint16_t PseudoOpc;
102 uint16_t RealOpc;
103 bool IsLoad;
104 bool isUpdating;
105 bool hasWritebackOperand;
106 uint8_t RegSpacing; // One of type NEONRegSpacing
107 uint8_t NumRegs; // D registers loaded or stored
108 uint8_t RegElts; // elements per D register; used for lane ops
109 // FIXME: Temporary flag to denote whether the real instruction takes
110 // a single register (like the encoding) or all of the registers in
111 // the list (like the asm syntax and the isel DAG). When all definitions
112 // are converted to take only the single encoded register, this will
113 // go away.
114 bool copyAllListRegs;
115
116 // Comparison methods for binary search of the table.
117 bool operator<(const NEONLdStTableEntry &TE) const {
118 return PseudoOpc < TE.PseudoOpc;
119 }
120 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
121 return TE.PseudoOpc < PseudoOpc;
122 }
123 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
124 const NEONLdStTableEntry &TE) {
125 return PseudoOpc < TE.PseudoOpc;
126 }
127 };
128}
129
130static const NEONLdStTableEntry NEONLdStTable[] = {
131{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
132{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
133{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
134{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
135{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
136{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
137
138{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
139{ ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
140{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
141{ ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
142
143{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
144{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
145{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
146{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
147{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
148{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
149{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
150{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
151{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
152{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
153
154{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
155{ ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
156{ ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
157{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
158{ ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
159{ ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
160{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
161{ ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
162{ ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
163
164{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
165{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
166{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
167{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
168{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
169{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
170
171{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
172{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
173{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
174{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
175{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
176{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
177{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
178{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
179{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
180{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
181
182{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
183{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
184{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
185{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
186{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
187{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
188
189{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
190{ ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
191{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
192{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
193{ ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
194{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
195{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
196{ ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
197{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
198
199{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
200{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
201{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
202{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
203{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
204{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
205
206{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
207{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
208{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
209{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
210{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
211{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
212{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
213{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
214{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
215{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
216
217{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
218{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
219{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
220{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
221{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
222{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
223
224{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
225{ ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
226{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
227{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
228{ ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
229{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
230{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
231{ ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
232{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
233
234{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
235{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
236{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
237{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
238{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
239{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
240
241{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
242{ ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
243{ ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
244{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
245{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
246{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
247
248{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
249{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
250{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
251{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
252{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
253{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
254{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
255{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
256{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
257{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
258
259{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
260{ ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
261{ ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
262{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
263{ ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
264{ ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
265{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
266{ ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
267{ ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
268
269{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
270{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
271{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
272{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
273{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
274{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
275{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
276{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
277{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
278{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
279
280{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
281{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
282{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
283{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
284{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
285{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
286
287{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
288{ ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
289{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
290{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
291{ ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
292{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
293{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
294{ ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
295{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
296
297{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
298{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
299{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
300{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
301{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
302{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
303{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
304{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
305{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
306{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
307
308{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
309{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
310{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
311{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
312{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
313{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
314
315{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
316{ ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
317{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
318{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
319{ ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
320{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
321{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
322{ ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
323{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
324};
325
326/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
327/// load or store pseudo instruction.
328static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
329 const unsigned NumEntries = array_lengthof(NEONLdStTable);
330
331#ifndef NDEBUG
332 // Make sure the table is sorted.
333 static bool TableChecked = false;
334 if (!TableChecked) {
335 for (unsigned i = 0; i != NumEntries-1; ++i)
336 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
337 "NEONLdStTable is not sorted!");
338 TableChecked = true;
339 }
340#endif
341
342 const NEONLdStTableEntry *I =
343 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
344 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
345 return I;
346 return NULL;
347}
348
349/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
350/// corresponding to the specified register spacing. Not all of the results
351/// are necessarily valid, e.g., a Q register only has 2 D subregisters.
352static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
353 const TargetRegisterInfo *TRI, unsigned &D0,
354 unsigned &D1, unsigned &D2, unsigned &D3) {
355 if (RegSpc == SingleSpc) {
356 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
357 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
358 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
359 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
360 } else if (RegSpc == EvenDblSpc) {
361 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
362 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
363 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
364 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
365 } else {
366 assert(RegSpc == OddDblSpc && "unknown register spacing");
367 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
368 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
369 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
370 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
371 }
372}
373
374/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
375/// operands to real VLD instructions with D register operands.
376void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
377 MachineInstr &MI = *MBBI;
378 MachineBasicBlock &MBB = *MI.getParent();
379
380 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
381 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
382 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
383 unsigned NumRegs = TableEntry->NumRegs;
384
385 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
386 TII->get(TableEntry->RealOpc));
387 unsigned OpIdx = 0;
388
389 bool DstIsDead = MI.getOperand(OpIdx).isDead();
390 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
391 unsigned D0, D1, D2, D3;
392 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
393 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
394 if (NumRegs > 1 && TableEntry->copyAllListRegs)
395 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
396 if (NumRegs > 2 && TableEntry->copyAllListRegs)
397 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
398 if (NumRegs > 3 && TableEntry->copyAllListRegs)
399 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
400
401 if (TableEntry->isUpdating)
402 MIB.addOperand(MI.getOperand(OpIdx++));
403
404 // Copy the addrmode6 operands.
405 MIB.addOperand(MI.getOperand(OpIdx++));
406 MIB.addOperand(MI.getOperand(OpIdx++));
407 // Copy the am6offset operand.
408 if (TableEntry->hasWritebackOperand)
409 MIB.addOperand(MI.getOperand(OpIdx++));
410
411 // For an instruction writing double-spaced subregs, the pseudo instruction
412 // has an extra operand that is a use of the super-register. Record the
413 // operand index and skip over it.
414 unsigned SrcOpIdx = 0;
415 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
416 SrcOpIdx = OpIdx++;
417
418 // Copy the predicate operands.
419 MIB.addOperand(MI.getOperand(OpIdx++));
420 MIB.addOperand(MI.getOperand(OpIdx++));
421
422 // Copy the super-register source operand used for double-spaced subregs over
423 // to the new instruction as an implicit operand.
424 if (SrcOpIdx != 0) {
425 MachineOperand MO = MI.getOperand(SrcOpIdx);
426 MO.setImplicit(true);
427 MIB.addOperand(MO);
428 }
429 // Add an implicit def for the super-register.
430 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
431 TransferImpOps(MI, MIB, MIB);
432
433 // Transfer memoperands.
434 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
435
436 MI.eraseFromParent();
437}
438
439/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
440/// operands to real VST instructions with D register operands.
441void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
442 MachineInstr &MI = *MBBI;
443 MachineBasicBlock &MBB = *MI.getParent();
444
445 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
446 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
447 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
448 unsigned NumRegs = TableEntry->NumRegs;
449
450 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
451 TII->get(TableEntry->RealOpc));
452 unsigned OpIdx = 0;
453 if (TableEntry->isUpdating)
454 MIB.addOperand(MI.getOperand(OpIdx++));
455
456 // Copy the addrmode6 operands.
457 MIB.addOperand(MI.getOperand(OpIdx++));
458 MIB.addOperand(MI.getOperand(OpIdx++));
459 // Copy the am6offset operand.
460 if (TableEntry->hasWritebackOperand)
461 MIB.addOperand(MI.getOperand(OpIdx++));
462
463 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
464 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
465 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
466 unsigned D0, D1, D2, D3;
467 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
468 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
469 if (NumRegs > 1 && TableEntry->copyAllListRegs)
470 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
471 if (NumRegs > 2 && TableEntry->copyAllListRegs)
472 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
473 if (NumRegs > 3 && TableEntry->copyAllListRegs)
474 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
475
476 // Copy the predicate operands.
477 MIB.addOperand(MI.getOperand(OpIdx++));
478 MIB.addOperand(MI.getOperand(OpIdx++));
479
480 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
481 MIB->addRegisterKilled(SrcReg, TRI, true);
482 TransferImpOps(MI, MIB, MIB);
483
484 // Transfer memoperands.
485 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
486
487 MI.eraseFromParent();
488}
489
490/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
491/// register operands to real instructions with D register operands.
492void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
493 MachineInstr &MI = *MBBI;
494 MachineBasicBlock &MBB = *MI.getParent();
495
496 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
497 assert(TableEntry && "NEONLdStTable lookup failed");
498 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
499 unsigned NumRegs = TableEntry->NumRegs;
500 unsigned RegElts = TableEntry->RegElts;
501
502 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
503 TII->get(TableEntry->RealOpc));
504 unsigned OpIdx = 0;
505 // The lane operand is always the 3rd from last operand, before the 2
506 // predicate operands.
507 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
508
509 // Adjust the lane and spacing as needed for Q registers.
510 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
511 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
512 RegSpc = OddDblSpc;
513 Lane -= RegElts;
514 }
515 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
516
517 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
518 unsigned DstReg = 0;
519 bool DstIsDead = false;
520 if (TableEntry->IsLoad) {
521 DstIsDead = MI.getOperand(OpIdx).isDead();
522 DstReg = MI.getOperand(OpIdx++).getReg();
523 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
524 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
525 if (NumRegs > 1)
526 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
527 if (NumRegs > 2)
528 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
529 if (NumRegs > 3)
530 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
531 }
532
533 if (TableEntry->isUpdating)
534 MIB.addOperand(MI.getOperand(OpIdx++));
535
536 // Copy the addrmode6 operands.
537 MIB.addOperand(MI.getOperand(OpIdx++));
538 MIB.addOperand(MI.getOperand(OpIdx++));
539 // Copy the am6offset operand.
540 if (TableEntry->hasWritebackOperand)
541 MIB.addOperand(MI.getOperand(OpIdx++));
542
543 // Grab the super-register source.
544 MachineOperand MO = MI.getOperand(OpIdx++);
545 if (!TableEntry->IsLoad)
546 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
547
548 // Add the subregs as sources of the new instruction.
549 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
550 getKillRegState(MO.isKill()));
551 MIB.addReg(D0, SrcFlags);
552 if (NumRegs > 1)
553 MIB.addReg(D1, SrcFlags);
554 if (NumRegs > 2)
555 MIB.addReg(D2, SrcFlags);
556 if (NumRegs > 3)
557 MIB.addReg(D3, SrcFlags);
558
559 // Add the lane number operand.
560 MIB.addImm(Lane);
561 OpIdx += 1;
562
563 // Copy the predicate operands.
564 MIB.addOperand(MI.getOperand(OpIdx++));
565 MIB.addOperand(MI.getOperand(OpIdx++));
566
567 // Copy the super-register source to be an implicit source.
568 MO.setImplicit(true);
569 MIB.addOperand(MO);
570 if (TableEntry->IsLoad)
571 // Add an implicit def for the super-register.
572 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
573 TransferImpOps(MI, MIB, MIB);
574 // Transfer memoperands.
575 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
576 MI.eraseFromParent();
577}
578
579/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
580/// register operands to real instructions with D register operands.
581void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
582 unsigned Opc, bool IsExt) {
583 MachineInstr &MI = *MBBI;
584 MachineBasicBlock &MBB = *MI.getParent();
585
586 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
587 unsigned OpIdx = 0;
588
589 // Transfer the destination register operand.
590 MIB.addOperand(MI.getOperand(OpIdx++));
591 if (IsExt)
592 MIB.addOperand(MI.getOperand(OpIdx++));
593
594 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
595 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
596 unsigned D0, D1, D2, D3;
597 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
598 MIB.addReg(D0);
599
600 // Copy the other source register operand.
601 MIB.addOperand(MI.getOperand(OpIdx++));
602
603 // Copy the predicate operands.
604 MIB.addOperand(MI.getOperand(OpIdx++));
605 MIB.addOperand(MI.getOperand(OpIdx++));
606
607 if (SrcIsKill) // Add an implicit kill for the super-reg.
608 MIB->addRegisterKilled(SrcReg, TRI, true);
609 TransferImpOps(MI, MIB, MIB);
610 MI.eraseFromParent();
611}
612
613void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
614 MachineBasicBlock::iterator &MBBI) {
615 MachineInstr &MI = *MBBI;
616 unsigned Opcode = MI.getOpcode();
617 unsigned PredReg = 0;
618 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
619 unsigned DstReg = MI.getOperand(0).getReg();
620 bool DstIsDead = MI.getOperand(0).isDead();
621 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
622 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
623 MachineInstrBuilder LO16, HI16;
624
625 if (!STI->hasV6T2Ops() &&
626 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
627 // Expand into a movi + orr.
628 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
629 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
630 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
631 .addReg(DstReg);
632
633 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
634 unsigned ImmVal = (unsigned)MO.getImm();
635 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
636 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
637 LO16 = LO16.addImm(SOImmValV1);
638 HI16 = HI16.addImm(SOImmValV2);
639 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
640 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
641 LO16.addImm(Pred).addReg(PredReg).addReg(0);
642 HI16.addImm(Pred).addReg(PredReg).addReg(0);
643 TransferImpOps(MI, LO16, HI16);
644 MI.eraseFromParent();
645 return;
646 }
647
648 unsigned LO16Opc = 0;
649 unsigned HI16Opc = 0;
650 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
651 LO16Opc = ARM::t2MOVi16;
652 HI16Opc = ARM::t2MOVTi16;
653 } else {
654 LO16Opc = ARM::MOVi16;
655 HI16Opc = ARM::MOVTi16;
656 }
657
658 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
659 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
660 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
661 .addReg(DstReg);
662
663 if (MO.isImm()) {
664 unsigned Imm = MO.getImm();
665 unsigned Lo16 = Imm & 0xffff;
666 unsigned Hi16 = (Imm >> 16) & 0xffff;
667 LO16 = LO16.addImm(Lo16);
668 HI16 = HI16.addImm(Hi16);
669 } else {
670 const GlobalValue *GV = MO.getGlobal();
671 unsigned TF = MO.getTargetFlags();
672 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
673 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
674 }
675
676 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
677 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
678 LO16.addImm(Pred).addReg(PredReg);
679 HI16.addImm(Pred).addReg(PredReg);
680
681 TransferImpOps(MI, LO16, HI16);
682 MI.eraseFromParent();
683}
684
685bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
686 MachineBasicBlock::iterator MBBI) {
687 MachineInstr &MI = *MBBI;
688 unsigned Opcode = MI.getOpcode();
689 switch (Opcode) {
690 default:
691 return false;
692 case ARM::VMOVScc:
693 case ARM::VMOVDcc: {
694 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
695 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
696 MI.getOperand(1).getReg())
697 .addOperand(MI.getOperand(2))
698 .addImm(MI.getOperand(3).getImm()) // 'pred'
699 .addOperand(MI.getOperand(4));
700
701 MI.eraseFromParent();
702 return true;
703 }
704 case ARM::t2MOVCCr:
705 case ARM::MOVCCr: {
706 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
707 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
708 MI.getOperand(1).getReg())
709 .addOperand(MI.getOperand(2))
710 .addImm(MI.getOperand(3).getImm()) // 'pred'
711 .addOperand(MI.getOperand(4))
712 .addReg(0); // 's' bit
713
714 MI.eraseFromParent();
715 return true;
716 }
717 case ARM::MOVCCsi: {
718 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
719 (MI.getOperand(1).getReg()))
720 .addOperand(MI.getOperand(2))
721 .addImm(MI.getOperand(3).getImm())
722 .addImm(MI.getOperand(4).getImm()) // 'pred'
723 .addOperand(MI.getOperand(5))
724 .addReg(0); // 's' bit
725
726 MI.eraseFromParent();
727 return true;
728 }
729 case ARM::MOVCCsr: {
730 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
731 (MI.getOperand(1).getReg()))
732 .addOperand(MI.getOperand(2))
733 .addOperand(MI.getOperand(3))
734 .addImm(MI.getOperand(4).getImm())
735 .addImm(MI.getOperand(5).getImm()) // 'pred'
736 .addOperand(MI.getOperand(6))
737 .addReg(0); // 's' bit
738
739 MI.eraseFromParent();
740 return true;
741 }
742 case ARM::t2MOVCCi16:
743 case ARM::MOVCCi16: {
744 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
745 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
746 MI.getOperand(1).getReg())
747 .addImm(MI.getOperand(2).getImm())
748 .addImm(MI.getOperand(3).getImm()) // 'pred'
749 .addOperand(MI.getOperand(4));
750 MI.eraseFromParent();
751 return true;
752 }
753 case ARM::t2MOVCCi:
754 case ARM::MOVCCi: {
755 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
756 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
757 MI.getOperand(1).getReg())
758 .addImm(MI.getOperand(2).getImm())
759 .addImm(MI.getOperand(3).getImm()) // 'pred'
760 .addOperand(MI.getOperand(4))
761 .addReg(0); // 's' bit
762
763 MI.eraseFromParent();
764 return true;
765 }
766 case ARM::t2MVNCCi:
767 case ARM::MVNCCi: {
768 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
769 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
770 MI.getOperand(1).getReg())
771 .addImm(MI.getOperand(2).getImm())
772 .addImm(MI.getOperand(3).getImm()) // 'pred'
773 .addOperand(MI.getOperand(4))
774 .addReg(0); // 's' bit
775
776 MI.eraseFromParent();
777 return true;
778 }
779 case ARM::t2MOVCClsl:
780 case ARM::t2MOVCClsr:
781 case ARM::t2MOVCCasr:
782 case ARM::t2MOVCCror: {
783 unsigned NewOpc;
784 switch (Opcode) {
785 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
786 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
787 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
788 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
789 default: llvm_unreachable("unexpeced conditional move");
790 }
791 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
792 MI.getOperand(1).getReg())
793 .addOperand(MI.getOperand(2))
794 .addImm(MI.getOperand(3).getImm())
795 .addImm(MI.getOperand(4).getImm()) // 'pred'
796 .addOperand(MI.getOperand(5))
797 .addReg(0); // 's' bit
798 MI.eraseFromParent();
799 return true;
800 }
801 case ARM::Int_eh_sjlj_dispatchsetup: {
802 MachineFunction &MF = *MI.getParent()->getParent();
803 const ARMBaseInstrInfo *AII =
804 static_cast<const ARMBaseInstrInfo*>(TII);
805 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
806 // For functions using a base pointer, we rematerialize it (via the frame
807 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
808 // for us. Otherwise, expand to nothing.
809 if (RI.hasBasePointer(MF)) {
810 int32_t NumBytes = AFI->getFramePtrSpillOffset();
811 unsigned FramePtr = RI.getFrameRegister(MF);
812 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
813 "base pointer without frame pointer?");
814
815 if (AFI->isThumb2Function()) {
816 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
817 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
818 } else if (AFI->isThumbFunction()) {
819 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
820 FramePtr, -NumBytes, *TII, RI);
821 } else {
822 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
823 FramePtr, -NumBytes, ARMCC::AL, 0,
824 *TII);
825 }
826 // If there's dynamic realignment, adjust for it.
827 if (RI.needsStackRealignment(MF)) {
828 MachineFrameInfo *MFI = MF.getFrameInfo();
829 unsigned MaxAlign = MFI->getMaxAlignment();
830 assert (!AFI->isThumb1OnlyFunction());
831 // Emit bic r6, r6, MaxAlign
832 unsigned bicOpc = AFI->isThumbFunction() ?
833 ARM::t2BICri : ARM::BICri;
834 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
835 TII->get(bicOpc), ARM::R6)
836 .addReg(ARM::R6, RegState::Kill)
837 .addImm(MaxAlign-1)));
838 }
839
840 }
841 MI.eraseFromParent();
842 return true;
843 }
844
845 case ARM::MOVsrl_flag:
846 case ARM::MOVsra_flag: {
847 // These are just fancy MOVs instructions.
848 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
849 MI.getOperand(0).getReg())
850 .addOperand(MI.getOperand(1))
851 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
852 ARM_AM::lsr : ARM_AM::asr),
853 1)))
854 .addReg(ARM::CPSR, RegState::Define);
855 MI.eraseFromParent();
856 return true;
857 }
858 case ARM::RRX: {
859 // This encodes as "MOVs Rd, Rm, rrx
860 MachineInstrBuilder MIB =
861 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
862 MI.getOperand(0).getReg())
863 .addOperand(MI.getOperand(1))
864 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
865 .addReg(0);
866 TransferImpOps(MI, MIB, MIB);
867 MI.eraseFromParent();
868 return true;
869 }
870 case ARM::tTPsoft:
871 case ARM::TPsoft: {
872 MachineInstrBuilder MIB =
873 BuildMI(MBB, MBBI, MI.getDebugLoc(),
874 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
875 .addExternalSymbol("__aeabi_read_tp", 0);
876
877 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
878 TransferImpOps(MI, MIB, MIB);
879 MI.eraseFromParent();
880 return true;
881 }
882 case ARM::tLDRpci_pic:
883 case ARM::t2LDRpci_pic: {
884 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
885 ? ARM::tLDRpci : ARM::t2LDRpci;
886 unsigned DstReg = MI.getOperand(0).getReg();
887 bool DstIsDead = MI.getOperand(0).isDead();
888 MachineInstrBuilder MIB1 =
889 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
890 TII->get(NewLdOpc), DstReg)
891 .addOperand(MI.getOperand(1)));
892 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
893 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
894 TII->get(ARM::tPICADD))
895 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
896 .addReg(DstReg)
897 .addOperand(MI.getOperand(2));
898 TransferImpOps(MI, MIB1, MIB2);
899 MI.eraseFromParent();
900 return true;
901 }
902
903 case ARM::MOV_ga_dyn:
904 case ARM::MOV_ga_pcrel:
905 case ARM::MOV_ga_pcrel_ldr:
906 case ARM::t2MOV_ga_dyn:
907 case ARM::t2MOV_ga_pcrel: {
908 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
909 unsigned LabelId = AFI->createPICLabelUId();
910 unsigned DstReg = MI.getOperand(0).getReg();
911 bool DstIsDead = MI.getOperand(0).isDead();
912 const MachineOperand &MO1 = MI.getOperand(1);
913 const GlobalValue *GV = MO1.getGlobal();
914 unsigned TF = MO1.getTargetFlags();
915 bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode!=ARM::t2MOV_ga_dyn);
916 bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn);
917 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
918 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
919 unsigned LO16TF = isPIC
920 ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY;
921 unsigned HI16TF = isPIC
922 ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY;
923 unsigned PICAddOpc = isARM
924 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
925 : ARM::tPICADD;
926 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
927 TII->get(LO16Opc), DstReg)
928 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
929 .addImm(LabelId);
930 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
931 TII->get(HI16Opc), DstReg)
932 .addReg(DstReg)
933 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
934 .addImm(LabelId);
935 if (!isPIC) {
936 TransferImpOps(MI, MIB1, MIB2);
937 MI.eraseFromParent();
938 return true;
939 }
940
941 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
942 TII->get(PICAddOpc))
943 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
944 .addReg(DstReg).addImm(LabelId);
945 if (isARM) {
946 AddDefaultPred(MIB3);
947 if (Opcode == ARM::MOV_ga_pcrel_ldr)
948 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
949 }
950 TransferImpOps(MI, MIB1, MIB3);
951 MI.eraseFromParent();
952 return true;
953 }
954
955 case ARM::MOVi32imm:
956 case ARM::MOVCCi32imm:
957 case ARM::t2MOVi32imm:
958 case ARM::t2MOVCCi32imm:
959 ExpandMOV32BitImm(MBB, MBBI);
960 return true;
961
962 case ARM::SUBS_PC_LR: {
963 MachineInstrBuilder MIB =
964 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
965 .addReg(ARM::LR)
966 .addOperand(MI.getOperand(0))
967 .addOperand(MI.getOperand(1))
968 .addOperand(MI.getOperand(2))
969 .addReg(ARM::CPSR, RegState::Undef);
970 TransferImpOps(MI, MIB, MIB);
971 MI.eraseFromParent();
972 return true;
973 }
974 case ARM::VLDMQIA: {
975 unsigned NewOpc = ARM::VLDMDIA;
976 MachineInstrBuilder MIB =
977 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
978 unsigned OpIdx = 0;
979
980 // Grab the Q register destination.
981 bool DstIsDead = MI.getOperand(OpIdx).isDead();
982 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
983
984 // Copy the source register.
985 MIB.addOperand(MI.getOperand(OpIdx++));
986
987 // Copy the predicate operands.
988 MIB.addOperand(MI.getOperand(OpIdx++));
989 MIB.addOperand(MI.getOperand(OpIdx++));
990
991 // Add the destination operands (D subregs).
992 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
993 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
994 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
995 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
996
997 // Add an implicit def for the super-register.
998 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
999 TransferImpOps(MI, MIB, MIB);
1000 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1001 MI.eraseFromParent();
1002 return true;
1003 }
1004
1005 case ARM::VSTMQIA: {
1006 unsigned NewOpc = ARM::VSTMDIA;
1007 MachineInstrBuilder MIB =
1008 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1009 unsigned OpIdx = 0;
1010
1011 // Grab the Q register source.
1012 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1013 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1014
1015 // Copy the destination register.
1016 MIB.addOperand(MI.getOperand(OpIdx++));
1017
1018 // Copy the predicate operands.
1019 MIB.addOperand(MI.getOperand(OpIdx++));
1020 MIB.addOperand(MI.getOperand(OpIdx++));
1021
1022 // Add the source operands (D subregs).
1023 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1024 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1025 MIB.addReg(D0).addReg(D1);
1026
1027 if (SrcIsKill) // Add an implicit kill for the Q register.
1028 MIB->addRegisterKilled(SrcReg, TRI, true);
1029
1030 TransferImpOps(MI, MIB, MIB);
1031 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1032 MI.eraseFromParent();
1033 return true;
1034 }
1035 case ARM::VDUPfqf:
1036 case ARM::VDUPfdf:{
1037 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
1038 ARM::VDUPLN32d;
1039 MachineInstrBuilder MIB =
1040 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1041 unsigned OpIdx = 0;
1042 unsigned SrcReg = MI.getOperand(1).getReg();
1043 unsigned Lane = TRI->getEncodingValue(SrcReg) & 1;
1044 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
1045 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
1046 &ARM::DPR_VFP2RegClass);
1047 // The lane is [0,1] for the containing DReg superregister.
1048 // Copy the dst/src register operands.
1049 MIB.addOperand(MI.getOperand(OpIdx++));
1050 MIB.addReg(DReg);
1051 ++OpIdx;
1052 // Add the lane select operand.
1053 MIB.addImm(Lane);
1054 // Add the predicate operands.
1055 MIB.addOperand(MI.getOperand(OpIdx++));
1056 MIB.addOperand(MI.getOperand(OpIdx++));
1057
1058 TransferImpOps(MI, MIB, MIB);
1059 MI.eraseFromParent();
1060 return true;
1061 }
1062
1063 case ARM::VLD2q8Pseudo:
1064 case ARM::VLD2q16Pseudo:
1065 case ARM::VLD2q32Pseudo:
1066 case ARM::VLD2q8PseudoWB_fixed:
1067 case ARM::VLD2q16PseudoWB_fixed:
1068 case ARM::VLD2q32PseudoWB_fixed:
1069 case ARM::VLD2q8PseudoWB_register:
1070 case ARM::VLD2q16PseudoWB_register:
1071 case ARM::VLD2q32PseudoWB_register:
1072 case ARM::VLD3d8Pseudo:
1073 case ARM::VLD3d16Pseudo:
1074 case ARM::VLD3d32Pseudo:
1075 case ARM::VLD1d64TPseudo:
1076 case ARM::VLD1d64TPseudoWB_fixed:
1077 case ARM::VLD3d8Pseudo_UPD:
1078 case ARM::VLD3d16Pseudo_UPD:
1079 case ARM::VLD3d32Pseudo_UPD:
1080 case ARM::VLD3q8Pseudo_UPD:
1081 case ARM::VLD3q16Pseudo_UPD:
1082 case ARM::VLD3q32Pseudo_UPD:
1083 case ARM::VLD3q8oddPseudo:
1084 case ARM::VLD3q16oddPseudo:
1085 case ARM::VLD3q32oddPseudo:
1086 case ARM::VLD3q8oddPseudo_UPD:
1087 case ARM::VLD3q16oddPseudo_UPD:
1088 case ARM::VLD3q32oddPseudo_UPD:
1089 case ARM::VLD4d8Pseudo:
1090 case ARM::VLD4d16Pseudo:
1091 case ARM::VLD4d32Pseudo:
1092 case ARM::VLD1d64QPseudo:
1093 case ARM::VLD1d64QPseudoWB_fixed:
1094 case ARM::VLD4d8Pseudo_UPD:
1095 case ARM::VLD4d16Pseudo_UPD:
1096 case ARM::VLD4d32Pseudo_UPD:
1097 case ARM::VLD4q8Pseudo_UPD:
1098 case ARM::VLD4q16Pseudo_UPD:
1099 case ARM::VLD4q32Pseudo_UPD:
1100 case ARM::VLD4q8oddPseudo:
1101 case ARM::VLD4q16oddPseudo:
1102 case ARM::VLD4q32oddPseudo:
1103 case ARM::VLD4q8oddPseudo_UPD:
1104 case ARM::VLD4q16oddPseudo_UPD:
1105 case ARM::VLD4q32oddPseudo_UPD:
1106 case ARM::VLD3DUPd8Pseudo:
1107 case ARM::VLD3DUPd16Pseudo:
1108 case ARM::VLD3DUPd32Pseudo:
1109 case ARM::VLD3DUPd8Pseudo_UPD:
1110 case ARM::VLD3DUPd16Pseudo_UPD:
1111 case ARM::VLD3DUPd32Pseudo_UPD:
1112 case ARM::VLD4DUPd8Pseudo:
1113 case ARM::VLD4DUPd16Pseudo:
1114 case ARM::VLD4DUPd32Pseudo:
1115 case ARM::VLD4DUPd8Pseudo_UPD:
1116 case ARM::VLD4DUPd16Pseudo_UPD:
1117 case ARM::VLD4DUPd32Pseudo_UPD:
1118 ExpandVLD(MBBI);
1119 return true;
1120
1121 case ARM::VST2q8Pseudo:
1122 case ARM::VST2q16Pseudo:
1123 case ARM::VST2q32Pseudo:
1124 case ARM::VST2q8PseudoWB_fixed:
1125 case ARM::VST2q16PseudoWB_fixed:
1126 case ARM::VST2q32PseudoWB_fixed:
1127 case ARM::VST2q8PseudoWB_register:
1128 case ARM::VST2q16PseudoWB_register:
1129 case ARM::VST2q32PseudoWB_register:
1130 case ARM::VST3d8Pseudo:
1131 case ARM::VST3d16Pseudo:
1132 case ARM::VST3d32Pseudo:
1133 case ARM::VST1d64TPseudo:
1134 case ARM::VST3d8Pseudo_UPD:
1135 case ARM::VST3d16Pseudo_UPD:
1136 case ARM::VST3d32Pseudo_UPD:
1137 case ARM::VST1d64TPseudoWB_fixed:
1138 case ARM::VST1d64TPseudoWB_register:
1139 case ARM::VST3q8Pseudo_UPD:
1140 case ARM::VST3q16Pseudo_UPD:
1141 case ARM::VST3q32Pseudo_UPD:
1142 case ARM::VST3q8oddPseudo:
1143 case ARM::VST3q16oddPseudo:
1144 case ARM::VST3q32oddPseudo:
1145 case ARM::VST3q8oddPseudo_UPD:
1146 case ARM::VST3q16oddPseudo_UPD:
1147 case ARM::VST3q32oddPseudo_UPD:
1148 case ARM::VST4d8Pseudo:
1149 case ARM::VST4d16Pseudo:
1150 case ARM::VST4d32Pseudo:
1151 case ARM::VST1d64QPseudo:
1152 case ARM::VST4d8Pseudo_UPD:
1153 case ARM::VST4d16Pseudo_UPD:
1154 case ARM::VST4d32Pseudo_UPD:
1155 case ARM::VST1d64QPseudoWB_fixed:
1156 case ARM::VST1d64QPseudoWB_register:
1157 case ARM::VST4q8Pseudo_UPD:
1158 case ARM::VST4q16Pseudo_UPD:
1159 case ARM::VST4q32Pseudo_UPD:
1160 case ARM::VST4q8oddPseudo:
1161 case ARM::VST4q16oddPseudo:
1162 case ARM::VST4q32oddPseudo:
1163 case ARM::VST4q8oddPseudo_UPD:
1164 case ARM::VST4q16oddPseudo_UPD:
1165 case ARM::VST4q32oddPseudo_UPD:
1166 ExpandVST(MBBI);
1167 return true;
1168
1169 case ARM::VLD1LNq8Pseudo:
1170 case ARM::VLD1LNq16Pseudo:
1171 case ARM::VLD1LNq32Pseudo:
1172 case ARM::VLD1LNq8Pseudo_UPD:
1173 case ARM::VLD1LNq16Pseudo_UPD:
1174 case ARM::VLD1LNq32Pseudo_UPD:
1175 case ARM::VLD2LNd8Pseudo:
1176 case ARM::VLD2LNd16Pseudo:
1177 case ARM::VLD2LNd32Pseudo:
1178 case ARM::VLD2LNq16Pseudo:
1179 case ARM::VLD2LNq32Pseudo:
1180 case ARM::VLD2LNd8Pseudo_UPD:
1181 case ARM::VLD2LNd16Pseudo_UPD:
1182 case ARM::VLD2LNd32Pseudo_UPD:
1183 case ARM::VLD2LNq16Pseudo_UPD:
1184 case ARM::VLD2LNq32Pseudo_UPD:
1185 case ARM::VLD3LNd8Pseudo:
1186 case ARM::VLD3LNd16Pseudo:
1187 case ARM::VLD3LNd32Pseudo:
1188 case ARM::VLD3LNq16Pseudo:
1189 case ARM::VLD3LNq32Pseudo:
1190 case ARM::VLD3LNd8Pseudo_UPD:
1191 case ARM::VLD3LNd16Pseudo_UPD:
1192 case ARM::VLD3LNd32Pseudo_UPD:
1193 case ARM::VLD3LNq16Pseudo_UPD:
1194 case ARM::VLD3LNq32Pseudo_UPD:
1195 case ARM::VLD4LNd8Pseudo:
1196 case ARM::VLD4LNd16Pseudo:
1197 case ARM::VLD4LNd32Pseudo:
1198 case ARM::VLD4LNq16Pseudo:
1199 case ARM::VLD4LNq32Pseudo:
1200 case ARM::VLD4LNd8Pseudo_UPD:
1201 case ARM::VLD4LNd16Pseudo_UPD:
1202 case ARM::VLD4LNd32Pseudo_UPD:
1203 case ARM::VLD4LNq16Pseudo_UPD:
1204 case ARM::VLD4LNq32Pseudo_UPD:
1205 case ARM::VST1LNq8Pseudo:
1206 case ARM::VST1LNq16Pseudo:
1207 case ARM::VST1LNq32Pseudo:
1208 case ARM::VST1LNq8Pseudo_UPD:
1209 case ARM::VST1LNq16Pseudo_UPD:
1210 case ARM::VST1LNq32Pseudo_UPD:
1211 case ARM::VST2LNd8Pseudo:
1212 case ARM::VST2LNd16Pseudo:
1213 case ARM::VST2LNd32Pseudo:
1214 case ARM::VST2LNq16Pseudo:
1215 case ARM::VST2LNq32Pseudo:
1216 case ARM::VST2LNd8Pseudo_UPD:
1217 case ARM::VST2LNd16Pseudo_UPD:
1218 case ARM::VST2LNd32Pseudo_UPD:
1219 case ARM::VST2LNq16Pseudo_UPD:
1220 case ARM::VST2LNq32Pseudo_UPD:
1221 case ARM::VST3LNd8Pseudo:
1222 case ARM::VST3LNd16Pseudo:
1223 case ARM::VST3LNd32Pseudo:
1224 case ARM::VST3LNq16Pseudo:
1225 case ARM::VST3LNq32Pseudo:
1226 case ARM::VST3LNd8Pseudo_UPD:
1227 case ARM::VST3LNd16Pseudo_UPD:
1228 case ARM::VST3LNd32Pseudo_UPD:
1229 case ARM::VST3LNq16Pseudo_UPD:
1230 case ARM::VST3LNq32Pseudo_UPD:
1231 case ARM::VST4LNd8Pseudo:
1232 case ARM::VST4LNd16Pseudo:
1233 case ARM::VST4LNd32Pseudo:
1234 case ARM::VST4LNq16Pseudo:
1235 case ARM::VST4LNq32Pseudo:
1236 case ARM::VST4LNd8Pseudo_UPD:
1237 case ARM::VST4LNd16Pseudo_UPD:
1238 case ARM::VST4LNd32Pseudo_UPD:
1239 case ARM::VST4LNq16Pseudo_UPD:
1240 case ARM::VST4LNq32Pseudo_UPD:
1241 ExpandLaneOp(MBBI);
1242 return true;
1243
1244 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1245 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1246 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1247 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1248 }
1249}
1250
1251bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1252 bool Modified = false;
1253
1254 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1255 while (MBBI != E) {
1256 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
1257 Modified |= ExpandMI(MBB, MBBI);
1258 MBBI = NMBBI;
1259 }
1260
1261 return Modified;
1262}
1263
1264bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1265 const TargetMachine &TM = MF.getTarget();
1266 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
1267 TRI = TM.getRegisterInfo();
1268 STI = &TM.getSubtarget<ARMSubtarget>();
1269 AFI = MF.getInfo<ARMFunctionInfo>();
1270
1271 bool Modified = false;
1272 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1273 ++MFI)
1274 Modified |= ExpandMBB(*MFI);
1275 if (VerifyARMPseudo)
1276 MF.verify(this, "After expanding ARM pseudo instructions.");
1277 return Modified;
1278}
1279
1280/// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1281/// expansion pass.
1282FunctionPass *llvm::createARMExpandPseudoPass() {
1283 return new ARMExpandPseudo();
1284}
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a pass that expands pseudo instructions into target
11// instructions to allow proper scheduling, if-conversion, and other late
12// optimizations. This pass should be run after register allocation but before
13// the post-regalloc scheduling pass.
14//
15//===----------------------------------------------------------------------===//
16
17#define DEBUG_TYPE "arm-pseudo"
18#include "ARM.h"
19#include "ARMBaseInstrInfo.h"
20#include "ARMBaseRegisterInfo.h"
21#include "ARMMachineFunctionInfo.h"
22#include "MCTargetDesc/ARMAddressingModes.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunctionPass.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/Support/CommandLine.h"
27#include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
28#include "llvm/Target/TargetFrameLowering.h"
29#include "llvm/Target/TargetRegisterInfo.h"
30using namespace llvm;
31
32static cl::opt<bool>
33VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34 cl::desc("Verify machine code after expanding ARM pseudos"));
35
36namespace {
37 class ARMExpandPseudo : public MachineFunctionPass {
38 public:
39 static char ID;
40 ARMExpandPseudo() : MachineFunctionPass(ID) {}
41
42 const ARMBaseInstrInfo *TII;
43 const TargetRegisterInfo *TRI;
44 const ARMSubtarget *STI;
45 ARMFunctionInfo *AFI;
46
47 virtual bool runOnMachineFunction(MachineFunction &Fn);
48
49 virtual const char *getPassName() const {
50 return "ARM pseudo instruction expansion pass";
51 }
52
53 private:
54 void TransferImpOps(MachineInstr &OldMI,
55 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
56 bool ExpandMI(MachineBasicBlock &MBB,
57 MachineBasicBlock::iterator MBBI);
58 bool ExpandMBB(MachineBasicBlock &MBB);
59 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
60 void ExpandVST(MachineBasicBlock::iterator &MBBI);
61 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
62 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
63 unsigned Opc, bool IsExt);
64 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator &MBBI);
66 };
67 char ARMExpandPseudo::ID = 0;
68}
69
70/// TransferImpOps - Transfer implicit operands on the pseudo instruction to
71/// the instructions created from the expansion.
72void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
73 MachineInstrBuilder &UseMI,
74 MachineInstrBuilder &DefMI) {
75 const MCInstrDesc &Desc = OldMI.getDesc();
76 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
77 i != e; ++i) {
78 const MachineOperand &MO = OldMI.getOperand(i);
79 assert(MO.isReg() && MO.getReg());
80 if (MO.isUse())
81 UseMI.addOperand(MO);
82 else
83 DefMI.addOperand(MO);
84 }
85}
86
87namespace {
88 // Constants for register spacing in NEON load/store instructions.
89 // For quad-register load-lane and store-lane pseudo instructors, the
90 // spacing is initially assumed to be EvenDblSpc, and that is changed to
91 // OddDblSpc depending on the lane number operand.
92 enum NEONRegSpacing {
93 SingleSpc,
94 EvenDblSpc,
95 OddDblSpc
96 };
97
98 // Entries for NEON load/store information table. The table is sorted by
99 // PseudoOpc for fast binary-search lookups.
100 struct NEONLdStTableEntry {
101 uint16_t PseudoOpc;
102 uint16_t RealOpc;
103 bool IsLoad;
104 bool isUpdating;
105 bool hasWritebackOperand;
106 uint8_t RegSpacing; // One of type NEONRegSpacing
107 uint8_t NumRegs; // D registers loaded or stored
108 uint8_t RegElts; // elements per D register; used for lane ops
109 // FIXME: Temporary flag to denote whether the real instruction takes
110 // a single register (like the encoding) or all of the registers in
111 // the list (like the asm syntax and the isel DAG). When all definitions
112 // are converted to take only the single encoded register, this will
113 // go away.
114 bool copyAllListRegs;
115
116 // Comparison methods for binary search of the table.
117 bool operator<(const NEONLdStTableEntry &TE) const {
118 return PseudoOpc < TE.PseudoOpc;
119 }
120 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
121 return TE.PseudoOpc < PseudoOpc;
122 }
123 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
124 const NEONLdStTableEntry &TE) {
125 return PseudoOpc < TE.PseudoOpc;
126 }
127 };
128}
129
130static const NEONLdStTableEntry NEONLdStTable[] = {
131{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
132{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
133{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
134{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
135{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
136{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
137
138{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
139{ ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
140{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
141{ ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
142
143{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
144{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
145{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
146{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
147{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
148{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
149{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
150{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
151{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
152{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
153
154{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
155{ ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
156{ ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
157{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
158{ ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
159{ ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
160{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
161{ ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
162{ ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
163
164{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
165{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
166{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
167{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
168{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
169{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
170
171{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
172{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
173{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
174{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
175{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
176{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
177{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
178{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
179{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
180{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
181
182{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
183{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
184{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
185{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
186{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
187{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
188
189{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
190{ ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
191{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
192{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
193{ ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
194{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
195{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
196{ ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
197{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
198
199{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
200{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
201{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
202{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
203{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
204{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
205
206{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
207{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
208{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
209{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
210{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
211{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
212{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
213{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
214{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
215{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
216
217{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
218{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
219{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
220{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
221{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
222{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
223
224{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
225{ ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
226{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
227{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
228{ ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
229{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
230{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
231{ ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
232{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
233
234{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
235{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
236{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
237{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
238{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
239{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
240
241{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
242{ ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
243{ ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
244{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
245{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
246{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
247
248{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
249{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
250{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
251{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
252{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
253{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
254{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
255{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
256{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
257{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
258
259{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
260{ ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
261{ ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
262{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
263{ ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
264{ ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
265{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
266{ ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
267{ ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
268
269{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
270{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
271{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
272{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
273{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
274{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
275{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
276{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
277{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
278{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
279
280{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
281{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
282{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
283{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
284{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
285{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
286
287{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
288{ ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
289{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
290{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
291{ ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
292{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
293{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
294{ ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
295{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
296
297{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
298{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
299{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
300{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
301{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
302{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
303{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
304{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
305{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
306{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
307
308{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
309{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
310{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
311{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
312{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
313{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
314
315{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
316{ ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
317{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
318{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
319{ ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
320{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
321{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
322{ ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
323{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
324};
325
326/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
327/// load or store pseudo instruction.
328static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
329 const unsigned NumEntries = array_lengthof(NEONLdStTable);
330
331#ifndef NDEBUG
332 // Make sure the table is sorted.
333 static bool TableChecked = false;
334 if (!TableChecked) {
335 for (unsigned i = 0; i != NumEntries-1; ++i)
336 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
337 "NEONLdStTable is not sorted!");
338 TableChecked = true;
339 }
340#endif
341
342 const NEONLdStTableEntry *I =
343 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
344 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
345 return I;
346 return NULL;
347}
348
349/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
350/// corresponding to the specified register spacing. Not all of the results
351/// are necessarily valid, e.g., a Q register only has 2 D subregisters.
352static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
353 const TargetRegisterInfo *TRI, unsigned &D0,
354 unsigned &D1, unsigned &D2, unsigned &D3) {
355 if (RegSpc == SingleSpc) {
356 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
357 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
358 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
359 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
360 } else if (RegSpc == EvenDblSpc) {
361 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
362 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
363 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
364 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
365 } else {
366 assert(RegSpc == OddDblSpc && "unknown register spacing");
367 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
368 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
369 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
370 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
371 }
372}
373
374/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
375/// operands to real VLD instructions with D register operands.
376void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
377 MachineInstr &MI = *MBBI;
378 MachineBasicBlock &MBB = *MI.getParent();
379
380 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
381 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
382 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
383 unsigned NumRegs = TableEntry->NumRegs;
384
385 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
386 TII->get(TableEntry->RealOpc));
387 unsigned OpIdx = 0;
388
389 bool DstIsDead = MI.getOperand(OpIdx).isDead();
390 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
391 unsigned D0, D1, D2, D3;
392 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
393 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
394 if (NumRegs > 1 && TableEntry->copyAllListRegs)
395 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
396 if (NumRegs > 2 && TableEntry->copyAllListRegs)
397 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
398 if (NumRegs > 3 && TableEntry->copyAllListRegs)
399 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
400
401 if (TableEntry->isUpdating)
402 MIB.addOperand(MI.getOperand(OpIdx++));
403
404 // Copy the addrmode6 operands.
405 MIB.addOperand(MI.getOperand(OpIdx++));
406 MIB.addOperand(MI.getOperand(OpIdx++));
407 // Copy the am6offset operand.
408 if (TableEntry->hasWritebackOperand)
409 MIB.addOperand(MI.getOperand(OpIdx++));
410
411 // For an instruction writing double-spaced subregs, the pseudo instruction
412 // has an extra operand that is a use of the super-register. Record the
413 // operand index and skip over it.
414 unsigned SrcOpIdx = 0;
415 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
416 SrcOpIdx = OpIdx++;
417
418 // Copy the predicate operands.
419 MIB.addOperand(MI.getOperand(OpIdx++));
420 MIB.addOperand(MI.getOperand(OpIdx++));
421
422 // Copy the super-register source operand used for double-spaced subregs over
423 // to the new instruction as an implicit operand.
424 if (SrcOpIdx != 0) {
425 MachineOperand MO = MI.getOperand(SrcOpIdx);
426 MO.setImplicit(true);
427 MIB.addOperand(MO);
428 }
429 // Add an implicit def for the super-register.
430 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
431 TransferImpOps(MI, MIB, MIB);
432
433 // Transfer memoperands.
434 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
435
436 MI.eraseFromParent();
437}
438
439/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
440/// operands to real VST instructions with D register operands.
441void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
442 MachineInstr &MI = *MBBI;
443 MachineBasicBlock &MBB = *MI.getParent();
444
445 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
446 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
447 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
448 unsigned NumRegs = TableEntry->NumRegs;
449
450 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
451 TII->get(TableEntry->RealOpc));
452 unsigned OpIdx = 0;
453 if (TableEntry->isUpdating)
454 MIB.addOperand(MI.getOperand(OpIdx++));
455
456 // Copy the addrmode6 operands.
457 MIB.addOperand(MI.getOperand(OpIdx++));
458 MIB.addOperand(MI.getOperand(OpIdx++));
459 // Copy the am6offset operand.
460 if (TableEntry->hasWritebackOperand)
461 MIB.addOperand(MI.getOperand(OpIdx++));
462
463 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
464 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
465 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
466 unsigned D0, D1, D2, D3;
467 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
468 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
469 if (NumRegs > 1 && TableEntry->copyAllListRegs)
470 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
471 if (NumRegs > 2 && TableEntry->copyAllListRegs)
472 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
473 if (NumRegs > 3 && TableEntry->copyAllListRegs)
474 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
475
476 // Copy the predicate operands.
477 MIB.addOperand(MI.getOperand(OpIdx++));
478 MIB.addOperand(MI.getOperand(OpIdx++));
479
480 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
481 MIB->addRegisterKilled(SrcReg, TRI, true);
482 TransferImpOps(MI, MIB, MIB);
483
484 // Transfer memoperands.
485 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
486
487 MI.eraseFromParent();
488}
489
490/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
491/// register operands to real instructions with D register operands.
492void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
493 MachineInstr &MI = *MBBI;
494 MachineBasicBlock &MBB = *MI.getParent();
495
496 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
497 assert(TableEntry && "NEONLdStTable lookup failed");
498 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
499 unsigned NumRegs = TableEntry->NumRegs;
500 unsigned RegElts = TableEntry->RegElts;
501
502 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
503 TII->get(TableEntry->RealOpc));
504 unsigned OpIdx = 0;
505 // The lane operand is always the 3rd from last operand, before the 2
506 // predicate operands.
507 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
508
509 // Adjust the lane and spacing as needed for Q registers.
510 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
511 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
512 RegSpc = OddDblSpc;
513 Lane -= RegElts;
514 }
515 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
516
517 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
518 unsigned DstReg = 0;
519 bool DstIsDead = false;
520 if (TableEntry->IsLoad) {
521 DstIsDead = MI.getOperand(OpIdx).isDead();
522 DstReg = MI.getOperand(OpIdx++).getReg();
523 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
524 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
525 if (NumRegs > 1)
526 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
527 if (NumRegs > 2)
528 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
529 if (NumRegs > 3)
530 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
531 }
532
533 if (TableEntry->isUpdating)
534 MIB.addOperand(MI.getOperand(OpIdx++));
535
536 // Copy the addrmode6 operands.
537 MIB.addOperand(MI.getOperand(OpIdx++));
538 MIB.addOperand(MI.getOperand(OpIdx++));
539 // Copy the am6offset operand.
540 if (TableEntry->hasWritebackOperand)
541 MIB.addOperand(MI.getOperand(OpIdx++));
542
543 // Grab the super-register source.
544 MachineOperand MO = MI.getOperand(OpIdx++);
545 if (!TableEntry->IsLoad)
546 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
547
548 // Add the subregs as sources of the new instruction.
549 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
550 getKillRegState(MO.isKill()));
551 MIB.addReg(D0, SrcFlags);
552 if (NumRegs > 1)
553 MIB.addReg(D1, SrcFlags);
554 if (NumRegs > 2)
555 MIB.addReg(D2, SrcFlags);
556 if (NumRegs > 3)
557 MIB.addReg(D3, SrcFlags);
558
559 // Add the lane number operand.
560 MIB.addImm(Lane);
561 OpIdx += 1;
562
563 // Copy the predicate operands.
564 MIB.addOperand(MI.getOperand(OpIdx++));
565 MIB.addOperand(MI.getOperand(OpIdx++));
566
567 // Copy the super-register source to be an implicit source.
568 MO.setImplicit(true);
569 MIB.addOperand(MO);
570 if (TableEntry->IsLoad)
571 // Add an implicit def for the super-register.
572 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
573 TransferImpOps(MI, MIB, MIB);
574 // Transfer memoperands.
575 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
576 MI.eraseFromParent();
577}
578
579/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
580/// register operands to real instructions with D register operands.
581void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
582 unsigned Opc, bool IsExt) {
583 MachineInstr &MI = *MBBI;
584 MachineBasicBlock &MBB = *MI.getParent();
585
586 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
587 unsigned OpIdx = 0;
588
589 // Transfer the destination register operand.
590 MIB.addOperand(MI.getOperand(OpIdx++));
591 if (IsExt)
592 MIB.addOperand(MI.getOperand(OpIdx++));
593
594 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
595 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
596 unsigned D0, D1, D2, D3;
597 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
598 MIB.addReg(D0);
599
600 // Copy the other source register operand.
601 MIB.addOperand(MI.getOperand(OpIdx++));
602
603 // Copy the predicate operands.
604 MIB.addOperand(MI.getOperand(OpIdx++));
605 MIB.addOperand(MI.getOperand(OpIdx++));
606
607 if (SrcIsKill) // Add an implicit kill for the super-reg.
608 MIB->addRegisterKilled(SrcReg, TRI, true);
609 TransferImpOps(MI, MIB, MIB);
610 MI.eraseFromParent();
611}
612
613void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
614 MachineBasicBlock::iterator &MBBI) {
615 MachineInstr &MI = *MBBI;
616 unsigned Opcode = MI.getOpcode();
617 unsigned PredReg = 0;
618 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
619 unsigned DstReg = MI.getOperand(0).getReg();
620 bool DstIsDead = MI.getOperand(0).isDead();
621 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
622 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
623 MachineInstrBuilder LO16, HI16;
624
625 if (!STI->hasV6T2Ops() &&
626 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
627 // Expand into a movi + orr.
628 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
629 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
630 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
631 .addReg(DstReg);
632
633 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
634 unsigned ImmVal = (unsigned)MO.getImm();
635 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
636 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
637 LO16 = LO16.addImm(SOImmValV1);
638 HI16 = HI16.addImm(SOImmValV2);
639 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
640 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
641 LO16.addImm(Pred).addReg(PredReg).addReg(0);
642 HI16.addImm(Pred).addReg(PredReg).addReg(0);
643 TransferImpOps(MI, LO16, HI16);
644 MI.eraseFromParent();
645 return;
646 }
647
648 unsigned LO16Opc = 0;
649 unsigned HI16Opc = 0;
650 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
651 LO16Opc = ARM::t2MOVi16;
652 HI16Opc = ARM::t2MOVTi16;
653 } else {
654 LO16Opc = ARM::MOVi16;
655 HI16Opc = ARM::MOVTi16;
656 }
657
658 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
659 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
660 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
661 .addReg(DstReg);
662
663 if (MO.isImm()) {
664 unsigned Imm = MO.getImm();
665 unsigned Lo16 = Imm & 0xffff;
666 unsigned Hi16 = (Imm >> 16) & 0xffff;
667 LO16 = LO16.addImm(Lo16);
668 HI16 = HI16.addImm(Hi16);
669 } else {
670 const GlobalValue *GV = MO.getGlobal();
671 unsigned TF = MO.getTargetFlags();
672 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
673 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
674 }
675
676 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
677 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
678 LO16.addImm(Pred).addReg(PredReg);
679 HI16.addImm(Pred).addReg(PredReg);
680
681 TransferImpOps(MI, LO16, HI16);
682 MI.eraseFromParent();
683}
684
685bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
686 MachineBasicBlock::iterator MBBI) {
687 MachineInstr &MI = *MBBI;
688 unsigned Opcode = MI.getOpcode();
689 switch (Opcode) {
690 default:
691 return false;
692 case ARM::VMOVScc:
693 case ARM::VMOVDcc: {
694 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
695 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
696 MI.getOperand(1).getReg())
697 .addOperand(MI.getOperand(2))
698 .addImm(MI.getOperand(3).getImm()) // 'pred'
699 .addOperand(MI.getOperand(4));
700
701 MI.eraseFromParent();
702 return true;
703 }
704 case ARM::t2MOVCCr:
705 case ARM::MOVCCr: {
706 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
707 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
708 MI.getOperand(1).getReg())
709 .addOperand(MI.getOperand(2))
710 .addImm(MI.getOperand(3).getImm()) // 'pred'
711 .addOperand(MI.getOperand(4))
712 .addReg(0); // 's' bit
713
714 MI.eraseFromParent();
715 return true;
716 }
717 case ARM::MOVCCsi: {
718 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
719 (MI.getOperand(1).getReg()))
720 .addOperand(MI.getOperand(2))
721 .addImm(MI.getOperand(3).getImm())
722 .addImm(MI.getOperand(4).getImm()) // 'pred'
723 .addOperand(MI.getOperand(5))
724 .addReg(0); // 's' bit
725
726 MI.eraseFromParent();
727 return true;
728 }
729 case ARM::MOVCCsr: {
730 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
731 (MI.getOperand(1).getReg()))
732 .addOperand(MI.getOperand(2))
733 .addOperand(MI.getOperand(3))
734 .addImm(MI.getOperand(4).getImm())
735 .addImm(MI.getOperand(5).getImm()) // 'pred'
736 .addOperand(MI.getOperand(6))
737 .addReg(0); // 's' bit
738
739 MI.eraseFromParent();
740 return true;
741 }
742 case ARM::t2MOVCCi16:
743 case ARM::MOVCCi16: {
744 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
745 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
746 MI.getOperand(1).getReg())
747 .addImm(MI.getOperand(2).getImm())
748 .addImm(MI.getOperand(3).getImm()) // 'pred'
749 .addOperand(MI.getOperand(4));
750 MI.eraseFromParent();
751 return true;
752 }
753 case ARM::t2MOVCCi:
754 case ARM::MOVCCi: {
755 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
756 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
757 MI.getOperand(1).getReg())
758 .addImm(MI.getOperand(2).getImm())
759 .addImm(MI.getOperand(3).getImm()) // 'pred'
760 .addOperand(MI.getOperand(4))
761 .addReg(0); // 's' bit
762
763 MI.eraseFromParent();
764 return true;
765 }
766 case ARM::t2MVNCCi:
767 case ARM::MVNCCi: {
768 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
769 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
770 MI.getOperand(1).getReg())
771 .addImm(MI.getOperand(2).getImm())
772 .addImm(MI.getOperand(3).getImm()) // 'pred'
773 .addOperand(MI.getOperand(4))
774 .addReg(0); // 's' bit
775
776 MI.eraseFromParent();
777 return true;
778 }
779 case ARM::t2MOVCClsl:
780 case ARM::t2MOVCClsr:
781 case ARM::t2MOVCCasr:
782 case ARM::t2MOVCCror: {
783 unsigned NewOpc;
784 switch (Opcode) {
785 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
786 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
787 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
788 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
789 default: llvm_unreachable("unexpeced conditional move");
790 }
791 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
792 MI.getOperand(1).getReg())
793 .addOperand(MI.getOperand(2))
794 .addImm(MI.getOperand(3).getImm())
795 .addImm(MI.getOperand(4).getImm()) // 'pred'
796 .addOperand(MI.getOperand(5))
797 .addReg(0); // 's' bit
798 MI.eraseFromParent();
799 return true;
800 }
801 case ARM::Int_eh_sjlj_dispatchsetup: {
802 MachineFunction &MF = *MI.getParent()->getParent();
803 const ARMBaseInstrInfo *AII =
804 static_cast<const ARMBaseInstrInfo*>(TII);
805 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
806 // For functions using a base pointer, we rematerialize it (via the frame
807 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
808 // for us. Otherwise, expand to nothing.
809 if (RI.hasBasePointer(MF)) {
810 int32_t NumBytes = AFI->getFramePtrSpillOffset();
811 unsigned FramePtr = RI.getFrameRegister(MF);
812 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
813 "base pointer without frame pointer?");
814
815 if (AFI->isThumb2Function()) {
816 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
817 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
818 } else if (AFI->isThumbFunction()) {
819 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
820 FramePtr, -NumBytes, *TII, RI);
821 } else {
822 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
823 FramePtr, -NumBytes, ARMCC::AL, 0,
824 *TII);
825 }
826 // If there's dynamic realignment, adjust for it.
827 if (RI.needsStackRealignment(MF)) {
828 MachineFrameInfo *MFI = MF.getFrameInfo();
829 unsigned MaxAlign = MFI->getMaxAlignment();
830 assert (!AFI->isThumb1OnlyFunction());
831 // Emit bic r6, r6, MaxAlign
832 unsigned bicOpc = AFI->isThumbFunction() ?
833 ARM::t2BICri : ARM::BICri;
834 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
835 TII->get(bicOpc), ARM::R6)
836 .addReg(ARM::R6, RegState::Kill)
837 .addImm(MaxAlign-1)));
838 }
839
840 }
841 MI.eraseFromParent();
842 return true;
843 }
844
845 case ARM::MOVsrl_flag:
846 case ARM::MOVsra_flag: {
847 // These are just fancy MOVs instructions.
848 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
849 MI.getOperand(0).getReg())
850 .addOperand(MI.getOperand(1))
851 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
852 ARM_AM::lsr : ARM_AM::asr),
853 1)))
854 .addReg(ARM::CPSR, RegState::Define);
855 MI.eraseFromParent();
856 return true;
857 }
858 case ARM::RRX: {
859 // This encodes as "MOVs Rd, Rm, rrx
860 MachineInstrBuilder MIB =
861 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
862 MI.getOperand(0).getReg())
863 .addOperand(MI.getOperand(1))
864 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
865 .addReg(0);
866 TransferImpOps(MI, MIB, MIB);
867 MI.eraseFromParent();
868 return true;
869 }
870 case ARM::tTPsoft:
871 case ARM::TPsoft: {
872 MachineInstrBuilder MIB =
873 BuildMI(MBB, MBBI, MI.getDebugLoc(),
874 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
875 .addExternalSymbol("__aeabi_read_tp", 0);
876
877 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
878 TransferImpOps(MI, MIB, MIB);
879 MI.eraseFromParent();
880 return true;
881 }
882 case ARM::tLDRpci_pic:
883 case ARM::t2LDRpci_pic: {
884 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
885 ? ARM::tLDRpci : ARM::t2LDRpci;
886 unsigned DstReg = MI.getOperand(0).getReg();
887 bool DstIsDead = MI.getOperand(0).isDead();
888 MachineInstrBuilder MIB1 =
889 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
890 TII->get(NewLdOpc), DstReg)
891 .addOperand(MI.getOperand(1)));
892 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
893 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
894 TII->get(ARM::tPICADD))
895 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
896 .addReg(DstReg)
897 .addOperand(MI.getOperand(2));
898 TransferImpOps(MI, MIB1, MIB2);
899 MI.eraseFromParent();
900 return true;
901 }
902
903 case ARM::MOV_ga_dyn:
904 case ARM::MOV_ga_pcrel:
905 case ARM::MOV_ga_pcrel_ldr:
906 case ARM::t2MOV_ga_dyn:
907 case ARM::t2MOV_ga_pcrel: {
908 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
909 unsigned LabelId = AFI->createPICLabelUId();
910 unsigned DstReg = MI.getOperand(0).getReg();
911 bool DstIsDead = MI.getOperand(0).isDead();
912 const MachineOperand &MO1 = MI.getOperand(1);
913 const GlobalValue *GV = MO1.getGlobal();
914 unsigned TF = MO1.getTargetFlags();
915 bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode!=ARM::t2MOV_ga_dyn);
916 bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn);
917 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
918 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
919 unsigned LO16TF = isPIC
920 ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY;
921 unsigned HI16TF = isPIC
922 ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY;
923 unsigned PICAddOpc = isARM
924 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
925 : ARM::tPICADD;
926 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
927 TII->get(LO16Opc), DstReg)
928 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
929 .addImm(LabelId);
930 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
931 TII->get(HI16Opc), DstReg)
932 .addReg(DstReg)
933 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
934 .addImm(LabelId);
935 if (!isPIC) {
936 TransferImpOps(MI, MIB1, MIB2);
937 MI.eraseFromParent();
938 return true;
939 }
940
941 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
942 TII->get(PICAddOpc))
943 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
944 .addReg(DstReg).addImm(LabelId);
945 if (isARM) {
946 AddDefaultPred(MIB3);
947 if (Opcode == ARM::MOV_ga_pcrel_ldr)
948 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
949 }
950 TransferImpOps(MI, MIB1, MIB3);
951 MI.eraseFromParent();
952 return true;
953 }
954
955 case ARM::MOVi32imm:
956 case ARM::MOVCCi32imm:
957 case ARM::t2MOVi32imm:
958 case ARM::t2MOVCCi32imm:
959 ExpandMOV32BitImm(MBB, MBBI);
960 return true;
961
962 case ARM::SUBS_PC_LR: {
963 MachineInstrBuilder MIB =
964 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
965 .addReg(ARM::LR)
966 .addOperand(MI.getOperand(0))
967 .addOperand(MI.getOperand(1))
968 .addOperand(MI.getOperand(2))
969 .addReg(ARM::CPSR, RegState::Undef);
970 TransferImpOps(MI, MIB, MIB);
971 MI.eraseFromParent();
972 return true;
973 }
974 case ARM::VLDMQIA: {
975 unsigned NewOpc = ARM::VLDMDIA;
976 MachineInstrBuilder MIB =
977 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
978 unsigned OpIdx = 0;
979
980 // Grab the Q register destination.
981 bool DstIsDead = MI.getOperand(OpIdx).isDead();
982 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
983
984 // Copy the source register.
985 MIB.addOperand(MI.getOperand(OpIdx++));
986
987 // Copy the predicate operands.
988 MIB.addOperand(MI.getOperand(OpIdx++));
989 MIB.addOperand(MI.getOperand(OpIdx++));
990
991 // Add the destination operands (D subregs).
992 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
993 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
994 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
995 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
996
997 // Add an implicit def for the super-register.
998 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
999 TransferImpOps(MI, MIB, MIB);
1000 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1001 MI.eraseFromParent();
1002 return true;
1003 }
1004
1005 case ARM::VSTMQIA: {
1006 unsigned NewOpc = ARM::VSTMDIA;
1007 MachineInstrBuilder MIB =
1008 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1009 unsigned OpIdx = 0;
1010
1011 // Grab the Q register source.
1012 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1013 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1014
1015 // Copy the destination register.
1016 MIB.addOperand(MI.getOperand(OpIdx++));
1017
1018 // Copy the predicate operands.
1019 MIB.addOperand(MI.getOperand(OpIdx++));
1020 MIB.addOperand(MI.getOperand(OpIdx++));
1021
1022 // Add the source operands (D subregs).
1023 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1024 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1025 MIB.addReg(D0).addReg(D1);
1026
1027 if (SrcIsKill) // Add an implicit kill for the Q register.
1028 MIB->addRegisterKilled(SrcReg, TRI, true);
1029
1030 TransferImpOps(MI, MIB, MIB);
1031 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1032 MI.eraseFromParent();
1033 return true;
1034 }
1035 case ARM::VDUPfqf:
1036 case ARM::VDUPfdf:{
1037 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
1038 ARM::VDUPLN32d;
1039 MachineInstrBuilder MIB =
1040 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1041 unsigned OpIdx = 0;
1042 unsigned SrcReg = MI.getOperand(1).getReg();
1043 unsigned Lane = TRI->getEncodingValue(SrcReg) & 1;
1044 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
1045 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
1046 &ARM::DPR_VFP2RegClass);
1047 // The lane is [0,1] for the containing DReg superregister.
1048 // Copy the dst/src register operands.
1049 MIB.addOperand(MI.getOperand(OpIdx++));
1050 MIB.addReg(DReg);
1051 ++OpIdx;
1052 // Add the lane select operand.
1053 MIB.addImm(Lane);
1054 // Add the predicate operands.
1055 MIB.addOperand(MI.getOperand(OpIdx++));
1056 MIB.addOperand(MI.getOperand(OpIdx++));
1057
1058 TransferImpOps(MI, MIB, MIB);
1059 MI.eraseFromParent();
1060 return true;
1061 }
1062
1063 case ARM::VLD2q8Pseudo:
1064 case ARM::VLD2q16Pseudo:
1065 case ARM::VLD2q32Pseudo:
1066 case ARM::VLD2q8PseudoWB_fixed:
1067 case ARM::VLD2q16PseudoWB_fixed:
1068 case ARM::VLD2q32PseudoWB_fixed:
1069 case ARM::VLD2q8PseudoWB_register:
1070 case ARM::VLD2q16PseudoWB_register:
1071 case ARM::VLD2q32PseudoWB_register:
1072 case ARM::VLD3d8Pseudo:
1073 case ARM::VLD3d16Pseudo:
1074 case ARM::VLD3d32Pseudo:
1075 case ARM::VLD1d64TPseudo:
1076 case ARM::VLD1d64TPseudoWB_fixed:
1077 case ARM::VLD3d8Pseudo_UPD:
1078 case ARM::VLD3d16Pseudo_UPD:
1079 case ARM::VLD3d32Pseudo_UPD:
1080 case ARM::VLD3q8Pseudo_UPD:
1081 case ARM::VLD3q16Pseudo_UPD:
1082 case ARM::VLD3q32Pseudo_UPD:
1083 case ARM::VLD3q8oddPseudo:
1084 case ARM::VLD3q16oddPseudo:
1085 case ARM::VLD3q32oddPseudo:
1086 case ARM::VLD3q8oddPseudo_UPD:
1087 case ARM::VLD3q16oddPseudo_UPD:
1088 case ARM::VLD3q32oddPseudo_UPD:
1089 case ARM::VLD4d8Pseudo:
1090 case ARM::VLD4d16Pseudo:
1091 case ARM::VLD4d32Pseudo:
1092 case ARM::VLD1d64QPseudo:
1093 case ARM::VLD1d64QPseudoWB_fixed:
1094 case ARM::VLD4d8Pseudo_UPD:
1095 case ARM::VLD4d16Pseudo_UPD:
1096 case ARM::VLD4d32Pseudo_UPD:
1097 case ARM::VLD4q8Pseudo_UPD:
1098 case ARM::VLD4q16Pseudo_UPD:
1099 case ARM::VLD4q32Pseudo_UPD:
1100 case ARM::VLD4q8oddPseudo:
1101 case ARM::VLD4q16oddPseudo:
1102 case ARM::VLD4q32oddPseudo:
1103 case ARM::VLD4q8oddPseudo_UPD:
1104 case ARM::VLD4q16oddPseudo_UPD:
1105 case ARM::VLD4q32oddPseudo_UPD:
1106 case ARM::VLD3DUPd8Pseudo:
1107 case ARM::VLD3DUPd16Pseudo:
1108 case ARM::VLD3DUPd32Pseudo:
1109 case ARM::VLD3DUPd8Pseudo_UPD:
1110 case ARM::VLD3DUPd16Pseudo_UPD:
1111 case ARM::VLD3DUPd32Pseudo_UPD:
1112 case ARM::VLD4DUPd8Pseudo:
1113 case ARM::VLD4DUPd16Pseudo:
1114 case ARM::VLD4DUPd32Pseudo:
1115 case ARM::VLD4DUPd8Pseudo_UPD:
1116 case ARM::VLD4DUPd16Pseudo_UPD:
1117 case ARM::VLD4DUPd32Pseudo_UPD:
1118 ExpandVLD(MBBI);
1119 return true;
1120
1121 case ARM::VST2q8Pseudo:
1122 case ARM::VST2q16Pseudo:
1123 case ARM::VST2q32Pseudo:
1124 case ARM::VST2q8PseudoWB_fixed:
1125 case ARM::VST2q16PseudoWB_fixed:
1126 case ARM::VST2q32PseudoWB_fixed:
1127 case ARM::VST2q8PseudoWB_register:
1128 case ARM::VST2q16PseudoWB_register:
1129 case ARM::VST2q32PseudoWB_register:
1130 case ARM::VST3d8Pseudo:
1131 case ARM::VST3d16Pseudo:
1132 case ARM::VST3d32Pseudo:
1133 case ARM::VST1d64TPseudo:
1134 case ARM::VST3d8Pseudo_UPD:
1135 case ARM::VST3d16Pseudo_UPD:
1136 case ARM::VST3d32Pseudo_UPD:
1137 case ARM::VST1d64TPseudoWB_fixed:
1138 case ARM::VST1d64TPseudoWB_register:
1139 case ARM::VST3q8Pseudo_UPD:
1140 case ARM::VST3q16Pseudo_UPD:
1141 case ARM::VST3q32Pseudo_UPD:
1142 case ARM::VST3q8oddPseudo:
1143 case ARM::VST3q16oddPseudo:
1144 case ARM::VST3q32oddPseudo:
1145 case ARM::VST3q8oddPseudo_UPD:
1146 case ARM::VST3q16oddPseudo_UPD:
1147 case ARM::VST3q32oddPseudo_UPD:
1148 case ARM::VST4d8Pseudo:
1149 case ARM::VST4d16Pseudo:
1150 case ARM::VST4d32Pseudo:
1151 case ARM::VST1d64QPseudo:
1152 case ARM::VST4d8Pseudo_UPD:
1153 case ARM::VST4d16Pseudo_UPD:
1154 case ARM::VST4d32Pseudo_UPD:
1155 case ARM::VST1d64QPseudoWB_fixed:
1156 case ARM::VST1d64QPseudoWB_register:
1157 case ARM::VST4q8Pseudo_UPD:
1158 case ARM::VST4q16Pseudo_UPD:
1159 case ARM::VST4q32Pseudo_UPD:
1160 case ARM::VST4q8oddPseudo:
1161 case ARM::VST4q16oddPseudo:
1162 case ARM::VST4q32oddPseudo:
1163 case ARM::VST4q8oddPseudo_UPD:
1164 case ARM::VST4q16oddPseudo_UPD:
1165 case ARM::VST4q32oddPseudo_UPD:
1166 ExpandVST(MBBI);
1167 return true;
1168
1169 case ARM::VLD1LNq8Pseudo:
1170 case ARM::VLD1LNq16Pseudo:
1171 case ARM::VLD1LNq32Pseudo:
1172 case ARM::VLD1LNq8Pseudo_UPD:
1173 case ARM::VLD1LNq16Pseudo_UPD:
1174 case ARM::VLD1LNq32Pseudo_UPD:
1175 case ARM::VLD2LNd8Pseudo:
1176 case ARM::VLD2LNd16Pseudo:
1177 case ARM::VLD2LNd32Pseudo:
1178 case ARM::VLD2LNq16Pseudo:
1179 case ARM::VLD2LNq32Pseudo:
1180 case ARM::VLD2LNd8Pseudo_UPD:
1181 case ARM::VLD2LNd16Pseudo_UPD:
1182 case ARM::VLD2LNd32Pseudo_UPD:
1183 case ARM::VLD2LNq16Pseudo_UPD:
1184 case ARM::VLD2LNq32Pseudo_UPD:
1185 case ARM::VLD3LNd8Pseudo:
1186 case ARM::VLD3LNd16Pseudo:
1187 case ARM::VLD3LNd32Pseudo:
1188 case ARM::VLD3LNq16Pseudo:
1189 case ARM::VLD3LNq32Pseudo:
1190 case ARM::VLD3LNd8Pseudo_UPD:
1191 case ARM::VLD3LNd16Pseudo_UPD:
1192 case ARM::VLD3LNd32Pseudo_UPD:
1193 case ARM::VLD3LNq16Pseudo_UPD:
1194 case ARM::VLD3LNq32Pseudo_UPD:
1195 case ARM::VLD4LNd8Pseudo:
1196 case ARM::VLD4LNd16Pseudo:
1197 case ARM::VLD4LNd32Pseudo:
1198 case ARM::VLD4LNq16Pseudo:
1199 case ARM::VLD4LNq32Pseudo:
1200 case ARM::VLD4LNd8Pseudo_UPD:
1201 case ARM::VLD4LNd16Pseudo_UPD:
1202 case ARM::VLD4LNd32Pseudo_UPD:
1203 case ARM::VLD4LNq16Pseudo_UPD:
1204 case ARM::VLD4LNq32Pseudo_UPD:
1205 case ARM::VST1LNq8Pseudo:
1206 case ARM::VST1LNq16Pseudo:
1207 case ARM::VST1LNq32Pseudo:
1208 case ARM::VST1LNq8Pseudo_UPD:
1209 case ARM::VST1LNq16Pseudo_UPD:
1210 case ARM::VST1LNq32Pseudo_UPD:
1211 case ARM::VST2LNd8Pseudo:
1212 case ARM::VST2LNd16Pseudo:
1213 case ARM::VST2LNd32Pseudo:
1214 case ARM::VST2LNq16Pseudo:
1215 case ARM::VST2LNq32Pseudo:
1216 case ARM::VST2LNd8Pseudo_UPD:
1217 case ARM::VST2LNd16Pseudo_UPD:
1218 case ARM::VST2LNd32Pseudo_UPD:
1219 case ARM::VST2LNq16Pseudo_UPD:
1220 case ARM::VST2LNq32Pseudo_UPD:
1221 case ARM::VST3LNd8Pseudo:
1222 case ARM::VST3LNd16Pseudo:
1223 case ARM::VST3LNd32Pseudo:
1224 case ARM::VST3LNq16Pseudo:
1225 case ARM::VST3LNq32Pseudo:
1226 case ARM::VST3LNd8Pseudo_UPD:
1227 case ARM::VST3LNd16Pseudo_UPD:
1228 case ARM::VST3LNd32Pseudo_UPD:
1229 case ARM::VST3LNq16Pseudo_UPD:
1230 case ARM::VST3LNq32Pseudo_UPD:
1231 case ARM::VST4LNd8Pseudo:
1232 case ARM::VST4LNd16Pseudo:
1233 case ARM::VST4LNd32Pseudo:
1234 case ARM::VST4LNq16Pseudo:
1235 case ARM::VST4LNq32Pseudo:
1236 case ARM::VST4LNd8Pseudo_UPD:
1237 case ARM::VST4LNd16Pseudo_UPD:
1238 case ARM::VST4LNd32Pseudo_UPD:
1239 case ARM::VST4LNq16Pseudo_UPD:
1240 case ARM::VST4LNq32Pseudo_UPD:
1241 ExpandLaneOp(MBBI);
1242 return true;
1243
1244 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1245 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1246 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1247 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1248 }
1249}
1250
1251bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1252 bool Modified = false;
1253
1254 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1255 while (MBBI != E) {
1256 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
1257 Modified |= ExpandMI(MBB, MBBI);
1258 MBBI = NMBBI;
1259 }
1260
1261 return Modified;
1262}
1263
1264bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1265 const TargetMachine &TM = MF.getTarget();
1266 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
1267 TRI = TM.getRegisterInfo();
1268 STI = &TM.getSubtarget<ARMSubtarget>();
1269 AFI = MF.getInfo<ARMFunctionInfo>();
1270
1271 bool Modified = false;
1272 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1273 ++MFI)
1274 Modified |= ExpandMBB(*MFI);
1275 if (VerifyARMPseudo)
1276 MF.verify(this, "After expanding ARM pseudo instructions.");
1277 return Modified;
1278}
1279
1280/// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1281/// expansion pass.
1282FunctionPass *llvm::createARMExpandPseudoPass() {
1283 return new ARMExpandPseudo();
1284}