Deleted Added
sdiff udiff text old ( 256281 ) new ( 263508 )
full compact
MCSchedule.h (256281) MCSchedule.h (263508)
1//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 16 unchanged lines hidden (view full) ---

25/// Define a kind of processor resource that will be modeled by the scheduler.
26struct MCProcResourceDesc {
27#ifndef NDEBUG
28 const char *Name;
29#endif
30 unsigned NumUnits; // Number of resource of this kind
31 unsigned SuperIdx; // Index of the resources kind that contains this kind.
32
1//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 16 unchanged lines hidden (view full) ---

25/// Define a kind of processor resource that will be modeled by the scheduler.
26struct MCProcResourceDesc {
27#ifndef NDEBUG
28 const char *Name;
29#endif
30 unsigned NumUnits; // Number of resource of this kind
31 unsigned SuperIdx; // Index of the resources kind that contains this kind.
32
33 // Buffered resources may be consumed at some indeterminate cycle after
34 // dispatch (e.g. for instructions that may issue out-of-order). Unbuffered
35 // resources always consume their resource some fixed number of cycles after
36 // dispatch (e.g. for instruction interlocking that may stall the pipeline).
37 bool IsBuffered;
33 // Number of resources that may be buffered.
34 //
35 // Buffered resources (BufferSize > 0 || BufferSize == -1) may be consumed at
36 // some indeterminate cycle after dispatch (e.g. for instructions that may
37 // issue out-of-order). Unbuffered resources (BufferSize == 0) always consume
38 // their resource some fixed number of cycles after dispatch (e.g. for
39 // instruction interlocking that may stall the pipeline).
40 int BufferSize;
38
39 bool operator==(const MCProcResourceDesc &Other) const {
40 return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
41
42 bool operator==(const MCProcResourceDesc &Other) const {
43 return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
41 && IsBuffered == Other.IsBuffered;
44 && BufferSize == Other.BufferSize;
42 }
43};
44
45/// Identify one of the processor resource kinds consumed by a particular
46/// scheduling class for the specified number of cycles.
47struct MCWriteProcResEntry {
48 unsigned ProcResourceIdx;
49 unsigned Cycles;

--- 66 unchanged lines hidden (view full) ---

116};
117
118/// Machine model for scheduling, bundling, and heuristics.
119///
120/// The machine model directly provides basic information about the
121/// microarchitecture to the scheduler in the form of properties. It also
122/// optionally refers to scheduler resource tables and itinerary
123/// tables. Scheduler resource tables model the latency and cost for each
45 }
46};
47
48/// Identify one of the processor resource kinds consumed by a particular
49/// scheduling class for the specified number of cycles.
50struct MCWriteProcResEntry {
51 unsigned ProcResourceIdx;
52 unsigned Cycles;

--- 66 unchanged lines hidden (view full) ---

119};
120
121/// Machine model for scheduling, bundling, and heuristics.
122///
123/// The machine model directly provides basic information about the
124/// microarchitecture to the scheduler in the form of properties. It also
125/// optionally refers to scheduler resource tables and itinerary
126/// tables. Scheduler resource tables model the latency and cost for each
124/// instruction type. Itinerary tables are an independant mechanism that
127/// instruction type. Itinerary tables are an independent mechanism that
125/// provides a detailed reservation table describing each cycle of instruction
126/// execution. Subtargets may define any or all of the above categories of data
127/// depending on the type of CPU and selected scheduler.
128class MCSchedModel {
129public:
130 static MCSchedModel DefaultSchedModel; // For unknown processors.
131
132 // IssueWidth is the maximum number of instructions that may be scheduled in
133 // the same per-cycle group.
134 unsigned IssueWidth;
135 static const unsigned DefaultIssueWidth = 1;
136
128/// provides a detailed reservation table describing each cycle of instruction
129/// execution. Subtargets may define any or all of the above categories of data
130/// depending on the type of CPU and selected scheduler.
131class MCSchedModel {
132public:
133 static MCSchedModel DefaultSchedModel; // For unknown processors.
134
135 // IssueWidth is the maximum number of instructions that may be scheduled in
136 // the same per-cycle group.
137 unsigned IssueWidth;
138 static const unsigned DefaultIssueWidth = 1;
139
137 // MinLatency is the minimum latency between a register write
138 // followed by a data dependent read. This determines which
139 // instructions may be scheduled in the same per-cycle group. This
140 // is distinct from *expected* latency, which determines the likely
141 // critical path but does not guarantee a pipeline
142 // hazard. MinLatency can always be overridden by the number of
143 // InstrStage cycles.
140 // MicroOpBufferSize is the number of micro-ops that the processor may buffer
141 // for out-of-order execution.
144 //
142 //
145 // (-1) Standard in-order processor.
146 // Use InstrItinerary OperandCycles as MinLatency.
147 // If no OperandCycles exist, then use the cycle of the last InstrStage.
143 // "0" means operations that are not ready in this cycle are not considered
144 // for scheduling (they go in the pending queue). Latency is paramount. This
145 // may be more efficient if many instructions are pending in a schedule.
148 //
146 //
149 // (0) Out-of-order processor, or in-order with bundled dependencies.
150 // RAW dependencies may be dispatched in the same cycle.
151 // Optional InstrItinerary OperandCycles provides expected latency.
147 // "1" means all instructions are considered for scheduling regardless of
148 // whether they are ready in this cycle. Latency still causes issue stalls,
149 // but we balance those stalls against other heuristics.
152 //
150 //
153 // (>0) In-order processor with variable latencies.
154 // Use the greater of this value or the cycle of the last InstrStage.
155 // Optional InstrItinerary OperandCycles provides expected latency.
156 // TODO: can't yet specify both min and expected latency per operand.
157 int MinLatency;
158 static const int DefaultMinLatency = -1;
151 // "> 1" means the processor is out-of-order. This is a machine independent
152 // estimate of highly machine specific characteristics such are the register
153 // renaming pool and reorder buffer.
154 unsigned MicroOpBufferSize;
155 static const unsigned DefaultMicroOpBufferSize = 0;
159
160 // LoadLatency is the expected latency of load instructions.
161 //
162 // If MinLatency >= 0, this may be overriden for individual load opcodes by
163 // InstrItinerary OperandCycles.
164 unsigned LoadLatency;
165 static const unsigned DefaultLoadLatency = 4;
166
167 // HighLatency is the expected latency of "very high latency" operations.
168 // See TargetInstrInfo::isHighLatencyDef().
169 // By default, this is set to an arbitrarily high number of cycles
170 // likely to have some impact on scheduling heuristics.
171 // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
172 unsigned HighLatency;
173 static const unsigned DefaultHighLatency = 10;
174
156
157 // LoadLatency is the expected latency of load instructions.
158 //
159 // If MinLatency >= 0, this may be overriden for individual load opcodes by
160 // InstrItinerary OperandCycles.
161 unsigned LoadLatency;
162 static const unsigned DefaultLoadLatency = 4;
163
164 // HighLatency is the expected latency of "very high latency" operations.
165 // See TargetInstrInfo::isHighLatencyDef().
166 // By default, this is set to an arbitrarily high number of cycles
167 // likely to have some impact on scheduling heuristics.
168 // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
169 unsigned HighLatency;
170 static const unsigned DefaultHighLatency = 10;
171
175 // ILPWindow is the number of cycles that the scheduler effectively ignores
176 // before attempting to hide latency. This should be zero for in-order cpus to
177 // always hide expected latency. For out-of-order cpus, it may be tweaked as
178 // desired to roughly approximate instruction buffers. The actual threshold is
179 // not very important for an OOO processor, as long as it isn't too high. A
180 // nonzero value helps avoid rescheduling to hide latency when its is fairly
181 // obviously useless and makes register pressure heuristics more effective.
182 unsigned ILPWindow;
183 static const unsigned DefaultILPWindow = 0;
184
185 // MispredictPenalty is the typical number of extra cycles the processor
186 // takes to recover from a branch misprediction.
187 unsigned MispredictPenalty;
188 static const unsigned DefaultMispredictPenalty = 10;
189
172 // MispredictPenalty is the typical number of extra cycles the processor
173 // takes to recover from a branch misprediction.
174 unsigned MispredictPenalty;
175 static const unsigned DefaultMispredictPenalty = 10;
176
177 bool CompleteModel;
178
190private:
191 unsigned ProcID;
192 const MCProcResourceDesc *ProcResourceTable;
193 const MCSchedClassDesc *SchedClassTable;
194 unsigned NumProcResourceKinds;
195 unsigned NumSchedClasses;
196 // Instruction itinerary tables used by InstrItineraryData.
197 friend class InstrItineraryData;
198 const InstrItinerary *InstrItineraries;
199
200public:
201 // Default's must be specified as static const literals so that tablegenerated
202 // target code can use it in static initializers. The defaults need to be
203 // initialized in this default ctor because some clients directly instantiate
204 // MCSchedModel instead of using a generated itinerary.
205 MCSchedModel(): IssueWidth(DefaultIssueWidth),
179private:
180 unsigned ProcID;
181 const MCProcResourceDesc *ProcResourceTable;
182 const MCSchedClassDesc *SchedClassTable;
183 unsigned NumProcResourceKinds;
184 unsigned NumSchedClasses;
185 // Instruction itinerary tables used by InstrItineraryData.
186 friend class InstrItineraryData;
187 const InstrItinerary *InstrItineraries;
188
189public:
190 // Default's must be specified as static const literals so that tablegenerated
191 // target code can use it in static initializers. The defaults need to be
192 // initialized in this default ctor because some clients directly instantiate
193 // MCSchedModel instead of using a generated itinerary.
194 MCSchedModel(): IssueWidth(DefaultIssueWidth),
206 MinLatency(DefaultMinLatency),
195 MicroOpBufferSize(DefaultMicroOpBufferSize),
207 LoadLatency(DefaultLoadLatency),
208 HighLatency(DefaultHighLatency),
196 LoadLatency(DefaultLoadLatency),
197 HighLatency(DefaultHighLatency),
209 ILPWindow(DefaultILPWindow),
210 MispredictPenalty(DefaultMispredictPenalty),
198 MispredictPenalty(DefaultMispredictPenalty),
199 CompleteModel(true),
211 ProcID(0), ProcResourceTable(0), SchedClassTable(0),
212 NumProcResourceKinds(0), NumSchedClasses(0),
213 InstrItineraries(0) {
214 (void)NumProcResourceKinds;
215 (void)NumSchedClasses;
216 }
217
218 // Table-gen driven ctor.
200 ProcID(0), ProcResourceTable(0), SchedClassTable(0),
201 NumProcResourceKinds(0), NumSchedClasses(0),
202 InstrItineraries(0) {
203 (void)NumProcResourceKinds;
204 (void)NumSchedClasses;
205 }
206
207 // Table-gen driven ctor.
219 MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned ilp,
220 unsigned mp, unsigned pi, const MCProcResourceDesc *pr,
208 MCSchedModel(unsigned iw, int mbs, unsigned ll, unsigned hl,
209 unsigned mp, bool cm, unsigned pi, const MCProcResourceDesc *pr,
221 const MCSchedClassDesc *sc, unsigned npr, unsigned nsc,
222 const InstrItinerary *ii):
210 const MCSchedClassDesc *sc, unsigned npr, unsigned nsc,
211 const InstrItinerary *ii):
223 IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
224 ILPWindow(ilp), MispredictPenalty(mp), ProcID(pi), ProcResourceTable(pr),
225 SchedClassTable(sc), NumProcResourceKinds(npr), NumSchedClasses(nsc),
226 InstrItineraries(ii) {}
212 IssueWidth(iw), MicroOpBufferSize(mbs), LoadLatency(ll), HighLatency(hl),
213 MispredictPenalty(mp), CompleteModel(cm), ProcID(pi),
214 ProcResourceTable(pr), SchedClassTable(sc), NumProcResourceKinds(npr),
215 NumSchedClasses(nsc), InstrItineraries(ii) {}
227
228 unsigned getProcessorID() const { return ProcID; }
229
230 /// Does this machine model include instruction-level scheduling.
231 bool hasInstrSchedModel() const { return SchedClassTable; }
232
216
217 unsigned getProcessorID() const { return ProcID; }
218
219 /// Does this machine model include instruction-level scheduling.
220 bool hasInstrSchedModel() const { return SchedClassTable; }
221
222 /// Return true if this machine model data for all instructions with a
223 /// scheduling class (itinerary class or SchedRW list).
224 bool isComplete() const { return CompleteModel; }
225
233 unsigned getNumProcResourceKinds() const {
234 return NumProcResourceKinds;
235 }
236
237 const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
238 assert(hasInstrSchedModel() && "No scheduling machine model");
239
240 assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");

--- 14 unchanged lines hidden --- 		226 unsigned getNumProcResourceKinds() const {
227 return NumProcResourceKinds;
228 }
229
230 const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
231 assert(hasInstrSchedModel() && "No scheduling machine model");
232
233 assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");

--- 14 unchanged lines hidden ---