| instr.h (92050) | instr.h (96422) |
|---|---|
| 1/* 2 * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 3 * Copyright (c) 1995 Paul Kranenburg 4 * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 17 unchanged lines hidden (view full) --- 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 33 * | 1/* 2 * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 3 * Copyright (c) 1995 Paul Kranenburg 4 * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 17 unchanged lines hidden (view full) --- 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 33 * |
| 34 * $FreeBSD: head/sys/sparc64/include/instr.h 92050 2002-03-11 03:03:35Z tmm $ | 34 * $FreeBSD: head/sys/sparc64/include/instr.h 96422 2002-05-11 21:20:05Z jake $ |
| 35 */ 36 37#ifndef _MACHINE_INSTR_H_ 38#define _MACHINE_INSTR_H_ 39 40/* 41 * Definitions for all instruction formats 42 */ --- 411 unchanged lines hidden (view full) --- 454#define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS) 455#define INSFP2_FMOV_RCMUL 0x20 456#define INSFP2_FMOV_RCOFFS 0x04 457/* Use the IRCOND_* constants for rc. Operand types: s, d, q */ 458#define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS) 459#define INSFP2_FCMP 0x050 /* s, d, q */ 460#define INSFP2_FCMPE 0x054 /* s, d, q */ 461 | 35 */ 36 37#ifndef _MACHINE_INSTR_H_ 38#define _MACHINE_INSTR_H_ 39 40/* 41 * Definitions for all instruction formats 42 */ --- 411 unchanged lines hidden (view full) --- 454#define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS) 455#define INSFP2_FMOV_RCMUL 0x20 456#define INSFP2_FMOV_RCOFFS 0x04 457/* Use the IRCOND_* constants for rc. Operand types: s, d, q */ 458#define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS) 459#define INSFP2_FCMP 0x050 /* s, d, q */ 460#define INSFP2_FCMPE 0x054 /* s, d, q */ 461 |
| 462/* Decode 5-bit register field into 6-bit number (for doubles and quads). */ 463#define INSFPdq_RN(rn) (((rn) & ~1) | (((rn) & 1) << 5)) 464 |
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| 462/* IMPLDEP1 for Sun UltraSparc */ 463#define IIDP1_EDGE8 0x00 464#define IIDP1_EDGE8L 0x02 465#define IIDP1_EDGE16 0x04 466#define IIDP1_EDGE16L 0x06 467#define IIDP1_EDGE32 0x08 468#define IIDP1_EDGE32L 0x0a 469#define IIDP1_ARRAY8 0x10 --- 136 unchanged lines hidden --- | 465/* IMPLDEP1 for Sun UltraSparc */ 466#define IIDP1_EDGE8 0x00 467#define IIDP1_EDGE8L 0x02 468#define IIDP1_EDGE16 0x04 469#define IIDP1_EDGE16L 0x06 470#define IIDP1_EDGE32 0x08 471#define IIDP1_EDGE32L 0x0a 472#define IIDP1_ARRAY8 0x10 --- 136 unchanged lines hidden --- |