| instr.h (86146) | instr.h (88663) |
|---|---|
| 1/* 2 * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 3 * Copyright (c) 1995 Paul Kranenburg 4 * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 17 unchanged lines hidden (view full) --- 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 33 * | 1/* 2 * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 3 * Copyright (c) 1995 Paul Kranenburg 4 * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 17 unchanged lines hidden (view full) --- 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 33 * |
| 34 * $FreeBSD: head/sys/sparc64/include/instr.h 86146 2001-11-06 20:13:44Z tmm $ | 34 * $FreeBSD: head/sys/sparc64/include/instr.h 88663 2001-12-29 08:55:56Z jake $ |
| 35 */ 36 37#ifndef _MACHINE_INSTR_H_ 38#define _MACHINE_INSTR_H_ 39 40/* 41 * Definitions for all instruction formats 42 */ --- 89 unchanged lines hidden (view full) --- 132#define IF_F4_RS2_BITS IF_F3_RS2_BITS 133#define IF_F4_SW_TRAP_SHIFT 0 134#define IF_F4_SW_TRAP_BITS 7 135 136/* 137 * Macros to decode instructions 138 */ 139/* Extract a field */ | 35 */ 36 37#ifndef _MACHINE_INSTR_H_ 38#define _MACHINE_INSTR_H_ 39 40/* 41 * Definitions for all instruction formats 42 */ --- 89 unchanged lines hidden (view full) --- 132#define IF_F4_RS2_BITS IF_F3_RS2_BITS 133#define IF_F4_SW_TRAP_SHIFT 0 134#define IF_F4_SW_TRAP_BITS 7 135 136/* 137 * Macros to decode instructions 138 */ 139/* Extract a field */ |
| 140#define IF_EXTRACT(x, s, w) (((x) >> (s)) & ((1 << (w)) - 1)) | 140#define IF_MASK(s, w) (((1 << (w)) - 1) << (s)) 141#define IF_EXTRACT(x, s, w) (((x) & IF_MASK((s), (w))) >> (s)) |
| 141#define IF_DECODE(x, f) \ 142 IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 143 144/* Sign-extend a field of width W */ 145#define IF_SEXT(x, w) \ 146 (((x) & (1 << ((w) - 1))) != 0 ? (-1L - ((x) ^ ((1 << (w)) - 1))) : (x)) 147 148#if 0 --- 258 unchanged lines hidden (view full) --- 407/* undefined 0x38 - 0x3b */ 408#define INS3_CASA 0x39 409#define INS3_PREFETCHA 0x3a 410#define INS3_CASXA 0x3b 411 412/* 413 * OPF values (floating point instructions, IMPLDEP) 414 */ | 142#define IF_DECODE(x, f) \ 143 IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 144 145/* Sign-extend a field of width W */ 146#define IF_SEXT(x, w) \ 147 (((x) & (1 << ((w) - 1))) != 0 ? (-1L - ((x) ^ ((1 << (w)) - 1))) : (x)) 148 149#if 0 --- 258 unchanged lines hidden (view full) --- 408/* undefined 0x38 - 0x3b */ 409#define INS3_CASA 0x39 410#define INS3_PREFETCHA 0x3a 411#define INS3_CASXA 0x3b 412 413/* 414 * OPF values (floating point instructions, IMPLDEP) 415 */ |
| 415/* FPop1 */ 416#define INSFP1_FMOVs 0x001 417#define INSFP1_FMOVd 0x002 418#define INSFP1_FMOVq 0x003 419#define INSFP1_FNEGs 0x005 420#define INSFP1_FNEGd 0x006 421#define INSFP1_FNEGq 0x007 422#define INSFP1_FABSs 0x009 423#define INSFP1_FABSd 0x00a 424#define INSFP1_FABSq 0x00b 425#define INSFP1_FSQRTs 0x029 426#define INSFP1_FSQRTd 0x02a 427#define INSFP1_FSQRTq 0x02b 428#define INSFP1_FADDs 0x041 429#define INSFP1_FADDd 0x042 430#define INSFP1_FADDq 0x043 431#define INSFP1_FSUBs 0x045 432#define INSFP1_FSUBd 0x046 433#define INSFP1_FSUBq 0x047 434#define INSFP1_FMULs 0x049 435#define INSFP1_FMULd 0x04a 436#define INSFP1_FMULq 0x04b 437#define INSFP1_FDIVs 0x04d 438#define INSFP1_FDIVd 0x04e 439#define INSFP1_FDIVq 0x04f 440#define INSFP1_FsMULd 0x069 441#define INSFP1_FdMULq 0x06e 442#define INSFP1_FsTOx 0x081 443#define INSFP1_FdTOx 0x082 444#define INSFP1_FqTOx 0x083 445#define INSFP1_FxTOs 0x084 446#define INSFP1_FxTOd 0x088 447#define INSFP1_FxTOq 0x08c 448#define INSFP1_FiTOs 0x0c4 449#define INSFP1_FdTOs 0x0c6 450#define INSFP1_FqTOs 0x0c7 451#define INSFP1_FiTOd 0x0c8 452#define INSFP1_FsTOd 0x0c9 453#define INSFP1_FqTOd 0x0cb 454#define INSFP1_FiTOq 0x0cc 455#define INSFP1_FsTOq 0x0cd 456#define INSFP1_FdTOq 0x0ce | 416/* 417 * These values are or'ed to the FPop values to get the instructions. 418 * They describe the operand type(s). 419 */ 420#define INSFP_i 0x000 /* 32-bit int */ 421#define INSFP_s 0x001 /* 32-bit single */ 422#define INSFP_d 0x002 /* 64-bit double */ 423#define INSFP_q 0x003 /* 128-bit quad */ 424/* FPop1. The comments give the types for which this instruction is defined. */ 425#define INSFP1_FMOV 0x000 /* s, d, q */ 426#define INSFP1_FNEG 0x004 /* s, d, q */ 427#define INSFP1_FABS 0x008 /* s, d, q */ 428#define INSFP1_FSQRT 0x028 /* s, d, q */ 429#define INSFP1_FADD 0x040 /* s, d, q */ 430#define INSFP1_FSUB 0x044 /* s, d, q */ 431#define INSFP1_FMUL 0x048 /* s, d, q */ 432#define INSFP1_FDIV 0x04c /* s, d, q */ 433#define INSFP1_FsMULd 0x068 /* s */ 434#define INSFP1_FdMULq 0x06c /* d */ 435#define INSFP1_FTOx 0x080 /* s, d, q */ 436#define INSFP1_FxTOs 0x084 /* special: i only */ 437#define INSFP1_FxTOd 0x088 /* special: i only */ 438#define INSFP1_FxTOq 0x08c /* special: i only */ 439#define INSFP1_FTOs 0x0c4 /* i, d, q */ 440#define INSFP1_FTOd 0x0c8 /* i, s, q */ 441#define INSFP1_FTOq 0x0cc /* i, s, d */ 442#define INSFP1_FTOi 0x0d0 /* i, s, d */ |
| 457 458/* FPop2 */ 459#define INSFP2_FMOV_CCMUL 0x40 | 443 444/* FPop2 */ 445#define INSFP2_FMOV_CCMUL 0x40 |
| 460/* use the IFCC_* constants for cc */ 461#define INSFP2_FMOV_CC(i, cc) (i + (cc) * INSFP2_FMOV_CCMUL) 462#define INSFP2_FMOVs(cc) INSFP2_FMOV_CC(0x01, (cc)) 463#define INSFP2_FMOVd(cc) INSFP2_FMOV_CC(0x02, (cc)) 464#define INSFP2_FMOVq(cc) INSFP2_FMOV_CC(0x03, (cc)) 465 466/* use the IRCOND_* constants for rc */ | 446#define INSFP2_FMOV_CCOFFS 0x00 447/* Use the IFCC_* constants for cc. Operand types: s, d, q */ 448#define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS) |
| 467#define INSFP2_FMOV_RCMUL 0x20 | 449#define INSFP2_FMOV_RCMUL 0x20 |
| 468#define INSFP2_FMOV_RC(i, rc) (i + (rc) * INSFP2_FMOV_RCMUL) 469#define INSFP2_FMOVRsZ(rc) INSFP2_FMOV_RC(0x05, (rc)) 470#define INSFP2_FMOVRdZ(rc) INSFP2_FMOV_RC(0x06, (rc)) 471#define INSFP2_FMOVRqZ(rc) INSFP2_FMOV_RC(0x07, (rc)) 472#define INSFP2_FCMPs 0x051 473#define INSFP2_FCMPd 0x052 474#define INSFP2_FCMPq 0x053 475#define INSFP2_FCMPEs 0x055 476#define INSFP2_FCMPEd 0x056 477#define INSFP2_FCMPEq 0x057 | 450#define INSFP2_FMOV_RCOFFS 0x04 451/* Use the IRCOND_* constants for rc. Operand types: s, d, q */ 452#define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS) 453#define INSFP2_FCMP 0x050 /* s, d, q */ 454#define INSFP2_FCMPE 0x054 /* s, d, q */ |
| 478 479/* IMPLDEP1 for Sun UltraSparc */ 480#define IIDP1_EDGE8 0x00 481#define IIDP1_EDGE8L 0x02 482#define IIDP1_EDGE16 0x04 483#define IIDP1_EDGE16L 0x06 484#define IIDP1_EDGE32 0x08 485#define IIDP1_EDGE32L 0x0a --- 101 unchanged lines hidden (view full) --- 587#define IFCOND_UE 0x0a 588#define IFCOND_GE 0x0b 589#define IFCOND_UGE 0x0c 590#define IFCOND_LE 0x0d 591#define IFCOND_ULE 0x0e 592#define IFCOND_O 0x0f 593 594/* rcond values for BPr, MOVr, FMOVr */ | 455 456/* IMPLDEP1 for Sun UltraSparc */ 457#define IIDP1_EDGE8 0x00 458#define IIDP1_EDGE8L 0x02 459#define IIDP1_EDGE16 0x04 460#define IIDP1_EDGE16L 0x06 461#define IIDP1_EDGE32 0x08 462#define IIDP1_EDGE32L 0x0a --- 101 unchanged lines hidden (view full) --- 564#define IFCOND_UE 0x0a 565#define IFCOND_GE 0x0b 566#define IFCOND_UGE 0x0c 567#define IFCOND_LE 0x0d 568#define IFCOND_ULE 0x0e 569#define IFCOND_O 0x0f 570 571/* rcond values for BPr, MOVr, FMOVr */ |
| 595#define IRCOND_RZ 0x01 | 572#define IRCOND_Z 0x01 |
| 596#define IRCOND_LEZ 0x02 597#define IRCOND_LZ 0x03 598#define IRCOND_NZ 0x05 599#define IRCOND_GZ 0x06 600#define IRCOND_GEZ 0x07 601 602/* cc values for MOVcc and FMOVcc */ 603#define IFCC_ICC 0x04 604#define IFCC_XCC 0x06 605/* if true, the lower 2 bits are the fcc number */ | 573#define IRCOND_LEZ 0x02 574#define IRCOND_LZ 0x03 575#define IRCOND_NZ 0x05 576#define IRCOND_GZ 0x06 577#define IRCOND_GEZ 0x07 578 579/* cc values for MOVcc and FMOVcc */ 580#define IFCC_ICC 0x04 581#define IFCC_XCC 0x06 582/* if true, the lower 2 bits are the fcc number */ |
| 606#define IFCC_FCC(c) (((c) & 4) == 0) | 583#define IFCC_FCC(c) ((c) & 3) 584#define IFCC_GET_FCC(c) ((c) & 3) 585#define IFCC_ISFCC(c) (((c) & 4) == 0) |
| 607 608/* cc values for BPc and Tcc */ 609#define IBCC_ICC 0x00 610#define IBCC_XCC 0x02 611 612/* 613 * Integer registers 614 */ 615#define IREG_G0 0x00 616#define IREG_O0 0x08 617#define IREG_L0 0x10 618#define IREQ_I0 0x18 619 620#endif /* !_MACHINE_INSTR_H_ */ | 586 587/* cc values for BPc and Tcc */ 588#define IBCC_ICC 0x00 589#define IBCC_XCC 0x02 590 591/* 592 * Integer registers 593 */ 594#define IREG_G0 0x00 595#define IREG_O0 0x08 596#define IREG_L0 0x10 597#define IREQ_I0 0x18 598 599#endif /* !_MACHINE_INSTR_H_ */ |