1/*
2 * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu
3 * Copyright (c) 1995 Paul Kranenburg
4 * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by David Miller.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp
33 *
| 1/*
2 * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu
3 * Copyright (c) 1995 Paul Kranenburg
4 * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by David Miller.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp
33 *
|
84#define IF_F3_RS1_SHIFT IF_F2_RS1_SHIFT
85#define IF_F3_RS1_BITS IF_F2_RS1_BITS
86#define IF_F3_I_SHIFT 13
87#define IF_F3_I_BITS 1
88#define IF_F3_X_SHIFT 12
89#define IF_F3_X_BITS 1
90#define IF_F3_RCOND_SHIFT 10
91#define IF_F3_RCOND_BITS 3
92#define IF_F3_IMM_ASI_SHIFT 5
93#define IF_F3_IMM_ASI_BITS 8
94#define IF_F3_OPF_SHIFT 5
95#define IF_F3_OPF_BITS 9
96#define IF_F3_CMASK_SHIFT 4
97#define IF_F3_CMASK_BITS 3
98#define IF_F3_RS2_SHIFT 0
99#define IF_F3_RS2_BITS 5
100#define IF_F3_SHCNT32_SHIFT 0
101#define IF_F3_SHCNT32_BITS 5
102#define IF_F3_SHCNT64_SHIFT 0
103#define IF_F3_SHCNT64_BITS 6
104
105/*
106 * Definitions for format 4
107 */
108#define IF_F4_OP3_SHIFT IF_F3_OP3_SHIFT
109#define IF_F4_OP3_BITS IF_F3_OP3_BITS
110#define IF_F4_RD_SHIFT IF_F2_RD_SHIFT
111#define IF_F4_RD_BITS IF_F2_RD_BITS
112#define IF_F4_RS1_SHIFT IF_F2_RS1_SHIFT
113#define IF_F4_RS1_BITS IF_F2_RS1_BITS
114#define IF_F4_TCOND_SHIFT IF_F2_COND_SHIFT /* cond for Tcc */
115#define IF_F4_TCOND_BITS IF_F2_COND_BITS
116#define IF_F4_CC2_SHIFT 18
117#define IF_F4_CC2_BITS 1
118#define IF_F4_COND_SHIFT 14
119#define IF_F4_COND_BITS 4
120#define IF_F4_I_SHIFT IF_F3_I_SHIFT
121#define IF_F4_I_BITS IF_F3_I_BITS
122#define IF_F4_OPF_CC_SHIFT 11
123#define IF_F4_OPF_CC_BITS 3
124#define IF_F4_CC1_SHIFT 12
125#define IF_F4_CC1_BITS 1
126#define IF_F4_CC0_SHIFT 11
127#define IF_F4_CC0_BITS 1
128#define IF_F4_RCOND_SHIFT IF_F3_RCOND_SHIFT
129#define IF_F4_RCOND_BITS IF_F3_RCOND_BITS
130#define IF_F4_OPF_LOW_SHIFT 5
131#define IF_F4_RS2_SHIFT IF_F3_RS2_SHIFT
132#define IF_F4_RS2_BITS IF_F3_RS2_BITS
133#define IF_F4_SW_TRAP_SHIFT 0
134#define IF_F4_SW_TRAP_BITS 7
135
136/*
137 * Macros to decode instructions
138 */
139/* Extract a field */
140#define IF_MASK(s, w) (((1 << (w)) - 1) << (s))
141#define IF_EXTRACT(x, s, w) (((x) & IF_MASK((s), (w))) >> (s))
142#define IF_DECODE(x, f) \
143 IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS)
144
145/* Sign-extend a field of width W */
146#define IF_SEXT(x, w) \
147 (((x) & (1 << ((w) - 1))) != 0 ? (-1L - ((x) ^ ((1 << (w)) - 1))) : (x))
148
149#if 0
150/*
151 * The following C variant is from db_disassemble.c, and surely faster, but it
152 * relies on behaviour that is undefined by the C standard (>> in conjunction
153 * with signed negative arguments).
154 */
155#define IF_SEXT(v, w) ((((long long)(v)) << (64 - w)) >> (64 - w))
156/* Assembler version of the above */
157#define IF_SEXT(v, w) \
158 { u_long t; ( __asm __volatile("sllx %1, %2, %0; srax %0, %2, %0" :
159 "=r" (t) : "r" (v) : "i" (64 - w)); t)}
160#endif
161
162/* All instruction formats */
163#define IF_OP(i) IF_DECODE(i, OP)
164
165/* Instruction format 2 */
166#define IF_F2_RD(i) IF_DECODE((i), F2_RD)
167#define IF_F2_A(i) IF_DECODE((i), F2_A)
168#define IF_F2_COND(i) IF_DECODE((i), F2_COND)
169#define IF_F2_RCOND(i) IF_DECODE((i), F2_RCOND)
170#define IF_F2_OP2(i) IF_DECODE((i), F2_OP2)
171#define IF_F2_CC1(i) IF_DECODE((i), F2_CC1)
172#define IF_F2_CC0(i) IF_DECODE((i), F2_CC0)
| 88#define IF_F3_RS1_SHIFT IF_F2_RS1_SHIFT
89#define IF_F3_RS1_BITS IF_F2_RS1_BITS
90#define IF_F3_I_SHIFT 13
91#define IF_F3_I_BITS 1
92#define IF_F3_X_SHIFT 12
93#define IF_F3_X_BITS 1
94#define IF_F3_RCOND_SHIFT 10
95#define IF_F3_RCOND_BITS 3
96#define IF_F3_IMM_ASI_SHIFT 5
97#define IF_F3_IMM_ASI_BITS 8
98#define IF_F3_OPF_SHIFT 5
99#define IF_F3_OPF_BITS 9
100#define IF_F3_CMASK_SHIFT 4
101#define IF_F3_CMASK_BITS 3
102#define IF_F3_RS2_SHIFT 0
103#define IF_F3_RS2_BITS 5
104#define IF_F3_SHCNT32_SHIFT 0
105#define IF_F3_SHCNT32_BITS 5
106#define IF_F3_SHCNT64_SHIFT 0
107#define IF_F3_SHCNT64_BITS 6
108
109/*
110 * Definitions for format 4
111 */
112#define IF_F4_OP3_SHIFT IF_F3_OP3_SHIFT
113#define IF_F4_OP3_BITS IF_F3_OP3_BITS
114#define IF_F4_RD_SHIFT IF_F2_RD_SHIFT
115#define IF_F4_RD_BITS IF_F2_RD_BITS
116#define IF_F4_RS1_SHIFT IF_F2_RS1_SHIFT
117#define IF_F4_RS1_BITS IF_F2_RS1_BITS
118#define IF_F4_TCOND_SHIFT IF_F2_COND_SHIFT /* cond for Tcc */
119#define IF_F4_TCOND_BITS IF_F2_COND_BITS
120#define IF_F4_CC2_SHIFT 18
121#define IF_F4_CC2_BITS 1
122#define IF_F4_COND_SHIFT 14
123#define IF_F4_COND_BITS 4
124#define IF_F4_I_SHIFT IF_F3_I_SHIFT
125#define IF_F4_I_BITS IF_F3_I_BITS
126#define IF_F4_OPF_CC_SHIFT 11
127#define IF_F4_OPF_CC_BITS 3
128#define IF_F4_CC1_SHIFT 12
129#define IF_F4_CC1_BITS 1
130#define IF_F4_CC0_SHIFT 11
131#define IF_F4_CC0_BITS 1
132#define IF_F4_RCOND_SHIFT IF_F3_RCOND_SHIFT
133#define IF_F4_RCOND_BITS IF_F3_RCOND_BITS
134#define IF_F4_OPF_LOW_SHIFT 5
135#define IF_F4_RS2_SHIFT IF_F3_RS2_SHIFT
136#define IF_F4_RS2_BITS IF_F3_RS2_BITS
137#define IF_F4_SW_TRAP_SHIFT 0
138#define IF_F4_SW_TRAP_BITS 7
139
140/*
141 * Macros to decode instructions
142 */
143/* Extract a field */
144#define IF_MASK(s, w) (((1 << (w)) - 1) << (s))
145#define IF_EXTRACT(x, s, w) (((x) & IF_MASK((s), (w))) >> (s))
146#define IF_DECODE(x, f) \
147 IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS)
148
149/* Sign-extend a field of width W */
150#define IF_SEXT(x, w) \
151 (((x) & (1 << ((w) - 1))) != 0 ? (-1L - ((x) ^ ((1 << (w)) - 1))) : (x))
152
153#if 0
154/*
155 * The following C variant is from db_disassemble.c, and surely faster, but it
156 * relies on behaviour that is undefined by the C standard (>> in conjunction
157 * with signed negative arguments).
158 */
159#define IF_SEXT(v, w) ((((long long)(v)) << (64 - w)) >> (64 - w))
160/* Assembler version of the above */
161#define IF_SEXT(v, w) \
162 { u_long t; ( __asm __volatile("sllx %1, %2, %0; srax %0, %2, %0" :
163 "=r" (t) : "r" (v) : "i" (64 - w)); t)}
164#endif
165
166/* All instruction formats */
167#define IF_OP(i) IF_DECODE(i, OP)
168
169/* Instruction format 2 */
170#define IF_F2_RD(i) IF_DECODE((i), F2_RD)
171#define IF_F2_A(i) IF_DECODE((i), F2_A)
172#define IF_F2_COND(i) IF_DECODE((i), F2_COND)
173#define IF_F2_RCOND(i) IF_DECODE((i), F2_RCOND)
174#define IF_F2_OP2(i) IF_DECODE((i), F2_OP2)
175#define IF_F2_CC1(i) IF_DECODE((i), F2_CC1)
176#define IF_F2_CC0(i) IF_DECODE((i), F2_CC0)
|
183#define IF_F3_RS1(i) IF_F2_RS1((i))
184#define IF_F3_I(i) IF_DECODE((i), F3_I)
185#define IF_F3_X(i) IF_DECODE((i), F3_X)
186#define IF_F3_RCOND(i) IF_DECODE((i), F3_RCOND)
187#define IF_F3_IMM_ASI(i) IF_DECODE((i), F3_IMM_ASI)
188#define IF_F3_OPF(i) IF_DECODE((i), F3_OPF)
189#define IF_F3_CMASK(i) IF_DECODE((i), F3_CMASK)
190#define IF_F3_RS2(i) IF_DECODE((i), F3_RS2)
191#define IF_F3_SHCNT32(i) IF_DECODE((i), F3_SHCNT32)
192#define IF_F3_SHCNT64(i) IF_DECODE((i), F3_SHCNT64)
193
194/* Instruction format 4 */
195#define IF_F4_OP3(i) IF_F3_OP3((i))
196#define IF_F4_RD(i) IF_F3_RD((i))
197#define IF_F4_TCOND(i) IF_DECODE((i), F4_TCOND)
198#define IF_F4_RS1(i) IF_F3_RS1((i))
199#define IF_F4_CC2(i) IF_DECODE((i), F4_CC2)
200#define IF_F4_COND(i) IF_DECODE((i), F4_COND)
201#define IF_F4_I(i) IF_F3_I((i))
202#define IF_F4_OPF_CC(i) IF_DECODE((i), F4_OPF_CC)
203#define IF_F4_RCOND(i) IF_F3_RCOND((i))
204#define IF_F4_OPF_LOW(i, w) IF_EXTRACT((i), IF_F4_OPF_LOW_SHIFT, (w))
205#define IF_F4_RS2(i) IF_F3_RS2((i))
206#define IF_F4_SW_TRAP(i) IF_DECODE((i), F4_SW_TRAP)
207
208/* Extract an immediate from an instruction, with an without sign extension */
209#define IF_IMM(i, w) IF_EXTRACT((i), IF_IMM_SHIFT, (w))
210#define IF_SIMM(i, w) ({ u_long b = (w), x = IF_IMM((i), b); IF_SEXT((x), b); })
211
212/*
213 * Macros to encode instructions
214 */
215#define IF_INSERT(x, s, w) (((x) & ((1 << (w)) - 1)) << (s))
216#define IF_ENCODE(x, f) \
217 IF_INSERT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS)
218
219/* All instruction formats */
220#define EIF_OP(x) IF_ENCODE((x), OP)
221
222/* Instruction format 2 */
223#define EIF_F2_RD(x) IF_ENCODE((x), F2_RD)
224#define EIF_F2_A(x) IF_ENCODE((x), F2_A)
225#define EIF_F2_COND(x) IF_ENCODE((x), F2_COND)
226#define EIF_F2_RCOND(x) IF_ENCODE((x), F2_RCOND)
227#define EIF_F2_OP2(x) IF_ENCODE((x), F2_OP2)
228#define EIF_F2_CC1(x) IF_ENCODE((x), F2_CC1)
229#define EIF_F2_CC0(x) IF_ENCODE((x), F2_CC0)
230#define EIF_F2_D16HI(x) IF_ENCODE((x), F2_D16HI)
231#define EIF_F2_P(x) IF_ENCODE((x), F2_P)
232#define EIF_F2_RS1(x) IF_ENCODE((x), F2_RS1)
233
234/* Instruction format 3 */
235#define EIF_F3_OP3(x) IF_ENCODE((x), F3_OP3)
236#define EIF_F3_RD(x) EIF_F2_RD((x))
237#define EIF_F3_FCN(x) IF_ENCODE((x), F3_FCN)
238#define EIF_F3_CC1(x) IF_ENCODE((x), F3_CC1)
239#define EIF_F3_CC0(x) IF_ENCODE((x), F3_CC0)
240#define EIF_F3_RS1(x) EIF_F2_RS1((x))
241#define EIF_F3_I(x) IF_ENCODE((x), F3_I)
242#define EIF_F3_X(x) IF_ENCODE((x), F3_X)
243#define EIF_F3_RCOND(x) IF_ENCODE((x), F3_RCOND)
244#define EIF_F3_IMM_ASI(x) IF_ENCODE((x), F3_IMM_ASI)
245#define EIF_F3_OPF(x) IF_ENCODE((x), F3_OPF)
246#define EIF_F3_CMASK(x) IF_ENCODE((x), F3_CMASK)
247#define EIF_F3_RS2(x) IF_ENCODE((x), F3_RS2)
248#define EIF_F3_SHCNT32(x) IF_ENCODE((x), F3_SHCNT32)
249#define EIF_F3_SHCNT64(x) IF_ENCODE((x), F3_SHCNT64)
250
251/* Instruction format 4 */
252#define EIF_F4_OP3(x) EIF_F3_OP3((x))
253#define EIF_F4_RD(x) EIF_F2_RD((x))
254#define EIF_F4_TCOND(x) IF_ENCODE((x), F4_TCOND)
255#define EIF_F4_RS1(x) EIF_F2_RS1((x))
256#define EIF_F4_CC2(x) IF_ENCODE((x), F4_CC2)
257#define EIF_F4_COND(x) IF_ENCODE((x), F4_COND)
258#define EIF_F4_I(x) EIF_F3_I((x))
259#define EIF_F4_OPF_CC(x) IF_ENCODE((x), F4_OPF_CC)
260#define EIF_F4_RCOND(x) EIF_F3_RCOND((x))
261#define EIF_F4_OPF_LOW(i, w) IF_INSERT((x), IF_F4_OPF_CC_SHIFT, (w))
262#define EIF_F4_RS2(x) EIF_F3_RS2((x))
263#define EIF_F4_SW_TRAP(x) IF_ENCODE((x), F4_SW_TRAP)
264
265/* Immediates */
266#define EIF_IMM(x, w) IF_INSERT((x), IF_IMM_SHIFT, (w))
267#define EIF_SIMM(x, w) IF_EIMM((x), (w))
268
269/*
270 * OP field values (specifying the instruction format)
271 */
272#define IOP_FORM2 0x00 /* Format 2: sethi, branches */
273#define IOP_CALL 0x01 /* Format 1: call */
274#define IOP_MISC 0x02 /* Format 3 or 4: arith & misc */
275#define IOP_LDST 0x03 /* Format 4: loads and stores */
276
277/*
278 * OP2/OP3 values (specifying the actual instruction)
279 */
280/* OP2 values for format 2 (OP = 0) */
281#define INS0_ILLTRAP 0x00
282#define INS0_BPcc 0x01
283#define INS0_Bicc 0x02
284#define INS0_BPr 0x03
285#define INS0_SETHI 0x04 /* with rd = 0 and imm22 = 0, nop */
286#define INS0_FBPfcc 0x05
287#define INS0_FBfcc 0x06
288/* undefined 0x07 */
289
290/* OP3 values for Format 3 and 4 (OP = 2) */
291#define INS2_ADD 0x00
292#define INS2_AND 0x01
293#define INS2_OR 0x02
294#define INS2_XOR 0x03
295#define INS2_SUB 0x04
296#define INS2_ANDN 0x05
297#define INS2_ORN 0x06
298#define INS2_XNOR 0x07
299#define INS2_ADDC 0x08
300#define INS2_MULX 0x09
301#define INS2_UMUL 0x0a
302#define INS2_SMUL 0x0b
303#define INS2_SUBC 0x0c
304#define INS2_UDIVX 0x0d
305#define INS2_UDIV 0x0e
306#define INS2_SDIV 0x0f
307#define INS2_ADDcc 0x10
308#define INS2_ANDcc 0x11
309#define INS2_ORcc 0x12
310#define INS2_XORcc 0x13
311#define INS2_SUBcc 0x14
312#define INS2_ANDNcc 0x15
313#define INS2_ORNcc 0x16
314#define INS2_XNORcc 0x17
315#define INS2_ADDCcc 0x18
316/* undefined 0x19 */
317#define INS2_UMULcc 0x1a
318#define INS2_SMULcc 0x1b
319#define INS2_SUBCcc 0x1c
320/* undefined 0x1d */
321#define INS2_UDIVcc 0x1e
322#define INS2_SDIVcc 0x1f
323#define INS2_TADDcc 0x20
324#define INS2_TSUBcc 0x21
325#define INS2_TADDccTV 0x22
326#define INS2_TSUBccTV 0x23
327#define INS2_MULScc 0x24
328#define INS2_SSL 0x25 /* SLLX when IF_X(i) == 1 */
329#define INS2_SRL 0x26 /* SRLX when IF_X(i) == 1 */
330#define INS2_SRA 0x27 /* SRAX when IF_X(i) == 1 */
331#define INS2_RD 0x28 /* and MEMBAR, STBAR */
332/* undefined 0x29 */
333#define INS2_RDPR 0x2a
334#define INS2_FLUSHW 0x2b
335#define INS2_MOVcc 0x2c
336#define INS2_SDIVX 0x2d
337#define INS2_POPC 0x2e /* undefined if IF_RS1(i) != 0 */
338#define INS2_MOVr 0x2f
339#define INS2_WR 0x30 /* and SIR */
340#define INS2_SV_RSTR 0x31 /* saved, restored */
341#define INS2_WRPR 0x32
342/* undefined 0x33 */
343#define INS2_FPop1 0x34 /* further encoded in opf field */
344#define INS2_FPop2 0x35 /* further encoded in opf field */
345#define INS2_IMPLDEP1 0x36
346#define INS2_IMPLDEP2 0x37
347#define INS2_JMPL 0x38
348#define INS2_RETURN 0x39
349#define INS2_Tcc 0x3a
350#define INS2_FLUSH 0x3b
351#define INS2_SAVE 0x3c
352#define INS2_RESTORE 0x3d
353#define INS2_DONE_RETR 0x3e /* done, retry */
354/* undefined 0x3f */
355
356/* OP3 values for format 3 (OP = 3) */
357#define INS3_LDUW 0x00
358#define INS3_LDUB 0x01
359#define INS3_LDUH 0x02
360#define INS3_LDD 0x03
361#define INS3_STW 0x04
362#define INS3_STB 0x05
363#define INS3_STH 0x06
364#define INS3_STD 0x07
365#define INS3_LDSW 0x08
366#define INS3_LDSB 0x09
367#define INS3_LDSH 0x0a
368#define INS3_LDX 0x0b
369/* undefined 0x0c */
370#define INS3_LDSTUB 0x0d
371#define INS3_STX 0x0e
372#define INS3_SWAP 0x0f
373#define INS3_LDUWA 0x10
374#define INS3_LDUBA 0x11
375#define INS3_LDUHA 0x12
376#define INS3_LDDA 0x13
377#define INS3_STWA 0x14
378#define INS3_STBA 0x15
379#define INS3_STHA 0x16
380#define INS3_STDA 0x17
381#define INS3_LDSWA 0x18
382#define INS3_LDSBA 0x19
383#define INS3_LDSHA 0x1a
384#define INS3_LDXA 0x1b
385/* undefined 0x1c */
386#define INS3_LDSTUBA 0x1d
387#define INS3_STXA 0x1e
388#define INS3_SWAPA 0x1f
389#define INS3_LDF 0x20
390#define INS3_LDFSR 0x21 /* and LDXFSR */
391#define INS3_LDQF 0x22
392#define INS3_LDDF 0x23
393#define INS3_STF 0x24
394#define INS3_STFSR 0x25 /* and STXFSR */
395#define INS3_STQF 0x26
396#define INS3_STDF 0x27
397/* undefined 0x28 - 0x2c */
398#define INS3_PREFETCH 0x2d
399/* undefined 0x2e - 0x2f */
400#define INS3_LDFA 0x30
401/* undefined 0x31 */
402#define INS3_LDQFA 0x32
403#define INS3_LDDFA 0x33
404#define INS3_STFA 0x34
405/* undefined 0x35 */
406#define INS3_STQFA 0x36
407#define INS3_STDFA 0x37
408/* undefined 0x38 - 0x3b */
409#define INS3_CASA 0x39
410#define INS3_PREFETCHA 0x3a
411#define INS3_CASXA 0x3b
412
413/*
414 * OPF values (floating point instructions, IMPLDEP)
415 */
416/*
417 * These values are or'ed to the FPop values to get the instructions.
418 * They describe the operand type(s).
419 */
420#define INSFP_i 0x000 /* 32-bit int */
421#define INSFP_s 0x001 /* 32-bit single */
422#define INSFP_d 0x002 /* 64-bit double */
423#define INSFP_q 0x003 /* 128-bit quad */
424/* FPop1. The comments give the types for which this instruction is defined. */
425#define INSFP1_FMOV 0x000 /* s, d, q */
426#define INSFP1_FNEG 0x004 /* s, d, q */
427#define INSFP1_FABS 0x008 /* s, d, q */
428#define INSFP1_FSQRT 0x028 /* s, d, q */
429#define INSFP1_FADD 0x040 /* s, d, q */
430#define INSFP1_FSUB 0x044 /* s, d, q */
431#define INSFP1_FMUL 0x048 /* s, d, q */
432#define INSFP1_FDIV 0x04c /* s, d, q */
433#define INSFP1_FsMULd 0x068 /* s */
434#define INSFP1_FdMULq 0x06c /* d */
435#define INSFP1_FTOx 0x080 /* s, d, q */
436#define INSFP1_FxTOs 0x084 /* special: i only */
437#define INSFP1_FxTOd 0x088 /* special: i only */
438#define INSFP1_FxTOq 0x08c /* special: i only */
439#define INSFP1_FTOs 0x0c4 /* i, d, q */
440#define INSFP1_FTOd 0x0c8 /* i, s, q */
441#define INSFP1_FTOq 0x0cc /* i, s, d */
442#define INSFP1_FTOi 0x0d0 /* i, s, d */
443
444/* FPop2 */
445#define INSFP2_FMOV_CCMUL 0x40
446#define INSFP2_FMOV_CCOFFS 0x00
447/* Use the IFCC_* constants for cc. Operand types: s, d, q */
448#define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS)
449#define INSFP2_FMOV_RCMUL 0x20
450#define INSFP2_FMOV_RCOFFS 0x04
451/* Use the IRCOND_* constants for rc. Operand types: s, d, q */
452#define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS)
453#define INSFP2_FCMP 0x050 /* s, d, q */
454#define INSFP2_FCMPE 0x054 /* s, d, q */
455
456/* IMPLDEP1 for Sun UltraSparc */
457#define IIDP1_EDGE8 0x00
458#define IIDP1_EDGE8L 0x02
459#define IIDP1_EDGE16 0x04
460#define IIDP1_EDGE16L 0x06
461#define IIDP1_EDGE32 0x08
462#define IIDP1_EDGE32L 0x0a
463#define IIDP1_ARRAY8 0x10
464#define IIDP1_ARRAY16 0x12
465#define IIDP1_ARRAY32 0x14
466#define IIDP1_ALIGNADDRESS 0x18
467#define IIDP1_ALIGNADDRESS_L 0x1a
468#define IIDP1_FCMPLE16 0x20
469#define IIDP1_FCMPNE16 0x22
470#define IIDP1_FCMPLE32 0x24
471#define IIDP1_FCMPNE32 0x26
472#define IIDP1_FCMPGT16 0x28
473#define IIDP1_FCMPEQ16 0x2a
474#define IIDP1_FCMPGT32 0x2c
475#define IIDP1_FCMPEQ32 0x2e
476#define IIDP1_FMUL8x16 0x31
477#define IIDP1_FMUL8x16AU 0x33
478#define IIDP1_FMUL8X16AL 0x35
479#define IIDP1_FMUL8SUx16 0x36
480#define IIDP1_FMUL8ULx16 0x37
481#define IIDP1_FMULD8SUx16 0x38
482#define IIDP1_FMULD8ULx16 0x39
483#define IIDP1_FPACK32 0x3a
484#define IIDP1_FPACK16 0x3b
485#define IIDP1_FPACKFIX 0x3d
486#define IIDP1_PDIST 0x3e
487#define IIDP1_FALIGNDATA 0x48
488#define IIDP1_FPMERGE 0x4b
489#define IIDP1_FEXPAND 0x4d
490#define IIDP1_FPADD16 0x50
491#define IIDP1_FPADD16S 0x51
492#define IIDP1_FPADD32 0x52
493#define IIDP1_FPADD32S 0x53
494#define IIDP1_SUB16 0x54
495#define IIDP1_SUB16S 0x55
496#define IIDP1_SUB32 0x56
497#define IIDP1_SUB32S 0x57
498#define IIDP1_FZERO 0x60
499#define IIDP1_FZEROS 0x61
500#define IIDP1_FNOR 0x62
501#define IIDP1_FNORS 0x63
502#define IIDP1_FANDNOT2 0x64
503#define IIDP1_FANDNOT2S 0x65
504#define IIDP1_NOT2 0x66
505#define IIDP1_NOT2S 0x67
506#define IIDP1_FANDNOT1 0x68
507#define IIDP1_FANDNOT1S 0x69
508#define IIDP1_FNOT1 0x6a
509#define IIDP1_FNOT1S 0x6b
510#define IIDP1_FXOR 0x6c
511#define IIDP1_FXORS 0x6d
512#define IIDP1_FNAND 0x6e
513#define IIDP1_FNANDS 0x6f
514#define IIDP1_FAND 0x70
515#define IIDP1_FANDS 0x71
516#define IIDP1_FXNOR 0x72
517#define IIDP1_FXNORS 0x73
518#define IIDP1_FSRC1 0x74
519#define IIDP1_FSRC1S 0x75
520#define IIDP1_FORNOT2 0x76
521#define IIDP1_FORNOT2S 0x77
522#define IIDP1_FSRC2 0x78
523#define IIDP1_FSRC2S 0x79
524#define IIDP1_FORNOT1 0x7a
525#define IIDP1_FORNOT1S 0x7b
526#define IIDP1_FOR 0x7c
527#define IIDP1_FORS 0x7d
528#define IIDP1_FONE 0x7e
529#define IIDP1_FONES 0x7f
530#define IIDP1_SHUTDOWN 0x80
531
532/*
533 * Instruction modifiers
534 */
535/* cond values for integer ccr's */
536#define IICOND_N 0x00
537#define IICOND_E 0x01
538#define IICOND_LE 0x02
539#define IICOND_L 0x03
540#define IICOND_LEU 0x04
541#define IICOND_CS 0x05
542#define IICOND_NEG 0x06
543#define IICOND_VS 0x07
544#define IICOND_A 0x08
545#define IICOND_NE 0x09
546#define IICOND_G 0x0a
547#define IICOND_GE 0x0b
548#define IICOND_GU 0x0c
549#define IICOND_CC 0x0d
550#define IICOND_POS 0x0e
551#define IICOND_VC 0x0f
552
553/* cond values for fp ccr's */
554#define IFCOND_N 0x00
555#define IFCOND_NE 0x01
556#define IFCOND_LG 0x02
557#define IFCOND_UL 0x03
558#define IFCOND_L 0x04
559#define IFCOND_UG 0x05
560#define IFCOND_G 0x06
561#define IFCOND_U 0x07
562#define IFCOND_A 0x08
563#define IFCOND_E 0x09
564#define IFCOND_UE 0x0a
565#define IFCOND_GE 0x0b
566#define IFCOND_UGE 0x0c
567#define IFCOND_LE 0x0d
568#define IFCOND_ULE 0x0e
569#define IFCOND_O 0x0f
570
571/* rcond values for BPr, MOVr, FMOVr */
572#define IRCOND_Z 0x01
573#define IRCOND_LEZ 0x02
574#define IRCOND_LZ 0x03
575#define IRCOND_NZ 0x05
576#define IRCOND_GZ 0x06
577#define IRCOND_GEZ 0x07
578
579/* cc values for MOVcc and FMOVcc */
580#define IFCC_ICC 0x04
581#define IFCC_XCC 0x06
582/* if true, the lower 2 bits are the fcc number */
583#define IFCC_FCC(c) ((c) & 3)
584#define IFCC_GET_FCC(c) ((c) & 3)
585#define IFCC_ISFCC(c) (((c) & 4) == 0)
586
587/* cc values for BPc and Tcc */
588#define IBCC_ICC 0x00
589#define IBCC_XCC 0x02
590
591/*
592 * Integer registers
593 */
594#define IREG_G0 0x00
595#define IREG_O0 0x08
596#define IREG_L0 0x10
597#define IREQ_I0 0x18
598
599#endif /* !_MACHINE_INSTR_H_ */
| 189#define IF_F3_RS1(i) IF_F2_RS1((i))
190#define IF_F3_I(i) IF_DECODE((i), F3_I)
191#define IF_F3_X(i) IF_DECODE((i), F3_X)
192#define IF_F3_RCOND(i) IF_DECODE((i), F3_RCOND)
193#define IF_F3_IMM_ASI(i) IF_DECODE((i), F3_IMM_ASI)
194#define IF_F3_OPF(i) IF_DECODE((i), F3_OPF)
195#define IF_F3_CMASK(i) IF_DECODE((i), F3_CMASK)
196#define IF_F3_RS2(i) IF_DECODE((i), F3_RS2)
197#define IF_F3_SHCNT32(i) IF_DECODE((i), F3_SHCNT32)
198#define IF_F3_SHCNT64(i) IF_DECODE((i), F3_SHCNT64)
199
200/* Instruction format 4 */
201#define IF_F4_OP3(i) IF_F3_OP3((i))
202#define IF_F4_RD(i) IF_F3_RD((i))
203#define IF_F4_TCOND(i) IF_DECODE((i), F4_TCOND)
204#define IF_F4_RS1(i) IF_F3_RS1((i))
205#define IF_F4_CC2(i) IF_DECODE((i), F4_CC2)
206#define IF_F4_COND(i) IF_DECODE((i), F4_COND)
207#define IF_F4_I(i) IF_F3_I((i))
208#define IF_F4_OPF_CC(i) IF_DECODE((i), F4_OPF_CC)
209#define IF_F4_RCOND(i) IF_F3_RCOND((i))
210#define IF_F4_OPF_LOW(i, w) IF_EXTRACT((i), IF_F4_OPF_LOW_SHIFT, (w))
211#define IF_F4_RS2(i) IF_F3_RS2((i))
212#define IF_F4_SW_TRAP(i) IF_DECODE((i), F4_SW_TRAP)
213
214/* Extract an immediate from an instruction, with an without sign extension */
215#define IF_IMM(i, w) IF_EXTRACT((i), IF_IMM_SHIFT, (w))
216#define IF_SIMM(i, w) ({ u_long b = (w), x = IF_IMM((i), b); IF_SEXT((x), b); })
217
218/*
219 * Macros to encode instructions
220 */
221#define IF_INSERT(x, s, w) (((x) & ((1 << (w)) - 1)) << (s))
222#define IF_ENCODE(x, f) \
223 IF_INSERT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS)
224
225/* All instruction formats */
226#define EIF_OP(x) IF_ENCODE((x), OP)
227
228/* Instruction format 2 */
229#define EIF_F2_RD(x) IF_ENCODE((x), F2_RD)
230#define EIF_F2_A(x) IF_ENCODE((x), F2_A)
231#define EIF_F2_COND(x) IF_ENCODE((x), F2_COND)
232#define EIF_F2_RCOND(x) IF_ENCODE((x), F2_RCOND)
233#define EIF_F2_OP2(x) IF_ENCODE((x), F2_OP2)
234#define EIF_F2_CC1(x) IF_ENCODE((x), F2_CC1)
235#define EIF_F2_CC0(x) IF_ENCODE((x), F2_CC0)
236#define EIF_F2_D16HI(x) IF_ENCODE((x), F2_D16HI)
237#define EIF_F2_P(x) IF_ENCODE((x), F2_P)
238#define EIF_F2_RS1(x) IF_ENCODE((x), F2_RS1)
239
240/* Instruction format 3 */
241#define EIF_F3_OP3(x) IF_ENCODE((x), F3_OP3)
242#define EIF_F3_RD(x) EIF_F2_RD((x))
243#define EIF_F3_FCN(x) IF_ENCODE((x), F3_FCN)
244#define EIF_F3_CC1(x) IF_ENCODE((x), F3_CC1)
245#define EIF_F3_CC0(x) IF_ENCODE((x), F3_CC0)
246#define EIF_F3_RS1(x) EIF_F2_RS1((x))
247#define EIF_F3_I(x) IF_ENCODE((x), F3_I)
248#define EIF_F3_X(x) IF_ENCODE((x), F3_X)
249#define EIF_F3_RCOND(x) IF_ENCODE((x), F3_RCOND)
250#define EIF_F3_IMM_ASI(x) IF_ENCODE((x), F3_IMM_ASI)
251#define EIF_F3_OPF(x) IF_ENCODE((x), F3_OPF)
252#define EIF_F3_CMASK(x) IF_ENCODE((x), F3_CMASK)
253#define EIF_F3_RS2(x) IF_ENCODE((x), F3_RS2)
254#define EIF_F3_SHCNT32(x) IF_ENCODE((x), F3_SHCNT32)
255#define EIF_F3_SHCNT64(x) IF_ENCODE((x), F3_SHCNT64)
256
257/* Instruction format 4 */
258#define EIF_F4_OP3(x) EIF_F3_OP3((x))
259#define EIF_F4_RD(x) EIF_F2_RD((x))
260#define EIF_F4_TCOND(x) IF_ENCODE((x), F4_TCOND)
261#define EIF_F4_RS1(x) EIF_F2_RS1((x))
262#define EIF_F4_CC2(x) IF_ENCODE((x), F4_CC2)
263#define EIF_F4_COND(x) IF_ENCODE((x), F4_COND)
264#define EIF_F4_I(x) EIF_F3_I((x))
265#define EIF_F4_OPF_CC(x) IF_ENCODE((x), F4_OPF_CC)
266#define EIF_F4_RCOND(x) EIF_F3_RCOND((x))
267#define EIF_F4_OPF_LOW(i, w) IF_INSERT((x), IF_F4_OPF_CC_SHIFT, (w))
268#define EIF_F4_RS2(x) EIF_F3_RS2((x))
269#define EIF_F4_SW_TRAP(x) IF_ENCODE((x), F4_SW_TRAP)
270
271/* Immediates */
272#define EIF_IMM(x, w) IF_INSERT((x), IF_IMM_SHIFT, (w))
273#define EIF_SIMM(x, w) IF_EIMM((x), (w))
274
275/*
276 * OP field values (specifying the instruction format)
277 */
278#define IOP_FORM2 0x00 /* Format 2: sethi, branches */
279#define IOP_CALL 0x01 /* Format 1: call */
280#define IOP_MISC 0x02 /* Format 3 or 4: arith & misc */
281#define IOP_LDST 0x03 /* Format 4: loads and stores */
282
283/*
284 * OP2/OP3 values (specifying the actual instruction)
285 */
286/* OP2 values for format 2 (OP = 0) */
287#define INS0_ILLTRAP 0x00
288#define INS0_BPcc 0x01
289#define INS0_Bicc 0x02
290#define INS0_BPr 0x03
291#define INS0_SETHI 0x04 /* with rd = 0 and imm22 = 0, nop */
292#define INS0_FBPfcc 0x05
293#define INS0_FBfcc 0x06
294/* undefined 0x07 */
295
296/* OP3 values for Format 3 and 4 (OP = 2) */
297#define INS2_ADD 0x00
298#define INS2_AND 0x01
299#define INS2_OR 0x02
300#define INS2_XOR 0x03
301#define INS2_SUB 0x04
302#define INS2_ANDN 0x05
303#define INS2_ORN 0x06
304#define INS2_XNOR 0x07
305#define INS2_ADDC 0x08
306#define INS2_MULX 0x09
307#define INS2_UMUL 0x0a
308#define INS2_SMUL 0x0b
309#define INS2_SUBC 0x0c
310#define INS2_UDIVX 0x0d
311#define INS2_UDIV 0x0e
312#define INS2_SDIV 0x0f
313#define INS2_ADDcc 0x10
314#define INS2_ANDcc 0x11
315#define INS2_ORcc 0x12
316#define INS2_XORcc 0x13
317#define INS2_SUBcc 0x14
318#define INS2_ANDNcc 0x15
319#define INS2_ORNcc 0x16
320#define INS2_XNORcc 0x17
321#define INS2_ADDCcc 0x18
322/* undefined 0x19 */
323#define INS2_UMULcc 0x1a
324#define INS2_SMULcc 0x1b
325#define INS2_SUBCcc 0x1c
326/* undefined 0x1d */
327#define INS2_UDIVcc 0x1e
328#define INS2_SDIVcc 0x1f
329#define INS2_TADDcc 0x20
330#define INS2_TSUBcc 0x21
331#define INS2_TADDccTV 0x22
332#define INS2_TSUBccTV 0x23
333#define INS2_MULScc 0x24
334#define INS2_SSL 0x25 /* SLLX when IF_X(i) == 1 */
335#define INS2_SRL 0x26 /* SRLX when IF_X(i) == 1 */
336#define INS2_SRA 0x27 /* SRAX when IF_X(i) == 1 */
337#define INS2_RD 0x28 /* and MEMBAR, STBAR */
338/* undefined 0x29 */
339#define INS2_RDPR 0x2a
340#define INS2_FLUSHW 0x2b
341#define INS2_MOVcc 0x2c
342#define INS2_SDIVX 0x2d
343#define INS2_POPC 0x2e /* undefined if IF_RS1(i) != 0 */
344#define INS2_MOVr 0x2f
345#define INS2_WR 0x30 /* and SIR */
346#define INS2_SV_RSTR 0x31 /* saved, restored */
347#define INS2_WRPR 0x32
348/* undefined 0x33 */
349#define INS2_FPop1 0x34 /* further encoded in opf field */
350#define INS2_FPop2 0x35 /* further encoded in opf field */
351#define INS2_IMPLDEP1 0x36
352#define INS2_IMPLDEP2 0x37
353#define INS2_JMPL 0x38
354#define INS2_RETURN 0x39
355#define INS2_Tcc 0x3a
356#define INS2_FLUSH 0x3b
357#define INS2_SAVE 0x3c
358#define INS2_RESTORE 0x3d
359#define INS2_DONE_RETR 0x3e /* done, retry */
360/* undefined 0x3f */
361
362/* OP3 values for format 3 (OP = 3) */
363#define INS3_LDUW 0x00
364#define INS3_LDUB 0x01
365#define INS3_LDUH 0x02
366#define INS3_LDD 0x03
367#define INS3_STW 0x04
368#define INS3_STB 0x05
369#define INS3_STH 0x06
370#define INS3_STD 0x07
371#define INS3_LDSW 0x08
372#define INS3_LDSB 0x09
373#define INS3_LDSH 0x0a
374#define INS3_LDX 0x0b
375/* undefined 0x0c */
376#define INS3_LDSTUB 0x0d
377#define INS3_STX 0x0e
378#define INS3_SWAP 0x0f
379#define INS3_LDUWA 0x10
380#define INS3_LDUBA 0x11
381#define INS3_LDUHA 0x12
382#define INS3_LDDA 0x13
383#define INS3_STWA 0x14
384#define INS3_STBA 0x15
385#define INS3_STHA 0x16
386#define INS3_STDA 0x17
387#define INS3_LDSWA 0x18
388#define INS3_LDSBA 0x19
389#define INS3_LDSHA 0x1a
390#define INS3_LDXA 0x1b
391/* undefined 0x1c */
392#define INS3_LDSTUBA 0x1d
393#define INS3_STXA 0x1e
394#define INS3_SWAPA 0x1f
395#define INS3_LDF 0x20
396#define INS3_LDFSR 0x21 /* and LDXFSR */
397#define INS3_LDQF 0x22
398#define INS3_LDDF 0x23
399#define INS3_STF 0x24
400#define INS3_STFSR 0x25 /* and STXFSR */
401#define INS3_STQF 0x26
402#define INS3_STDF 0x27
403/* undefined 0x28 - 0x2c */
404#define INS3_PREFETCH 0x2d
405/* undefined 0x2e - 0x2f */
406#define INS3_LDFA 0x30
407/* undefined 0x31 */
408#define INS3_LDQFA 0x32
409#define INS3_LDDFA 0x33
410#define INS3_STFA 0x34
411/* undefined 0x35 */
412#define INS3_STQFA 0x36
413#define INS3_STDFA 0x37
414/* undefined 0x38 - 0x3b */
415#define INS3_CASA 0x39
416#define INS3_PREFETCHA 0x3a
417#define INS3_CASXA 0x3b
418
419/*
420 * OPF values (floating point instructions, IMPLDEP)
421 */
422/*
423 * These values are or'ed to the FPop values to get the instructions.
424 * They describe the operand type(s).
425 */
426#define INSFP_i 0x000 /* 32-bit int */
427#define INSFP_s 0x001 /* 32-bit single */
428#define INSFP_d 0x002 /* 64-bit double */
429#define INSFP_q 0x003 /* 128-bit quad */
430/* FPop1. The comments give the types for which this instruction is defined. */
431#define INSFP1_FMOV 0x000 /* s, d, q */
432#define INSFP1_FNEG 0x004 /* s, d, q */
433#define INSFP1_FABS 0x008 /* s, d, q */
434#define INSFP1_FSQRT 0x028 /* s, d, q */
435#define INSFP1_FADD 0x040 /* s, d, q */
436#define INSFP1_FSUB 0x044 /* s, d, q */
437#define INSFP1_FMUL 0x048 /* s, d, q */
438#define INSFP1_FDIV 0x04c /* s, d, q */
439#define INSFP1_FsMULd 0x068 /* s */
440#define INSFP1_FdMULq 0x06c /* d */
441#define INSFP1_FTOx 0x080 /* s, d, q */
442#define INSFP1_FxTOs 0x084 /* special: i only */
443#define INSFP1_FxTOd 0x088 /* special: i only */
444#define INSFP1_FxTOq 0x08c /* special: i only */
445#define INSFP1_FTOs 0x0c4 /* i, d, q */
446#define INSFP1_FTOd 0x0c8 /* i, s, q */
447#define INSFP1_FTOq 0x0cc /* i, s, d */
448#define INSFP1_FTOi 0x0d0 /* i, s, d */
449
450/* FPop2 */
451#define INSFP2_FMOV_CCMUL 0x40
452#define INSFP2_FMOV_CCOFFS 0x00
453/* Use the IFCC_* constants for cc. Operand types: s, d, q */
454#define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS)
455#define INSFP2_FMOV_RCMUL 0x20
456#define INSFP2_FMOV_RCOFFS 0x04
457/* Use the IRCOND_* constants for rc. Operand types: s, d, q */
458#define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS)
459#define INSFP2_FCMP 0x050 /* s, d, q */
460#define INSFP2_FCMPE 0x054 /* s, d, q */
461
462/* IMPLDEP1 for Sun UltraSparc */
463#define IIDP1_EDGE8 0x00
464#define IIDP1_EDGE8L 0x02
465#define IIDP1_EDGE16 0x04
466#define IIDP1_EDGE16L 0x06
467#define IIDP1_EDGE32 0x08
468#define IIDP1_EDGE32L 0x0a
469#define IIDP1_ARRAY8 0x10
470#define IIDP1_ARRAY16 0x12
471#define IIDP1_ARRAY32 0x14
472#define IIDP1_ALIGNADDRESS 0x18
473#define IIDP1_ALIGNADDRESS_L 0x1a
474#define IIDP1_FCMPLE16 0x20
475#define IIDP1_FCMPNE16 0x22
476#define IIDP1_FCMPLE32 0x24
477#define IIDP1_FCMPNE32 0x26
478#define IIDP1_FCMPGT16 0x28
479#define IIDP1_FCMPEQ16 0x2a
480#define IIDP1_FCMPGT32 0x2c
481#define IIDP1_FCMPEQ32 0x2e
482#define IIDP1_FMUL8x16 0x31
483#define IIDP1_FMUL8x16AU 0x33
484#define IIDP1_FMUL8X16AL 0x35
485#define IIDP1_FMUL8SUx16 0x36
486#define IIDP1_FMUL8ULx16 0x37
487#define IIDP1_FMULD8SUx16 0x38
488#define IIDP1_FMULD8ULx16 0x39
489#define IIDP1_FPACK32 0x3a
490#define IIDP1_FPACK16 0x3b
491#define IIDP1_FPACKFIX 0x3d
492#define IIDP1_PDIST 0x3e
493#define IIDP1_FALIGNDATA 0x48
494#define IIDP1_FPMERGE 0x4b
495#define IIDP1_FEXPAND 0x4d
496#define IIDP1_FPADD16 0x50
497#define IIDP1_FPADD16S 0x51
498#define IIDP1_FPADD32 0x52
499#define IIDP1_FPADD32S 0x53
500#define IIDP1_SUB16 0x54
501#define IIDP1_SUB16S 0x55
502#define IIDP1_SUB32 0x56
503#define IIDP1_SUB32S 0x57
504#define IIDP1_FZERO 0x60
505#define IIDP1_FZEROS 0x61
506#define IIDP1_FNOR 0x62
507#define IIDP1_FNORS 0x63
508#define IIDP1_FANDNOT2 0x64
509#define IIDP1_FANDNOT2S 0x65
510#define IIDP1_NOT2 0x66
511#define IIDP1_NOT2S 0x67
512#define IIDP1_FANDNOT1 0x68
513#define IIDP1_FANDNOT1S 0x69
514#define IIDP1_FNOT1 0x6a
515#define IIDP1_FNOT1S 0x6b
516#define IIDP1_FXOR 0x6c
517#define IIDP1_FXORS 0x6d
518#define IIDP1_FNAND 0x6e
519#define IIDP1_FNANDS 0x6f
520#define IIDP1_FAND 0x70
521#define IIDP1_FANDS 0x71
522#define IIDP1_FXNOR 0x72
523#define IIDP1_FXNORS 0x73
524#define IIDP1_FSRC1 0x74
525#define IIDP1_FSRC1S 0x75
526#define IIDP1_FORNOT2 0x76
527#define IIDP1_FORNOT2S 0x77
528#define IIDP1_FSRC2 0x78
529#define IIDP1_FSRC2S 0x79
530#define IIDP1_FORNOT1 0x7a
531#define IIDP1_FORNOT1S 0x7b
532#define IIDP1_FOR 0x7c
533#define IIDP1_FORS 0x7d
534#define IIDP1_FONE 0x7e
535#define IIDP1_FONES 0x7f
536#define IIDP1_SHUTDOWN 0x80
537
538/*
539 * Instruction modifiers
540 */
541/* cond values for integer ccr's */
542#define IICOND_N 0x00
543#define IICOND_E 0x01
544#define IICOND_LE 0x02
545#define IICOND_L 0x03
546#define IICOND_LEU 0x04
547#define IICOND_CS 0x05
548#define IICOND_NEG 0x06
549#define IICOND_VS 0x07
550#define IICOND_A 0x08
551#define IICOND_NE 0x09
552#define IICOND_G 0x0a
553#define IICOND_GE 0x0b
554#define IICOND_GU 0x0c
555#define IICOND_CC 0x0d
556#define IICOND_POS 0x0e
557#define IICOND_VC 0x0f
558
559/* cond values for fp ccr's */
560#define IFCOND_N 0x00
561#define IFCOND_NE 0x01
562#define IFCOND_LG 0x02
563#define IFCOND_UL 0x03
564#define IFCOND_L 0x04
565#define IFCOND_UG 0x05
566#define IFCOND_G 0x06
567#define IFCOND_U 0x07
568#define IFCOND_A 0x08
569#define IFCOND_E 0x09
570#define IFCOND_UE 0x0a
571#define IFCOND_GE 0x0b
572#define IFCOND_UGE 0x0c
573#define IFCOND_LE 0x0d
574#define IFCOND_ULE 0x0e
575#define IFCOND_O 0x0f
576
577/* rcond values for BPr, MOVr, FMOVr */
578#define IRCOND_Z 0x01
579#define IRCOND_LEZ 0x02
580#define IRCOND_LZ 0x03
581#define IRCOND_NZ 0x05
582#define IRCOND_GZ 0x06
583#define IRCOND_GEZ 0x07
584
585/* cc values for MOVcc and FMOVcc */
586#define IFCC_ICC 0x04
587#define IFCC_XCC 0x06
588/* if true, the lower 2 bits are the fcc number */
589#define IFCC_FCC(c) ((c) & 3)
590#define IFCC_GET_FCC(c) ((c) & 3)
591#define IFCC_ISFCC(c) (((c) & 4) == 0)
592
593/* cc values for BPc and Tcc */
594#define IBCC_ICC 0x00
595#define IBCC_XCC 0x02
596
597/*
598 * Integer registers
599 */
600#define IREG_G0 0x00
601#define IREG_O0 0x08
602#define IREG_L0 0x10
603#define IREQ_I0 0x18
604
605#endif /* !_MACHINE_INSTR_H_ */
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