2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
3
4/*-
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/*
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
38 *
39 * #include <powerpc/aim/trap_subr.S>
40 */
41
42/*
43 * Save/restore segment registers
44 */
45
46/*
47 * Restore SRs for a pmap
48 *
49 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache
50 */
51
52/*
53 * User SRs are loaded through a pointer to the current pmap.
54 */
55restore_usersrs:
56 GET_CPUINFO(%r28)
57 ld %r28,PC_USERSLB(%r28)
58 li %r29, 0 /* Set the counter to zero */
59
60 slbia
61 slbmfee %r31,%r29
62 clrrdi %r31,%r31,28
63 slbie %r31
641: ld %r31, 0(%r28) /* Load SLB entry pointer */
65 cmpli 0, %r31, 0 /* If NULL, stop */
66 beqlr
67
68 ld %r30, 0(%r31) /* Load SLBV */
69 ld %r31, 8(%r31) /* Load SLBE */
70 or %r31, %r31, %r29 /* Set SLBE slot */
71 slbmte %r30, %r31 /* Install SLB entry */
72
73 addi %r28, %r28, 8 /* Advance pointer */
74 addi %r29, %r29, 1
75 b 1b /* Repeat */
76
77/*
78 * Kernel SRs are loaded directly from the PCPU fields
79 */
80restore_kernsrs:
81 GET_CPUINFO(%r28)
82 addi %r28,%r28,PC_KERNSLB
83 li %r29, 0 /* Set the counter to zero */
84
85 slbia
86 slbmfee %r31,%r29
87 clrrdi %r31,%r31,28
88 slbie %r31
891: cmpli 0, %r29, USER_SLB_SLOT /* Skip the user slot */
90 beq- 2f
91
92 ld %r31, 8(%r28) /* Load SLBE */
93 cmpli 0, %r31, 0 /* If SLBE is not valid, stop */
94 beqlr
95 ld %r30, 0(%r28) /* Load SLBV */
96 slbmte %r30, %r31 /* Install SLB entry */
97
982: addi %r28, %r28, 16 /* Advance pointer */
99 addi %r29, %r29, 1
100 cmpli 0, %r29, 64 /* Repeat if we are not at the end */
101 blt 1b
102 blr
103
104/*
105 * FRAME_SETUP assumes:
106 * SPRG1 SP (1)
107 * SPRG3 trap type
108 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
109 * r28 LR
110 * r29 CR
111 * r30 scratch
112 * r31 scratch
113 * r1 kernel stack
114 * SRR0/1 as at start of trap
115 *
116 * NOTE: SPRG1 is never used while the MMU is on, making it safe to reuse
117 * in any real-mode fault handler, including those handling double faults.
118 */
119#define FRAME_SETUP(savearea) \
120/* Have to enable translation to allow access of kernel stack: */ \
121 GET_CPUINFO(%r31); \
122 mfsrr0 %r30; \
123 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
124 mfsrr1 %r30; \
125 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
126 mfsprg1 %r31; /* get saved SP (clears SPRG1) */ \
127 mfmsr %r30; \
128 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
129 mtmsr %r30; /* stack can now be accessed */ \
130 isync; \
131 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \
132 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \
133 std %r31,FRAME_1+48(%r1); /* save SP " " */ \
134 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \
135 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \
136 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \
137 GET_CPUINFO(%r2); \
138 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \
139 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
140 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
141 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
142 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
143 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \
144 std %r4, FRAME_4+48(%r1); \
145 std %r5, FRAME_5+48(%r1); \
146 std %r6, FRAME_6+48(%r1); \
147 std %r7, FRAME_7+48(%r1); \
148 std %r8, FRAME_8+48(%r1); \
149 std %r9, FRAME_9+48(%r1); \
150 std %r10, FRAME_10+48(%r1); \
151 std %r11, FRAME_11+48(%r1); \
152 std %r12, FRAME_12+48(%r1); \
153 std %r13, FRAME_13+48(%r1); \
154 std %r14, FRAME_14+48(%r1); \
155 std %r15, FRAME_15+48(%r1); \
156 std %r16, FRAME_16+48(%r1); \
157 std %r17, FRAME_17+48(%r1); \
158 std %r18, FRAME_18+48(%r1); \
159 std %r19, FRAME_19+48(%r1); \
160 std %r20, FRAME_20+48(%r1); \
161 std %r21, FRAME_21+48(%r1); \
162 std %r22, FRAME_22+48(%r1); \
163 std %r23, FRAME_23+48(%r1); \
164 std %r24, FRAME_24+48(%r1); \
165 std %r25, FRAME_25+48(%r1); \
166 std %r26, FRAME_26+48(%r1); \
167 std %r27, FRAME_27+48(%r1); \
168 std %r28, FRAME_28+48(%r1); \
169 std %r29, FRAME_29+48(%r1); \
170 std %r30, FRAME_30+48(%r1); \
171 std %r31, FRAME_31+48(%r1); \
172 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
173 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
174 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
175 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
176 mfxer %r3; \
177 mfctr %r4; \
178 mfsprg3 %r5; \
179 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \
180 std %r4, FRAME_CTR+48(1); \
181 std %r5, FRAME_EXC+48(1); \
182 std %r28,FRAME_AIM_DAR+48(1); \
183 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \
184 std %r30,FRAME_SRR0+48(1); \
185 std %r31,FRAME_SRR1+48(1); \
186 ld %r13,PC_CURTHREAD(%r2) /* set kernel curthread */
187
188#define FRAME_LEAVE(savearea) \
189/* Disable exceptions: */ \
190 mfmsr %r2; \
191 andi. %r2,%r2,~PSL_EE@l; \
192 mtmsr %r2; \
193 isync; \
194/* Now restore regs: */ \
195 ld %r2,FRAME_SRR0+48(%r1); \
196 ld %r3,FRAME_SRR1+48(%r1); \
197 ld %r4,FRAME_CTR+48(%r1); \
198 ld %r5,FRAME_XER+48(%r1); \
199 ld %r6,FRAME_LR+48(%r1); \
200 GET_CPUINFO(%r7); \
201 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
202 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
203 ld %r7,FRAME_CR+48(%r1); \
204 mtctr %r4; \
205 mtxer %r5; \
206 mtlr %r6; \
207 mtsprg2 %r7; /* save cr */ \
208 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \
209 ld %r30,FRAME_30+48(%r1); \
210 ld %r29,FRAME_29+48(%r1); \
211 ld %r28,FRAME_28+48(%r1); \
212 ld %r27,FRAME_27+48(%r1); \
213 ld %r26,FRAME_26+48(%r1); \
214 ld %r25,FRAME_25+48(%r1); \
215 ld %r24,FRAME_24+48(%r1); \
216 ld %r23,FRAME_23+48(%r1); \
217 ld %r22,FRAME_22+48(%r1); \
218 ld %r21,FRAME_21+48(%r1); \
219 ld %r20,FRAME_20+48(%r1); \
220 ld %r19,FRAME_19+48(%r1); \
221 ld %r18,FRAME_18+48(%r1); \
222 ld %r17,FRAME_17+48(%r1); \
223 ld %r16,FRAME_16+48(%r1); \
224 ld %r15,FRAME_15+48(%r1); \
225 ld %r14,FRAME_14+48(%r1); \
226 ld %r13,FRAME_13+48(%r1); \
227 ld %r12,FRAME_12+48(%r1); \
228 ld %r11,FRAME_11+48(%r1); \
229 ld %r10,FRAME_10+48(%r1); \
230 ld %r9, FRAME_9+48(%r1); \
231 ld %r8, FRAME_8+48(%r1); \
232 ld %r7, FRAME_7+48(%r1); \
233 ld %r6, FRAME_6+48(%r1); \
234 ld %r5, FRAME_5+48(%r1); \
235 ld %r4, FRAME_4+48(%r1); \
236 ld %r3, FRAME_3+48(%r1); \
237 ld %r2, FRAME_2+48(%r1); \
238 ld %r0, FRAME_0+48(%r1); \
239 ld %r1, FRAME_1+48(%r1); \
240/* Can't touch %r1 from here on */ \
241 mtsprg3 %r3; /* save r3 */ \
242/* Disable translation, machine check and recoverability: */ \
243 mfmsr %r3; \
244 andi. %r3,%r3,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
245 mtmsr %r3; \
246 isync; \
247/* Decide whether we return to user mode: */ \
248 GET_CPUINFO(%r3); \
249 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); \
250 mtcr %r3; \
251 bf 17,1f; /* branch if PSL_PR is false */ \
252/* Restore user SRs */ \
253 GET_CPUINFO(%r3); \
254 std %r27,(savearea+CPUSAVE_R27)(%r3); \
255 std %r28,(savearea+CPUSAVE_R28)(%r3); \
256 std %r29,(savearea+CPUSAVE_R29)(%r3); \
257 std %r30,(savearea+CPUSAVE_R30)(%r3); \
258 std %r31,(savearea+CPUSAVE_R31)(%r3); \
259 mflr %r27; /* preserve LR */ \
260 bl restore_usersrs; /* uses r28-r31 */ \
261 mtlr %r27; \
262 ld %r31,(savearea+CPUSAVE_R31)(%r3); \
263 ld %r30,(savearea+CPUSAVE_R30)(%r3); \
264 ld %r29,(savearea+CPUSAVE_R29)(%r3); \
265 ld %r28,(savearea+CPUSAVE_R28)(%r3); \
266 ld %r27,(savearea+CPUSAVE_R27)(%r3); \
2671: mfsprg2 %r3; /* restore cr */ \
268 mtcr %r3; \
269 GET_CPUINFO(%r3); \
270 ld %r3,(savearea+CPUSAVE_SRR0)(%r3); /* restore srr0 */ \
271 mtsrr0 %r3; \
272 GET_CPUINFO(%r3); \
273 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); /* restore srr1 */ \
274 mtsrr1 %r3; \
275 mfsprg3 %r3 /* restore r3 */
276
277#ifdef SMP
278/*
279 * Processor reset exception handler. These are typically
280 * the first instructions the processor executes after a
281 * software reset. We do this in two bits so that we are
282 * not still hanging around in the trap handling region
283 * once the MMU is turned on.
284 */
285 .globl CNAME(rstcode), CNAME(rstsize)
286CNAME(rstcode):
287 /* Explicitly set MSR[SF] */
288 mfmsr %r9
289 li %r8,1
290 insrdi %r9,%r8,1,0
291 mtmsrd %r9
292 isync
293
294 ba cpu_reset
295CNAME(rstsize) = . - CNAME(rstcode)
296
297cpu_reset:
298 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */
299 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l
300
301 lis %r3,tocbase@ha
302 ld %r2,tocbase@l(%r3)
303 lis %r3,1@l
304 bl CNAME(cpudep_ap_early_bootstrap) /* Set PCPU */
305 nop
306 lis %r3,1@l
307 bl CNAME(pmap_cpu_bootstrap) /* Turn on virtual memory */
308 nop
309 bl CNAME(cpudep_ap_bootstrap) /* Set up PCPU and stack */
310 nop
311 mr %r1,%r3 /* Use new stack */
312 bl CNAME(machdep_ap_bootstrap) /* And away! */
313 nop
314
315 /* Should not be reached */
3169:
317 b 9b
318#endif
319
320/*
321 * This code gets copied to all the trap vectors
322 * (except ISI/DSI, ALI, and the interrupts)
323 */
324
325 .globl CNAME(trapcode),CNAME(trapsize)
326CNAME(trapcode):
327 mtsprg1 %r1 /* save SP */
328 mflr %r1 /* Save the old LR in r1 */
329 mtsprg2 %r1 /* And then in SPRG2 */
330 li %r1, 0xA0 /* How to get the vector from LR */
331 bla generictrap /* LR & SPRG3 is exception # */
332CNAME(trapsize) = .-CNAME(trapcode)
333
334/*
335 * For SLB misses: do special things for the kernel
336 *
337 * Note: SPRG1 is always safe to overwrite any time the MMU is on, which is
338 * the only time this can be called.
339 */
340 .globl CNAME(slbtrap),CNAME(slbtrapsize)
341CNAME(slbtrap):
342 mtsprg1 %r1 /* save SP */
343 GET_CPUINFO(%r1)
344 std %r2,(PC_SLBSAVE+16)(%r1)
345 mfcr %r2 /* save CR */
346 std %r2,(PC_SLBSAVE+104)(%r1)
347 mfsrr1 %r2 /* test kernel mode */
348 mtcr %r2
349 bf 17,1f /* branch if PSL_PR is false */
350 /* User mode */
351 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
352 mtcr %r2
353 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */
354 mflr %r1 /* Save the old LR in r1 */
355 mtsprg2 %r1 /* And then in SPRG2 */
356 li %r1, 0x80 /* How to get the vector from LR */
357 bla generictrap /* LR & SPRG3 is exception # */
3581: mflr %r2 /* Save the old LR in r2 */
359 bla kern_slbtrap
360CNAME(slbtrapsize) = .-CNAME(slbtrap)
361
362kern_slbtrap:
363 std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */
364 std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */
365
366 /* Check if this needs to be handled as a regular trap (userseg miss) */
367 mflr %r2
368 andi. %r2,%r2,0xff80
369 cmpwi %r2,0x380
370 bne 1f
371 mfdar %r2
372 b 2f
3731: mfsrr0 %r2
3742: /* r2 now contains the fault address */
375 lis %r3,SEGMENT_MASK@highesta
376 ori %r3,%r3,SEGMENT_MASK@highera
377 sldi %r3,%r3,32
378 oris %r3,%r3,SEGMENT_MASK@ha
379 ori %r3,%r3,SEGMENT_MASK@l
380 and %r2,%r2,%r3 /* R2 = segment base address */
381 lis %r3,USER_ADDR@highesta
382 ori %r3,%r3,USER_ADDR@highera
383 sldi %r3,%r3,32
384 oris %r3,%r3,USER_ADDR@ha
385 ori %r3,%r3,USER_ADDR@l
386 cmpd %r2,%r3 /* Compare fault base to USER_ADDR */
387 bne 3f
388
389 /* User seg miss, handle as a regular trap */
390 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
391 mtcr %r2
392 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2,R3 */
393 ld %r3,(PC_SLBSAVE+24)(%r1)
394 ld %r1,(PC_SLBSAVE+136)(%r1) /* Save the old LR in r1 */
395 mtsprg2 %r1 /* And then in SPRG2 */
396 li %r1, 0x80 /* How to get the vector from LR */
397 b generictrap /* Retain old LR using b */
398
3993: /* Real kernel SLB miss */
400 std %r0,(PC_SLBSAVE+0)(%r1) /* free all volatile regs */
401 mfsprg1 %r2 /* Old R1 */
402 std %r2,(PC_SLBSAVE+8)(%r1)
403 /* R2,R3 already saved */
404 std %r4,(PC_SLBSAVE+32)(%r1)
405 std %r5,(PC_SLBSAVE+40)(%r1)
406 std %r6,(PC_SLBSAVE+48)(%r1)
407 std %r7,(PC_SLBSAVE+56)(%r1)
408 std %r8,(PC_SLBSAVE+64)(%r1)
409 std %r9,(PC_SLBSAVE+72)(%r1)
410 std %r10,(PC_SLBSAVE+80)(%r1)
411 std %r11,(PC_SLBSAVE+88)(%r1)
412 std %r12,(PC_SLBSAVE+96)(%r1)
413 /* CR already saved */
414 mfxer %r2 /* save XER */
415 std %r2,(PC_SLBSAVE+112)(%r1)
416 mflr %r2 /* save LR (SP already saved) */
417 std %r2,(PC_SLBSAVE+120)(%r1)
418 mfctr %r2 /* save CTR */
419 std %r2,(PC_SLBSAVE+128)(%r1)
420
421 /* Call handler */
422 addi %r1,%r1,PC_SLBSTACK-48+1024
423 li %r2,~15
424 and %r1,%r1,%r2
425 lis %r3,tocbase@ha
426 ld %r2,tocbase@l(%r3)
427 mflr %r3
428 andi. %r3,%r3,0xff80
429 mfdar %r4
430 mfsrr0 %r5
431 bl handle_kernel_slb_spill
432 nop
433
434 /* Save r28-31, restore r4-r12 */
435 GET_CPUINFO(%r1)
436 ld %r4,(PC_SLBSAVE+32)(%r1)
437 ld %r5,(PC_SLBSAVE+40)(%r1)
438 ld %r6,(PC_SLBSAVE+48)(%r1)
439 ld %r7,(PC_SLBSAVE+56)(%r1)
440 ld %r8,(PC_SLBSAVE+64)(%r1)
441 ld %r9,(PC_SLBSAVE+72)(%r1)
442 ld %r10,(PC_SLBSAVE+80)(%r1)
443 ld %r11,(PC_SLBSAVE+88)(%r1)
444 ld %r12,(PC_SLBSAVE+96)(%r1)
445 std %r28,(PC_SLBSAVE+64)(%r1)
446 std %r29,(PC_SLBSAVE+72)(%r1)
447 std %r30,(PC_SLBSAVE+80)(%r1)
448 std %r31,(PC_SLBSAVE+88)(%r1)
449
450 /* Restore kernel mapping */
451 bl restore_kernsrs
452
453 /* Restore remaining registers */
454 ld %r28,(PC_SLBSAVE+64)(%r1)
455 ld %r29,(PC_SLBSAVE+72)(%r1)
456 ld %r30,(PC_SLBSAVE+80)(%r1)
457 ld %r31,(PC_SLBSAVE+88)(%r1)
458
459 ld %r2,(PC_SLBSAVE+104)(%r1)
460 mtcr %r2
461 ld %r2,(PC_SLBSAVE+112)(%r1)
462 mtxer %r2
463 ld %r2,(PC_SLBSAVE+120)(%r1)
464 mtlr %r2
465 ld %r2,(PC_SLBSAVE+128)(%r1)
466 mtctr %r2
467 ld %r2,(PC_SLBSAVE+136)(%r1)
468 mtlr %r2
469
470 /* Restore r0-r3 */
471 ld %r0,(PC_SLBSAVE+0)(%r1)
472 ld %r2,(PC_SLBSAVE+16)(%r1)
473 ld %r3,(PC_SLBSAVE+24)(%r1)
474 mfsprg1 %r1
475
476 /* Back to whatever we were doing */
477 rfid
478
479/*
480 * For ALI: has to save DSISR and DAR
481 */
482 .globl CNAME(alitrap),CNAME(alisize)
483CNAME(alitrap):
484 mtsprg1 %r1 /* save SP */
485 GET_CPUINFO(%r1)
486 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
487 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
488 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
489 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
490 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
491 mfdar %r30
492 mfdsisr %r31
493 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
494 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
495 mfsprg1 %r1 /* restore SP, in case of branch */
496 mflr %r28 /* save LR */
497 mfcr %r29 /* save CR */
498
499 /* Put our exception vector in SPRG3 */
500 li %r31, EXC_ALI
501 mtsprg3 %r31
502
503 /* Test whether we already had PR set */
504 mfsrr1 %r31
505 mtcr %r31
506 bla s_trap
507CNAME(alisize) = .-CNAME(alitrap)
508
509/*
510 * Similar to the above for DSI
511 * Has to handle BAT spills
512 * and standard pagetable spills
513 */
514 .globl CNAME(dsitrap),CNAME(dsisize)
515CNAME(dsitrap):
516 mtsprg1 %r1 /* save SP */
517 GET_CPUINFO(%r1)
518 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
519 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1)
520 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
521 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
522 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
523 mfsprg1 %r1 /* restore SP */
524 mfcr %r29 /* save CR */
525 mfxer %r30 /* save XER */
526 mtsprg2 %r30 /* in SPRG2 */
527 mfsrr1 %r31 /* test kernel mode */
528 mtcr %r31
529 mflr %r28 /* save LR (SP already saved) */
530 bla disitrap
531CNAME(dsisize) = .-CNAME(dsitrap)
532
533/*
534 * Preamble code for DSI/ISI traps
535 */
536disitrap:
537 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
538 mflr %r1
539 andi. %r1,%r1,0xff00
540 mtsprg3 %r1
541
542 GET_CPUINFO(%r1)
543 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1)
544 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1)
545 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
546 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
547 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
548 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
549 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
550 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
551 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
552 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
553 mfdar %r30
554 mfdsisr %r31
555 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
556 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
557
558#ifdef KDB
559 /* Try and detect a kernel stack overflow */
560 mfsrr1 %r31
561 mtcr %r31
562 bt 17,realtrap /* branch is user mode */
563 mfsprg1 %r31 /* get old SP */
564 sub. %r30,%r31,%r30 /* SP - DAR */
565 bge 1f
566 neg %r30,%r30 /* modulo value */
5671: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */
568 bge %cr0,realtrap /* no, too far away. */
569
570 /* Now convert this DSI into a DDB trap. */
571 GET_CPUINFO(%r1)
572 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
573 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
574 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
575 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
576 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */
577 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */
578 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
579 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
580 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
581 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
582 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
583 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
584 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
585 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
586 b dbtrap
587#endif
588
589 /* XXX need stack probe here */
590realtrap:
591/* Test whether we already had PR set */
592 mfsrr1 %r1
593 mtcr %r1
594 mfsprg1 %r1 /* restore SP (might have been
595 overwritten) */
596 bf 17,k_trap /* branch if PSL_PR is false */
597 GET_CPUINFO(%r1)
598 ld %r1,PC_CURPCB(%r1)
599 mr %r27,%r28 /* Save LR, r29 */
600 mtsprg2 %r29
601 bl restore_kernsrs /* enable kernel mapping */
602 mfsprg2 %r29
603 mr %r28,%r27
604 ba s_trap
605
606/*
607 * generictrap does some standard setup for trap handling to minimize
608 * the code that need be installed in the actual vectors. It expects
609 * the following conditions.
610 *
611 * R1 - Trap vector = LR & (0xff00 | R1)
612 * SPRG1 - Original R1 contents
613 * SPRG2 - Original LR
614 */
615
616generictrap:
617 /* Save R1 for computing the exception vector */
618 mtsprg3 %r1
619
620 /* Save interesting registers */
621 GET_CPUINFO(%r1)
622 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
623 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
624 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
625 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
626 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
627 mfdar %r30
628 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
629 mfsprg1 %r1 /* restore SP, in case of branch */
630 mfsprg2 %r28 /* save LR */
631 mfcr %r29 /* save CR */
632
633 /* Compute the exception vector from the link register */
634 mfsprg3 %r31
635 ori %r31,%r31,0xff00
636 mflr %r30
637 and %r30,%r30,%r31
638 mtsprg3 %r30
639
640 /* Test whether we already had PR set */
641 mfsrr1 %r31
642 mtcr %r31
643
644s_trap:
645 bf 17,k_trap /* branch if PSL_PR is false */
646 GET_CPUINFO(%r1)
647u_trap:
648 ld %r1,PC_CURPCB(%r1)
649 mr %r27,%r28 /* Save LR, r29 */
650 mtsprg2 %r29
651 bl restore_kernsrs /* enable kernel mapping */
652 mfsprg2 %r29
653 mr %r28,%r27
654
655/*
656 * Now the common trap catching code.
657 */
658k_trap:
659 FRAME_SETUP(PC_TEMPSAVE)
660/* Call C interrupt dispatcher: */
661trapagain:
662 lis %r3,tocbase@ha
663 ld %r2,tocbase@l(%r3)
664 addi %r3,%r1,48
665 bl CNAME(powerpc_interrupt)
666 nop
667
668 .globl CNAME(trapexit) /* backtrace code sentinel */
669CNAME(trapexit):
670/* Disable interrupts: */
671 mfmsr %r3
672 andi. %r3,%r3,~PSL_EE@l
673 mtmsr %r3
674 isync
675/* Test AST pending: */
676 ld %r5,FRAME_SRR1+48(%r1)
677 mtcr %r5
678 bf 17,1f /* branch if PSL_PR is false */
679
680 GET_CPUINFO(%r3) /* get per-CPU pointer */
681 lwz %r4, TD_FLAGS(%r13) /* get thread flags value */
682 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
683 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
684 and. %r4,%r4,%r5
685 beq 1f
686 mfmsr %r3 /* re-enable interrupts */
687 ori %r3,%r3,PSL_EE@l
688 mtmsr %r3
689 isync
690 lis %r3,tocbase@ha
691 ld %r2,tocbase@l(%r3)
692 addi %r3,%r1,48
693 bl CNAME(ast)
694 nop
695 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */
696CNAME(asttrapexit):
697 b trapexit /* test ast ret value ? */
6981:
699 FRAME_LEAVE(PC_TEMPSAVE)
700 rfid
701
702#if defined(KDB)
703/*
704 * Deliberate entry to dbtrap
705 */
| 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
3
4/*-
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/*
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
38 *
39 * #include <powerpc/aim/trap_subr.S>
40 */
41
42/*
43 * Save/restore segment registers
44 */
45
46/*
47 * Restore SRs for a pmap
48 *
49 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache
50 */
51
52/*
53 * User SRs are loaded through a pointer to the current pmap.
54 */
55restore_usersrs:
56 GET_CPUINFO(%r28)
57 ld %r28,PC_USERSLB(%r28)
58 li %r29, 0 /* Set the counter to zero */
59
60 slbia
61 slbmfee %r31,%r29
62 clrrdi %r31,%r31,28
63 slbie %r31
641: ld %r31, 0(%r28) /* Load SLB entry pointer */
65 cmpli 0, %r31, 0 /* If NULL, stop */
66 beqlr
67
68 ld %r30, 0(%r31) /* Load SLBV */
69 ld %r31, 8(%r31) /* Load SLBE */
70 or %r31, %r31, %r29 /* Set SLBE slot */
71 slbmte %r30, %r31 /* Install SLB entry */
72
73 addi %r28, %r28, 8 /* Advance pointer */
74 addi %r29, %r29, 1
75 b 1b /* Repeat */
76
77/*
78 * Kernel SRs are loaded directly from the PCPU fields
79 */
80restore_kernsrs:
81 GET_CPUINFO(%r28)
82 addi %r28,%r28,PC_KERNSLB
83 li %r29, 0 /* Set the counter to zero */
84
85 slbia
86 slbmfee %r31,%r29
87 clrrdi %r31,%r31,28
88 slbie %r31
891: cmpli 0, %r29, USER_SLB_SLOT /* Skip the user slot */
90 beq- 2f
91
92 ld %r31, 8(%r28) /* Load SLBE */
93 cmpli 0, %r31, 0 /* If SLBE is not valid, stop */
94 beqlr
95 ld %r30, 0(%r28) /* Load SLBV */
96 slbmte %r30, %r31 /* Install SLB entry */
97
982: addi %r28, %r28, 16 /* Advance pointer */
99 addi %r29, %r29, 1
100 cmpli 0, %r29, 64 /* Repeat if we are not at the end */
101 blt 1b
102 blr
103
104/*
105 * FRAME_SETUP assumes:
106 * SPRG1 SP (1)
107 * SPRG3 trap type
108 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
109 * r28 LR
110 * r29 CR
111 * r30 scratch
112 * r31 scratch
113 * r1 kernel stack
114 * SRR0/1 as at start of trap
115 *
116 * NOTE: SPRG1 is never used while the MMU is on, making it safe to reuse
117 * in any real-mode fault handler, including those handling double faults.
118 */
119#define FRAME_SETUP(savearea) \
120/* Have to enable translation to allow access of kernel stack: */ \
121 GET_CPUINFO(%r31); \
122 mfsrr0 %r30; \
123 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
124 mfsrr1 %r30; \
125 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
126 mfsprg1 %r31; /* get saved SP (clears SPRG1) */ \
127 mfmsr %r30; \
128 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
129 mtmsr %r30; /* stack can now be accessed */ \
130 isync; \
131 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \
132 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \
133 std %r31,FRAME_1+48(%r1); /* save SP " " */ \
134 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \
135 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \
136 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \
137 GET_CPUINFO(%r2); \
138 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \
139 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
140 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
141 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
142 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
143 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \
144 std %r4, FRAME_4+48(%r1); \
145 std %r5, FRAME_5+48(%r1); \
146 std %r6, FRAME_6+48(%r1); \
147 std %r7, FRAME_7+48(%r1); \
148 std %r8, FRAME_8+48(%r1); \
149 std %r9, FRAME_9+48(%r1); \
150 std %r10, FRAME_10+48(%r1); \
151 std %r11, FRAME_11+48(%r1); \
152 std %r12, FRAME_12+48(%r1); \
153 std %r13, FRAME_13+48(%r1); \
154 std %r14, FRAME_14+48(%r1); \
155 std %r15, FRAME_15+48(%r1); \
156 std %r16, FRAME_16+48(%r1); \
157 std %r17, FRAME_17+48(%r1); \
158 std %r18, FRAME_18+48(%r1); \
159 std %r19, FRAME_19+48(%r1); \
160 std %r20, FRAME_20+48(%r1); \
161 std %r21, FRAME_21+48(%r1); \
162 std %r22, FRAME_22+48(%r1); \
163 std %r23, FRAME_23+48(%r1); \
164 std %r24, FRAME_24+48(%r1); \
165 std %r25, FRAME_25+48(%r1); \
166 std %r26, FRAME_26+48(%r1); \
167 std %r27, FRAME_27+48(%r1); \
168 std %r28, FRAME_28+48(%r1); \
169 std %r29, FRAME_29+48(%r1); \
170 std %r30, FRAME_30+48(%r1); \
171 std %r31, FRAME_31+48(%r1); \
172 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
173 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
174 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
175 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
176 mfxer %r3; \
177 mfctr %r4; \
178 mfsprg3 %r5; \
179 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \
180 std %r4, FRAME_CTR+48(1); \
181 std %r5, FRAME_EXC+48(1); \
182 std %r28,FRAME_AIM_DAR+48(1); \
183 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \
184 std %r30,FRAME_SRR0+48(1); \
185 std %r31,FRAME_SRR1+48(1); \
186 ld %r13,PC_CURTHREAD(%r2) /* set kernel curthread */
187
188#define FRAME_LEAVE(savearea) \
189/* Disable exceptions: */ \
190 mfmsr %r2; \
191 andi. %r2,%r2,~PSL_EE@l; \
192 mtmsr %r2; \
193 isync; \
194/* Now restore regs: */ \
195 ld %r2,FRAME_SRR0+48(%r1); \
196 ld %r3,FRAME_SRR1+48(%r1); \
197 ld %r4,FRAME_CTR+48(%r1); \
198 ld %r5,FRAME_XER+48(%r1); \
199 ld %r6,FRAME_LR+48(%r1); \
200 GET_CPUINFO(%r7); \
201 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
202 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
203 ld %r7,FRAME_CR+48(%r1); \
204 mtctr %r4; \
205 mtxer %r5; \
206 mtlr %r6; \
207 mtsprg2 %r7; /* save cr */ \
208 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \
209 ld %r30,FRAME_30+48(%r1); \
210 ld %r29,FRAME_29+48(%r1); \
211 ld %r28,FRAME_28+48(%r1); \
212 ld %r27,FRAME_27+48(%r1); \
213 ld %r26,FRAME_26+48(%r1); \
214 ld %r25,FRAME_25+48(%r1); \
215 ld %r24,FRAME_24+48(%r1); \
216 ld %r23,FRAME_23+48(%r1); \
217 ld %r22,FRAME_22+48(%r1); \
218 ld %r21,FRAME_21+48(%r1); \
219 ld %r20,FRAME_20+48(%r1); \
220 ld %r19,FRAME_19+48(%r1); \
221 ld %r18,FRAME_18+48(%r1); \
222 ld %r17,FRAME_17+48(%r1); \
223 ld %r16,FRAME_16+48(%r1); \
224 ld %r15,FRAME_15+48(%r1); \
225 ld %r14,FRAME_14+48(%r1); \
226 ld %r13,FRAME_13+48(%r1); \
227 ld %r12,FRAME_12+48(%r1); \
228 ld %r11,FRAME_11+48(%r1); \
229 ld %r10,FRAME_10+48(%r1); \
230 ld %r9, FRAME_9+48(%r1); \
231 ld %r8, FRAME_8+48(%r1); \
232 ld %r7, FRAME_7+48(%r1); \
233 ld %r6, FRAME_6+48(%r1); \
234 ld %r5, FRAME_5+48(%r1); \
235 ld %r4, FRAME_4+48(%r1); \
236 ld %r3, FRAME_3+48(%r1); \
237 ld %r2, FRAME_2+48(%r1); \
238 ld %r0, FRAME_0+48(%r1); \
239 ld %r1, FRAME_1+48(%r1); \
240/* Can't touch %r1 from here on */ \
241 mtsprg3 %r3; /* save r3 */ \
242/* Disable translation, machine check and recoverability: */ \
243 mfmsr %r3; \
244 andi. %r3,%r3,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
245 mtmsr %r3; \
246 isync; \
247/* Decide whether we return to user mode: */ \
248 GET_CPUINFO(%r3); \
249 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); \
250 mtcr %r3; \
251 bf 17,1f; /* branch if PSL_PR is false */ \
252/* Restore user SRs */ \
253 GET_CPUINFO(%r3); \
254 std %r27,(savearea+CPUSAVE_R27)(%r3); \
255 std %r28,(savearea+CPUSAVE_R28)(%r3); \
256 std %r29,(savearea+CPUSAVE_R29)(%r3); \
257 std %r30,(savearea+CPUSAVE_R30)(%r3); \
258 std %r31,(savearea+CPUSAVE_R31)(%r3); \
259 mflr %r27; /* preserve LR */ \
260 bl restore_usersrs; /* uses r28-r31 */ \
261 mtlr %r27; \
262 ld %r31,(savearea+CPUSAVE_R31)(%r3); \
263 ld %r30,(savearea+CPUSAVE_R30)(%r3); \
264 ld %r29,(savearea+CPUSAVE_R29)(%r3); \
265 ld %r28,(savearea+CPUSAVE_R28)(%r3); \
266 ld %r27,(savearea+CPUSAVE_R27)(%r3); \
2671: mfsprg2 %r3; /* restore cr */ \
268 mtcr %r3; \
269 GET_CPUINFO(%r3); \
270 ld %r3,(savearea+CPUSAVE_SRR0)(%r3); /* restore srr0 */ \
271 mtsrr0 %r3; \
272 GET_CPUINFO(%r3); \
273 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); /* restore srr1 */ \
274 mtsrr1 %r3; \
275 mfsprg3 %r3 /* restore r3 */
276
277#ifdef SMP
278/*
279 * Processor reset exception handler. These are typically
280 * the first instructions the processor executes after a
281 * software reset. We do this in two bits so that we are
282 * not still hanging around in the trap handling region
283 * once the MMU is turned on.
284 */
285 .globl CNAME(rstcode), CNAME(rstsize)
286CNAME(rstcode):
287 /* Explicitly set MSR[SF] */
288 mfmsr %r9
289 li %r8,1
290 insrdi %r9,%r8,1,0
291 mtmsrd %r9
292 isync
293
294 ba cpu_reset
295CNAME(rstsize) = . - CNAME(rstcode)
296
297cpu_reset:
298 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */
299 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l
300
301 lis %r3,tocbase@ha
302 ld %r2,tocbase@l(%r3)
303 lis %r3,1@l
304 bl CNAME(cpudep_ap_early_bootstrap) /* Set PCPU */
305 nop
306 lis %r3,1@l
307 bl CNAME(pmap_cpu_bootstrap) /* Turn on virtual memory */
308 nop
309 bl CNAME(cpudep_ap_bootstrap) /* Set up PCPU and stack */
310 nop
311 mr %r1,%r3 /* Use new stack */
312 bl CNAME(machdep_ap_bootstrap) /* And away! */
313 nop
314
315 /* Should not be reached */
3169:
317 b 9b
318#endif
319
320/*
321 * This code gets copied to all the trap vectors
322 * (except ISI/DSI, ALI, and the interrupts)
323 */
324
325 .globl CNAME(trapcode),CNAME(trapsize)
326CNAME(trapcode):
327 mtsprg1 %r1 /* save SP */
328 mflr %r1 /* Save the old LR in r1 */
329 mtsprg2 %r1 /* And then in SPRG2 */
330 li %r1, 0xA0 /* How to get the vector from LR */
331 bla generictrap /* LR & SPRG3 is exception # */
332CNAME(trapsize) = .-CNAME(trapcode)
333
334/*
335 * For SLB misses: do special things for the kernel
336 *
337 * Note: SPRG1 is always safe to overwrite any time the MMU is on, which is
338 * the only time this can be called.
339 */
340 .globl CNAME(slbtrap),CNAME(slbtrapsize)
341CNAME(slbtrap):
342 mtsprg1 %r1 /* save SP */
343 GET_CPUINFO(%r1)
344 std %r2,(PC_SLBSAVE+16)(%r1)
345 mfcr %r2 /* save CR */
346 std %r2,(PC_SLBSAVE+104)(%r1)
347 mfsrr1 %r2 /* test kernel mode */
348 mtcr %r2
349 bf 17,1f /* branch if PSL_PR is false */
350 /* User mode */
351 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
352 mtcr %r2
353 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */
354 mflr %r1 /* Save the old LR in r1 */
355 mtsprg2 %r1 /* And then in SPRG2 */
356 li %r1, 0x80 /* How to get the vector from LR */
357 bla generictrap /* LR & SPRG3 is exception # */
3581: mflr %r2 /* Save the old LR in r2 */
359 bla kern_slbtrap
360CNAME(slbtrapsize) = .-CNAME(slbtrap)
361
362kern_slbtrap:
363 std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */
364 std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */
365
366 /* Check if this needs to be handled as a regular trap (userseg miss) */
367 mflr %r2
368 andi. %r2,%r2,0xff80
369 cmpwi %r2,0x380
370 bne 1f
371 mfdar %r2
372 b 2f
3731: mfsrr0 %r2
3742: /* r2 now contains the fault address */
375 lis %r3,SEGMENT_MASK@highesta
376 ori %r3,%r3,SEGMENT_MASK@highera
377 sldi %r3,%r3,32
378 oris %r3,%r3,SEGMENT_MASK@ha
379 ori %r3,%r3,SEGMENT_MASK@l
380 and %r2,%r2,%r3 /* R2 = segment base address */
381 lis %r3,USER_ADDR@highesta
382 ori %r3,%r3,USER_ADDR@highera
383 sldi %r3,%r3,32
384 oris %r3,%r3,USER_ADDR@ha
385 ori %r3,%r3,USER_ADDR@l
386 cmpd %r2,%r3 /* Compare fault base to USER_ADDR */
387 bne 3f
388
389 /* User seg miss, handle as a regular trap */
390 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
391 mtcr %r2
392 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2,R3 */
393 ld %r3,(PC_SLBSAVE+24)(%r1)
394 ld %r1,(PC_SLBSAVE+136)(%r1) /* Save the old LR in r1 */
395 mtsprg2 %r1 /* And then in SPRG2 */
396 li %r1, 0x80 /* How to get the vector from LR */
397 b generictrap /* Retain old LR using b */
398
3993: /* Real kernel SLB miss */
400 std %r0,(PC_SLBSAVE+0)(%r1) /* free all volatile regs */
401 mfsprg1 %r2 /* Old R1 */
402 std %r2,(PC_SLBSAVE+8)(%r1)
403 /* R2,R3 already saved */
404 std %r4,(PC_SLBSAVE+32)(%r1)
405 std %r5,(PC_SLBSAVE+40)(%r1)
406 std %r6,(PC_SLBSAVE+48)(%r1)
407 std %r7,(PC_SLBSAVE+56)(%r1)
408 std %r8,(PC_SLBSAVE+64)(%r1)
409 std %r9,(PC_SLBSAVE+72)(%r1)
410 std %r10,(PC_SLBSAVE+80)(%r1)
411 std %r11,(PC_SLBSAVE+88)(%r1)
412 std %r12,(PC_SLBSAVE+96)(%r1)
413 /* CR already saved */
414 mfxer %r2 /* save XER */
415 std %r2,(PC_SLBSAVE+112)(%r1)
416 mflr %r2 /* save LR (SP already saved) */
417 std %r2,(PC_SLBSAVE+120)(%r1)
418 mfctr %r2 /* save CTR */
419 std %r2,(PC_SLBSAVE+128)(%r1)
420
421 /* Call handler */
422 addi %r1,%r1,PC_SLBSTACK-48+1024
423 li %r2,~15
424 and %r1,%r1,%r2
425 lis %r3,tocbase@ha
426 ld %r2,tocbase@l(%r3)
427 mflr %r3
428 andi. %r3,%r3,0xff80
429 mfdar %r4
430 mfsrr0 %r5
431 bl handle_kernel_slb_spill
432 nop
433
434 /* Save r28-31, restore r4-r12 */
435 GET_CPUINFO(%r1)
436 ld %r4,(PC_SLBSAVE+32)(%r1)
437 ld %r5,(PC_SLBSAVE+40)(%r1)
438 ld %r6,(PC_SLBSAVE+48)(%r1)
439 ld %r7,(PC_SLBSAVE+56)(%r1)
440 ld %r8,(PC_SLBSAVE+64)(%r1)
441 ld %r9,(PC_SLBSAVE+72)(%r1)
442 ld %r10,(PC_SLBSAVE+80)(%r1)
443 ld %r11,(PC_SLBSAVE+88)(%r1)
444 ld %r12,(PC_SLBSAVE+96)(%r1)
445 std %r28,(PC_SLBSAVE+64)(%r1)
446 std %r29,(PC_SLBSAVE+72)(%r1)
447 std %r30,(PC_SLBSAVE+80)(%r1)
448 std %r31,(PC_SLBSAVE+88)(%r1)
449
450 /* Restore kernel mapping */
451 bl restore_kernsrs
452
453 /* Restore remaining registers */
454 ld %r28,(PC_SLBSAVE+64)(%r1)
455 ld %r29,(PC_SLBSAVE+72)(%r1)
456 ld %r30,(PC_SLBSAVE+80)(%r1)
457 ld %r31,(PC_SLBSAVE+88)(%r1)
458
459 ld %r2,(PC_SLBSAVE+104)(%r1)
460 mtcr %r2
461 ld %r2,(PC_SLBSAVE+112)(%r1)
462 mtxer %r2
463 ld %r2,(PC_SLBSAVE+120)(%r1)
464 mtlr %r2
465 ld %r2,(PC_SLBSAVE+128)(%r1)
466 mtctr %r2
467 ld %r2,(PC_SLBSAVE+136)(%r1)
468 mtlr %r2
469
470 /* Restore r0-r3 */
471 ld %r0,(PC_SLBSAVE+0)(%r1)
472 ld %r2,(PC_SLBSAVE+16)(%r1)
473 ld %r3,(PC_SLBSAVE+24)(%r1)
474 mfsprg1 %r1
475
476 /* Back to whatever we were doing */
477 rfid
478
479/*
480 * For ALI: has to save DSISR and DAR
481 */
482 .globl CNAME(alitrap),CNAME(alisize)
483CNAME(alitrap):
484 mtsprg1 %r1 /* save SP */
485 GET_CPUINFO(%r1)
486 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
487 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
488 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
489 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
490 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
491 mfdar %r30
492 mfdsisr %r31
493 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
494 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
495 mfsprg1 %r1 /* restore SP, in case of branch */
496 mflr %r28 /* save LR */
497 mfcr %r29 /* save CR */
498
499 /* Put our exception vector in SPRG3 */
500 li %r31, EXC_ALI
501 mtsprg3 %r31
502
503 /* Test whether we already had PR set */
504 mfsrr1 %r31
505 mtcr %r31
506 bla s_trap
507CNAME(alisize) = .-CNAME(alitrap)
508
509/*
510 * Similar to the above for DSI
511 * Has to handle BAT spills
512 * and standard pagetable spills
513 */
514 .globl CNAME(dsitrap),CNAME(dsisize)
515CNAME(dsitrap):
516 mtsprg1 %r1 /* save SP */
517 GET_CPUINFO(%r1)
518 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
519 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1)
520 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
521 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
522 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
523 mfsprg1 %r1 /* restore SP */
524 mfcr %r29 /* save CR */
525 mfxer %r30 /* save XER */
526 mtsprg2 %r30 /* in SPRG2 */
527 mfsrr1 %r31 /* test kernel mode */
528 mtcr %r31
529 mflr %r28 /* save LR (SP already saved) */
530 bla disitrap
531CNAME(dsisize) = .-CNAME(dsitrap)
532
533/*
534 * Preamble code for DSI/ISI traps
535 */
536disitrap:
537 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
538 mflr %r1
539 andi. %r1,%r1,0xff00
540 mtsprg3 %r1
541
542 GET_CPUINFO(%r1)
543 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1)
544 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1)
545 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
546 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
547 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
548 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
549 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
550 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
551 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
552 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
553 mfdar %r30
554 mfdsisr %r31
555 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
556 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
557
558#ifdef KDB
559 /* Try and detect a kernel stack overflow */
560 mfsrr1 %r31
561 mtcr %r31
562 bt 17,realtrap /* branch is user mode */
563 mfsprg1 %r31 /* get old SP */
564 sub. %r30,%r31,%r30 /* SP - DAR */
565 bge 1f
566 neg %r30,%r30 /* modulo value */
5671: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */
568 bge %cr0,realtrap /* no, too far away. */
569
570 /* Now convert this DSI into a DDB trap. */
571 GET_CPUINFO(%r1)
572 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
573 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
574 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
575 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
576 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */
577 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */
578 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
579 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
580 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
581 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
582 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
583 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
584 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
585 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
586 b dbtrap
587#endif
588
589 /* XXX need stack probe here */
590realtrap:
591/* Test whether we already had PR set */
592 mfsrr1 %r1
593 mtcr %r1
594 mfsprg1 %r1 /* restore SP (might have been
595 overwritten) */
596 bf 17,k_trap /* branch if PSL_PR is false */
597 GET_CPUINFO(%r1)
598 ld %r1,PC_CURPCB(%r1)
599 mr %r27,%r28 /* Save LR, r29 */
600 mtsprg2 %r29
601 bl restore_kernsrs /* enable kernel mapping */
602 mfsprg2 %r29
603 mr %r28,%r27
604 ba s_trap
605
606/*
607 * generictrap does some standard setup for trap handling to minimize
608 * the code that need be installed in the actual vectors. It expects
609 * the following conditions.
610 *
611 * R1 - Trap vector = LR & (0xff00 | R1)
612 * SPRG1 - Original R1 contents
613 * SPRG2 - Original LR
614 */
615
616generictrap:
617 /* Save R1 for computing the exception vector */
618 mtsprg3 %r1
619
620 /* Save interesting registers */
621 GET_CPUINFO(%r1)
622 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
623 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
624 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
625 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
626 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
627 mfdar %r30
628 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
629 mfsprg1 %r1 /* restore SP, in case of branch */
630 mfsprg2 %r28 /* save LR */
631 mfcr %r29 /* save CR */
632
633 /* Compute the exception vector from the link register */
634 mfsprg3 %r31
635 ori %r31,%r31,0xff00
636 mflr %r30
637 and %r30,%r30,%r31
638 mtsprg3 %r30
639
640 /* Test whether we already had PR set */
641 mfsrr1 %r31
642 mtcr %r31
643
644s_trap:
645 bf 17,k_trap /* branch if PSL_PR is false */
646 GET_CPUINFO(%r1)
647u_trap:
648 ld %r1,PC_CURPCB(%r1)
649 mr %r27,%r28 /* Save LR, r29 */
650 mtsprg2 %r29
651 bl restore_kernsrs /* enable kernel mapping */
652 mfsprg2 %r29
653 mr %r28,%r27
654
655/*
656 * Now the common trap catching code.
657 */
658k_trap:
659 FRAME_SETUP(PC_TEMPSAVE)
660/* Call C interrupt dispatcher: */
661trapagain:
662 lis %r3,tocbase@ha
663 ld %r2,tocbase@l(%r3)
664 addi %r3,%r1,48
665 bl CNAME(powerpc_interrupt)
666 nop
667
668 .globl CNAME(trapexit) /* backtrace code sentinel */
669CNAME(trapexit):
670/* Disable interrupts: */
671 mfmsr %r3
672 andi. %r3,%r3,~PSL_EE@l
673 mtmsr %r3
674 isync
675/* Test AST pending: */
676 ld %r5,FRAME_SRR1+48(%r1)
677 mtcr %r5
678 bf 17,1f /* branch if PSL_PR is false */
679
680 GET_CPUINFO(%r3) /* get per-CPU pointer */
681 lwz %r4, TD_FLAGS(%r13) /* get thread flags value */
682 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
683 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
684 and. %r4,%r4,%r5
685 beq 1f
686 mfmsr %r3 /* re-enable interrupts */
687 ori %r3,%r3,PSL_EE@l
688 mtmsr %r3
689 isync
690 lis %r3,tocbase@ha
691 ld %r2,tocbase@l(%r3)
692 addi %r3,%r1,48
693 bl CNAME(ast)
694 nop
695 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */
696CNAME(asttrapexit):
697 b trapexit /* test ast ret value ? */
6981:
699 FRAME_LEAVE(PC_TEMPSAVE)
700 rfid
701
702#if defined(KDB)
703/*
704 * Deliberate entry to dbtrap
705 */
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