| cpu.h (178172) | cpu.h (202031) |
|---|---|
| 1/* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. --- 27 unchanged lines hidden (view full) --- 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 * JNPR: cpu.h,v 1.9.2.2 2007/09/10 08:23:46 girish | 1/* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. --- 27 unchanged lines hidden (view full) --- 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 * JNPR: cpu.h,v 1.9.2.2 2007/09/10 08:23:46 girish |
| 44 * $FreeBSD: head/sys/mips/include/cpu.h 178172 2008-04-13 07:27:37Z imp $ | 44 * $FreeBSD: head/sys/mips/include/cpu.h 202031 2010-01-10 19:50:24Z imp $ |
| 45 */ 46 47#ifndef _MACHINE_CPU_H_ 48#define _MACHINE_CPU_H_ 49 50#include <machine/psl.h> 51#include <machine/endian.h> 52 53#define MIPS_CACHED_MEMORY_ADDR 0x80000000 54#define MIPS_UNCACHED_MEMORY_ADDR 0xa0000000 55#define MIPS_MAX_MEM_ADDR 0xbe000000 56#define MIPS_RESERVED_ADDR 0xbfc80000 57 58#define MIPS_KSEG0_LARGEST_PHYS 0x20000000 | 45 */ 46 47#ifndef _MACHINE_CPU_H_ 48#define _MACHINE_CPU_H_ 49 50#include <machine/psl.h> 51#include <machine/endian.h> 52 53#define MIPS_CACHED_MEMORY_ADDR 0x80000000 54#define MIPS_UNCACHED_MEMORY_ADDR 0xa0000000 55#define MIPS_MAX_MEM_ADDR 0xbe000000 56#define MIPS_RESERVED_ADDR 0xbfc80000 57 58#define MIPS_KSEG0_LARGEST_PHYS 0x20000000 |
| 59#define MIPS_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 60#define MIPS_PHYS_TO_CACHED(x) ((unsigned)(x) | MIPS_CACHED_MEMORY_ADDR) 61#define MIPS_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 62#define MIPS_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MIPS_UNCACHED_MEMORY_ADDR) | 59#define MIPS_CACHED_TO_PHYS(x) ((uintptr_t)(x) & 0x1fffffff) 60#define MIPS_PHYS_TO_CACHED(x) ((uintptr_t)(x) | MIPS_CACHED_MEMORY_ADDR) 61#define MIPS_UNCACHED_TO_PHYS(x) ((uintptr_t)(x) & 0x1fffffff) 62#define MIPS_PHYS_TO_UNCACHED(x) ((uintptr_t)(x) | MIPS_UNCACHED_MEMORY_ADDR) |
| 63 64#define MIPS_PHYS_MASK (0x1fffffff) 65#define MIPS_PA_2_K1VA(x) (MIPS_KSEG1_START | ((x) & MIPS_PHYS_MASK)) 66 | 63 64#define MIPS_PHYS_MASK (0x1fffffff) 65#define MIPS_PA_2_K1VA(x) (MIPS_KSEG1_START | ((x) & MIPS_PHYS_MASK)) 66 |
| 67#define MIPS_VA_TO_CINDEX(x) ((unsigned)(x) & 0xffffff | MIPS_CACHED_MEMORY_ADDR) | 67#define MIPS_VA_TO_CINDEX(x) ((uintptr_t)(x) & 0xffffff | MIPS_CACHED_MEMORY_ADDR) |
| 68#define MIPS_CACHED_TO_UNCACHED(x) (MIPS_PHYS_TO_UNCACHED(MIPS_CACHED_TO_PHYS(x))) 69 | 68#define MIPS_CACHED_TO_UNCACHED(x) (MIPS_PHYS_TO_UNCACHED(MIPS_CACHED_TO_PHYS(x))) 69 |
| 70#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START) 71#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START) 72#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 73#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) | 70#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 71#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 72#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 73#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) |
| 74 | 74 |
| 75#define MIPS_IS_KSEG0_ADDR(x) \ 76 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ 77 ((vm_offset_t)(x) <= MIPS_KSEG0_END)) 78#define MIPS_IS_KSEG1_ADDR(x) \ 79 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ 80 ((vm_offset_t)(x) <= MIPS_KSEG1_END)) 81#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ 82 MIPS_IS_KSEG1_ADDR(x)) 83 |
|
| 75/* 76 * Status register. 77 */ 78#define SR_COP_USABILITY 0xf0000000 79#define SR_COP_0_BIT 0x10000000 80#define SR_COP_1_BIT 0x20000000 81#define SR_COP_2_BIT 0x40000000 82#define SR_RP 0x08000000 --- 66 unchanged lines hidden (view full) --- 149#define CR_INT_UART CR_INT_1 150#define CR_INT_IPI CR_INT_2 151#define CR_INT_CLOCK CR_INT_5 152 153/* 154 * The bits in the CONFIG register 155 */ 156#define CFG_K0_UNCACHED 2 | 84/* 85 * Status register. 86 */ 87#define SR_COP_USABILITY 0xf0000000 88#define SR_COP_0_BIT 0x10000000 89#define SR_COP_1_BIT 0x20000000 90#define SR_COP_2_BIT 0x40000000 91#define SR_RP 0x08000000 --- 66 unchanged lines hidden (view full) --- 158#define CR_INT_UART CR_INT_1 159#define CR_INT_IPI CR_INT_2 160#define CR_INT_CLOCK CR_INT_5 161 162/* 163 * The bits in the CONFIG register 164 */ 165#define CFG_K0_UNCACHED 2 |
| 166#if defined(CPU_SB1) 167#define CFG_K0_COHERENT 5 /* cacheable coherent */ 168#else |
|
| 157#define CFG_K0_CACHED 3 | 169#define CFG_K0_CACHED 3 |
| 170#endif |
|
| 158 159/* 160 * The bits in the context register. 161 */ 162#define CNTXT_PTE_BASE 0xff800000 163#define CNTXT_BAD_VPN2 0x007ffff0 164 165/* --- 399 unchanged lines hidden --- | 171 172/* 173 * The bits in the context register. 174 */ 175#define CNTXT_PTE_BASE 0xff800000 176#define CNTXT_BAD_VPN2 0x007ffff0 177 178/* --- 399 unchanged lines hidden --- |