| cache_mipsNN.h (178172) | cache_mipsNN.h (202031) |
|---|---|
| 1/* $NetBSD: cache_mipsNN.h,v 1.4 2003/02/17 11:35:02 simonb Exp $ */ 2 3/* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * --- 20 unchanged lines hidden (view full) --- 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * | 1/* $NetBSD: cache_mipsNN.h,v 1.4 2003/02/17 11:35:02 simonb Exp $ */ 2 3/* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * --- 20 unchanged lines hidden (view full) --- 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * |
| 37 * $FreeBSD: head/sys/mips/include/cache_mipsNN.h 178172 2008-04-13 07:27:37Z imp $ | 37 * $FreeBSD: head/sys/mips/include/cache_mipsNN.h 202031 2010-01-10 19:50:24Z imp $ |
| 38 */ | 38 */ |
| 39#ifndef _MACHINE_CACHE_MIPSNN_H_ 40#define _MACHINE_CACHE_MIPSNN_H_ |
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| 39 40void mipsNN_cache_init(struct mips_cpuinfo *); 41 42void mipsNN_icache_sync_all_16(void); 43void mipsNN_icache_sync_all_32(void); 44void mipsNN_icache_sync_range_16(vm_offset_t, vm_size_t); 45void mipsNN_icache_sync_range_32(vm_offset_t, vm_size_t); 46void mipsNN_icache_sync_range_index_16(vm_offset_t, vm_size_t); --- 13 unchanged lines hidden (view full) --- 60void mipsNN_icache_sync_range_128(vm_offset_t, vm_size_t); 61void mipsNN_icache_sync_range_index_128(vm_offset_t, vm_size_t); 62void mipsNN_pdcache_wbinv_all_128(void); 63void mipsNN_pdcache_wbinv_range_128(vm_offset_t, vm_size_t); 64void mipsNN_pdcache_wbinv_range_index_128(vm_offset_t, vm_size_t); 65void mipsNN_pdcache_inv_range_128(vm_offset_t, vm_size_t); 66void mipsNN_pdcache_wb_range_128(vm_offset_t, vm_size_t); 67#endif | 41 42void mipsNN_cache_init(struct mips_cpuinfo *); 43 44void mipsNN_icache_sync_all_16(void); 45void mipsNN_icache_sync_all_32(void); 46void mipsNN_icache_sync_range_16(vm_offset_t, vm_size_t); 47void mipsNN_icache_sync_range_32(vm_offset_t, vm_size_t); 48void mipsNN_icache_sync_range_index_16(vm_offset_t, vm_size_t); --- 13 unchanged lines hidden (view full) --- 62void mipsNN_icache_sync_range_128(vm_offset_t, vm_size_t); 63void mipsNN_icache_sync_range_index_128(vm_offset_t, vm_size_t); 64void mipsNN_pdcache_wbinv_all_128(void); 65void mipsNN_pdcache_wbinv_range_128(vm_offset_t, vm_size_t); 66void mipsNN_pdcache_wbinv_range_index_128(vm_offset_t, vm_size_t); 67void mipsNN_pdcache_inv_range_128(vm_offset_t, vm_size_t); 68void mipsNN_pdcache_wb_range_128(vm_offset_t, vm_size_t); 69#endif |
| 70 71#endif /* _MACHINE_CACHE_MIPSNN_H_ */ |
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