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ar91xx_chip.c (223562) ar91xx_chip.c (228018)
1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar91xx_chip.c 223562 2011-06-26 10:07:48Z kevlo $");
28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar91xx_chip.c 228018 2011-11-27 11:15:59Z ray $");
29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>

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108{
109 uint32_t reg;
110
111 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
112 return ((reg & mask) == mask);
113}
114
115static void
29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>

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108{
109 uint32_t reg;
110
111 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
112 return ((reg & mask) == mask);
113}
114
115static void
116ar91xx_chip_set_pll_ge0(int speed)
116ar91xx_chip_set_pll_ge(int unit, int speed)
117{
118 uint32_t pll;
119
120 switch(speed) {
121 case 10:
122 pll = AR91XX_PLL_VAL_10;
123 break;
124 case 100:
125 pll = AR91XX_PLL_VAL_100;
126 break;
127 case 1000:
128 pll = AR91XX_PLL_VAL_1000;
129 break;
130 default:
117{
118 uint32_t pll;
119
120 switch(speed) {
121 case 10:
122 pll = AR91XX_PLL_VAL_10;
123 break;
124 case 100:
125 pll = AR91XX_PLL_VAL_100;
126 break;
127 case 1000:
128 pll = AR91XX_PLL_VAL_1000;
129 break;
130 default:
131 printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
132 speed);
131 printf("%s%d: invalid speed %d\n",
132 __func__, unit, speed);
133 return;
134 }
133 return;
134 }
135 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
136 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, AR91XX_ETH0_PLL_SHIFT);
135 switch (unit) {
136 case 0:
137 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
138 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll,
139 AR91XX_ETH0_PLL_SHIFT);
140 break;
141 case 1:
142 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
143 AR91XX_PLL_REG_ETH1_INT_CLOCK, pll,
144 AR91XX_ETH1_PLL_SHIFT);
145 break;
146 default:
147 printf("%s: invalid PLL set for arge unit: %d\n",
148 __func__, unit);
149 return;
150 }
137}
138
139static void
151}
152
153static void
140ar91xx_chip_set_pll_ge1(int speed)
154ar91xx_chip_ddr_flush_ge(int unit)
141{
155{
142 uint32_t pll;
143
144 switch(speed) {
145 case 10:
146 pll = AR91XX_PLL_VAL_10;
147 break;
148 case 100:
149 pll = AR91XX_PLL_VAL_100;
150 break;
151 case 1000:
152 pll = AR91XX_PLL_VAL_1000;
153 break;
154 default:
155 printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
156 speed);
157 return;
156 switch (unit) {
157 case 0:
158 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
159 break;
160 case 1:
161 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
162 break;
163 default:
164 printf("%s: invalid DDR flush for arge unit: %d\n",
165 __func__, unit);
166 return;
158 }
167 }
159 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
160 AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, AR91XX_ETH1_PLL_SHIFT);
161}
162
163static void
168}
169
170static void
164ar91xx_chip_ddr_flush_ge0(void)
165{
166 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
167}
168
169static void
170ar91xx_chip_ddr_flush_ge1(void)
171{
172 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
173}
174
175static void
176ar91xx_chip_ddr_flush_ip2(void)
177{
178 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
179}
180
181
182static uint32_t
183ar91xx_chip_get_eth_pll(unsigned int mac, int speed)

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206}
207
208struct ar71xx_cpu_def ar91xx_chip_def = {
209 &ar91xx_chip_detect_mem_size,
210 &ar91xx_chip_detect_sys_frequency,
211 &ar91xx_chip_device_stop,
212 &ar91xx_chip_device_start,
213 &ar91xx_chip_device_stopped,
171ar91xx_chip_ddr_flush_ip2(void)
172{
173 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
174}
175
176
177static uint32_t
178ar91xx_chip_get_eth_pll(unsigned int mac, int speed)

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201}
202
203struct ar71xx_cpu_def ar91xx_chip_def = {
204 &ar91xx_chip_detect_mem_size,
205 &ar91xx_chip_detect_sys_frequency,
206 &ar91xx_chip_device_stop,
207 &ar91xx_chip_device_start,
208 &ar91xx_chip_device_stopped,
214 &ar91xx_chip_set_pll_ge0,
215 &ar91xx_chip_set_pll_ge1,
216 &ar91xx_chip_ddr_flush_ge0,
217 &ar91xx_chip_ddr_flush_ge1,
209 &ar91xx_chip_set_pll_ge,
210 &ar91xx_chip_ddr_flush_ge,
218 &ar91xx_chip_get_eth_pll,
219 &ar91xx_chip_ddr_flush_ip2,
220 &ar91xx_chip_init_usb_peripheral,
221};
211 &ar91xx_chip_get_eth_pll,
212 &ar91xx_chip_ddr_flush_ip2,
213 &ar91xx_chip_init_usb_peripheral,
214};