1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
|
28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar724x_chip.c 219591 2011-03-13 08:36:57Z adrian $");
| 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar724x_chip.c 220180 2011-03-31 02:36:22Z adrian $");
|
29
30#include <sys/param.h>
31#include <machine/cpuregs.h>
32
33#include <mips/sentry5/s5reg.h>
34
35#include "opt_ddb.h"
36
37#include <sys/param.h>
38#include <sys/conf.h>
39#include <sys/kernel.h>
40#include <sys/systm.h>
41#include <sys/bus.h>
42#include <sys/cons.h>
43#include <sys/kdb.h>
44#include <sys/reboot.h>
45
46#include <vm/vm.h>
47#include <vm/vm_page.h>
48
49#include <net/ethernet.h>
50
51#include <machine/clock.h>
52#include <machine/cpu.h>
53#include <machine/hwfunc.h>
54#include <machine/md_var.h>
55#include <machine/trap.h>
56#include <machine/vmparam.h>
57
58#include <mips/atheros/ar71xxreg.h>
59#include <mips/atheros/ar724xreg.h>
60
61#include <mips/atheros/ar71xx_cpudef.h>
| 29
30#include <sys/param.h>
31#include <machine/cpuregs.h>
32
33#include <mips/sentry5/s5reg.h>
34
35#include "opt_ddb.h"
36
37#include <sys/param.h>
38#include <sys/conf.h>
39#include <sys/kernel.h>
40#include <sys/systm.h>
41#include <sys/bus.h>
42#include <sys/cons.h>
43#include <sys/kdb.h>
44#include <sys/reboot.h>
45
46#include <vm/vm.h>
47#include <vm/vm_page.h>
48
49#include <net/ethernet.h>
50
51#include <machine/clock.h>
52#include <machine/cpu.h>
53#include <machine/hwfunc.h>
54#include <machine/md_var.h>
55#include <machine/trap.h>
56#include <machine/vmparam.h>
57
58#include <mips/atheros/ar71xxreg.h>
59#include <mips/atheros/ar724xreg.h>
60
61#include <mips/atheros/ar71xx_cpudef.h>
|
| 62#include <mips/atheros/ar71xx_setup.h>
|
62#include <mips/atheros/ar724x_chip.h>
63
64static void
65ar724x_chip_detect_mem_size(void)
66{
67}
68
69static void
70ar724x_chip_detect_sys_frequency(void)
71{
72 uint32_t pll;
73 uint32_t freq;
74 uint32_t div;
75
76 pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
77
78 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
79 freq = div * AR724X_BASE_FREQ;
80
81 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
82 freq *= div;
83
84 u_ar71xx_cpu_freq = freq;
85
86 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
87 u_ar71xx_ddr_freq = freq / div;
88
89 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
90 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
91}
92
93static void
94ar724x_chip_device_stop(uint32_t mask)
95{
96 uint32_t mask_inv, reg;
97
98 mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
99 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
100 reg |= mask;
101 reg &= ~mask_inv;
102 ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
103}
104
105static void
106ar724x_chip_device_start(uint32_t mask)
107{
108 uint32_t mask_inv, reg;
109
110 mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
111 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
112 reg &= ~mask;
113 reg |= mask_inv;
114 ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
115}
116
117static int
118ar724x_chip_device_stopped(uint32_t mask)
119{
120 uint32_t reg;
121
122 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
123 return ((reg & mask) == mask);
124}
125
126static void
127ar724x_chip_set_pll_ge0(int speed)
128{
129}
130
131static void
132ar724x_chip_set_pll_ge1(int speed)
133{
134}
135
136static void
137ar724x_chip_ddr_flush_ge0(void)
138{
139 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
140}
141
142static void
143ar724x_chip_ddr_flush_ge1(void)
144{
145 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
146}
147
148static uint32_t
149ar724x_chip_get_eth_pll(unsigned int mac, int speed)
150{
151 return 0;
152}
153
| 63#include <mips/atheros/ar724x_chip.h>
64
65static void
66ar724x_chip_detect_mem_size(void)
67{
68}
69
70static void
71ar724x_chip_detect_sys_frequency(void)
72{
73 uint32_t pll;
74 uint32_t freq;
75 uint32_t div;
76
77 pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
78
79 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
80 freq = div * AR724X_BASE_FREQ;
81
82 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
83 freq *= div;
84
85 u_ar71xx_cpu_freq = freq;
86
87 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
88 u_ar71xx_ddr_freq = freq / div;
89
90 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
91 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
92}
93
94static void
95ar724x_chip_device_stop(uint32_t mask)
96{
97 uint32_t mask_inv, reg;
98
99 mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
100 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
101 reg |= mask;
102 reg &= ~mask_inv;
103 ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
104}
105
106static void
107ar724x_chip_device_start(uint32_t mask)
108{
109 uint32_t mask_inv, reg;
110
111 mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
112 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
113 reg &= ~mask;
114 reg |= mask_inv;
115 ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
116}
117
118static int
119ar724x_chip_device_stopped(uint32_t mask)
120{
121 uint32_t reg;
122
123 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
124 return ((reg & mask) == mask);
125}
126
127static void
128ar724x_chip_set_pll_ge0(int speed)
129{
130}
131
132static void
133ar724x_chip_set_pll_ge1(int speed)
134{
135}
136
137static void
138ar724x_chip_ddr_flush_ge0(void)
139{
140 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
141}
142
143static void
144ar724x_chip_ddr_flush_ge1(void)
145{
146 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
147}
148
149static uint32_t
150ar724x_chip_get_eth_pll(unsigned int mac, int speed)
151{
152 return 0;
153}
154
|
| 155static void
156ar724x_chip_init_usb_peripheral(void)
157{
158
159 switch (ar71xx_soc) {
160 case AR71XX_SOC_AR7240:
161
162 ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL |
163 AR724X_RESET_USB_HOST);
164 DELAY(1000);
165
166 ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL |
167 AR724X_RESET_USB_HOST);
168 DELAY(1000);
169
170 /*
171 * WAR for HW bug. Here it adjusts the duration
172 * between two SOFS.
173 */
174 ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
175 (3 << USB_CTRL_FLADJ_A0_SHIFT));
176
177 break;
178
179 case AR71XX_SOC_AR7241:
180 case AR71XX_SOC_AR7242:
181
182 ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL);
183 DELAY(100);
184
185 ar71xx_device_start(AR724X_RESET_USB_HOST);
186 DELAY(100);
187
188 ar71xx_device_start(AR724X_RESET_USB_PHY);
189 DELAY(100);
190
191 break;
192
193 default:
194 /* fallthrough */
195 break;
196 }
197}
198
|
154struct ar71xx_cpu_def ar724x_chip_def = {
155 &ar724x_chip_detect_mem_size,
156 &ar724x_chip_detect_sys_frequency,
157 &ar724x_chip_device_stop,
158 &ar724x_chip_device_start,
159 &ar724x_chip_device_stopped,
160 &ar724x_chip_set_pll_ge0,
161 &ar724x_chip_set_pll_ge1,
162 &ar724x_chip_ddr_flush_ge0,
163 &ar724x_chip_ddr_flush_ge1,
164 &ar724x_chip_get_eth_pll,
165 NULL, /* ar71xx_chip_irq_flush_ip2 */
| 199struct ar71xx_cpu_def ar724x_chip_def = {
200 &ar724x_chip_detect_mem_size,
201 &ar724x_chip_detect_sys_frequency,
202 &ar724x_chip_device_stop,
203 &ar724x_chip_device_start,
204 &ar724x_chip_device_stopped,
205 &ar724x_chip_set_pll_ge0,
206 &ar724x_chip_set_pll_ge1,
207 &ar724x_chip_ddr_flush_ge0,
208 &ar724x_chip_ddr_flush_ge1,
209 &ar724x_chip_get_eth_pll,
210 NULL, /* ar71xx_chip_irq_flush_ip2 */
|
166 NULL /* ar71xx_chip_init_usb_peripheral */
| 211 &ar724x_chip_init_usb_peripheral
|
167};
| 212};
|