1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
|
28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_setup.c 223562 2011-06-26 10:07:48Z kevlo $");
| 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_setup.c 248844 2013-03-28 19:30:56Z adrian $");
|
29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/cons.h>
38#include <sys/kdb.h>
39#include <sys/reboot.h>
40
41#include <vm/vm.h>
42#include <vm/vm_page.h>
43
44#include <net/ethernet.h>
45
46#include <machine/clock.h>
47#include <machine/cpu.h>
48#include <machine/cpuregs.h>
49#include <machine/hwfunc.h>
50#include <machine/md_var.h>
51#include <machine/trap.h>
52#include <machine/vmparam.h>
53
54#include <mips/atheros/ar71xxreg.h>
| 29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/cons.h>
38#include <sys/kdb.h>
39#include <sys/reboot.h>
40
41#include <vm/vm.h>
42#include <vm/vm_page.h>
43
44#include <net/ethernet.h>
45
46#include <machine/clock.h>
47#include <machine/cpu.h>
48#include <machine/cpuregs.h>
49#include <machine/hwfunc.h>
50#include <machine/md_var.h>
51#include <machine/trap.h>
52#include <machine/vmparam.h>
53
54#include <mips/atheros/ar71xxreg.h>
|
| 55#include <mips/atheros/ar933xreg.h>
56
|
55#include <mips/atheros/ar71xx_setup.h>
56
57#include <mips/atheros/ar71xx_cpudef.h>
58
59#include <mips/atheros/ar71xx_chip.h>
60#include <mips/atheros/ar724x_chip.h>
61#include <mips/atheros/ar91xx_chip.h>
| 57#include <mips/atheros/ar71xx_setup.h>
58
59#include <mips/atheros/ar71xx_cpudef.h>
60
61#include <mips/atheros/ar71xx_chip.h>
62#include <mips/atheros/ar724x_chip.h>
63#include <mips/atheros/ar91xx_chip.h>
|
| 64#include <mips/atheros/ar933x_chip.h>
|
62
| 65
|
63#include <mips/sentry5/s5reg.h>
64
| |
65#define AR71XX_SYS_TYPE_LEN 128
66
67static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
68enum ar71xx_soc_type ar71xx_soc;
69struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
70
71void
72ar71xx_detect_sys_type(void)
73{
74 char *chip = "????";
75 uint32_t id;
76 uint32_t major;
77 uint32_t minor;
78 uint32_t rev = 0;
79
80 id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
81 major = id & REV_ID_MAJOR_MASK;
82
83 switch (major) {
84 case REV_ID_MAJOR_AR71XX:
85 minor = id & AR71XX_REV_ID_MINOR_MASK;
86 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
87 rev &= AR71XX_REV_ID_REVISION_MASK;
88 ar71xx_cpu_ops = &ar71xx_chip_def;
89 switch (minor) {
90 case AR71XX_REV_ID_MINOR_AR7130:
91 ar71xx_soc = AR71XX_SOC_AR7130;
92 chip = "7130";
93 break;
94
95 case AR71XX_REV_ID_MINOR_AR7141:
96 ar71xx_soc = AR71XX_SOC_AR7141;
97 chip = "7141";
98 break;
99
100 case AR71XX_REV_ID_MINOR_AR7161:
101 ar71xx_soc = AR71XX_SOC_AR7161;
102 chip = "7161";
103 break;
104 }
105 break;
106
107 case REV_ID_MAJOR_AR7240:
108 ar71xx_soc = AR71XX_SOC_AR7240;
109 chip = "7240";
110 ar71xx_cpu_ops = &ar724x_chip_def;
111 rev = (id & AR724X_REV_ID_REVISION_MASK);
112 break;
113
114 case REV_ID_MAJOR_AR7241:
115 ar71xx_soc = AR71XX_SOC_AR7241;
116 chip = "7241";
117 ar71xx_cpu_ops = &ar724x_chip_def;
118 rev = (id & AR724X_REV_ID_REVISION_MASK);
119 break;
120
121 case REV_ID_MAJOR_AR7242:
122 ar71xx_soc = AR71XX_SOC_AR7242;
123 chip = "7242";
124 ar71xx_cpu_ops = &ar724x_chip_def;
125 rev = (id & AR724X_REV_ID_REVISION_MASK);
126 break;
127
128 case REV_ID_MAJOR_AR913X:
129 minor = id & AR91XX_REV_ID_MINOR_MASK;
130 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
131 rev &= AR91XX_REV_ID_REVISION_MASK;
132 ar71xx_cpu_ops = &ar91xx_chip_def;
133 switch (minor) {
134 case AR91XX_REV_ID_MINOR_AR9130:
135 ar71xx_soc = AR71XX_SOC_AR9130;
136 chip = "9130";
137 break;
138
139 case AR91XX_REV_ID_MINOR_AR9132:
140 ar71xx_soc = AR71XX_SOC_AR9132;
141 chip = "9132";
142 break;
143 }
144 break;
| 66#define AR71XX_SYS_TYPE_LEN 128
67
68static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
69enum ar71xx_soc_type ar71xx_soc;
70struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
71
72void
73ar71xx_detect_sys_type(void)
74{
75 char *chip = "????";
76 uint32_t id;
77 uint32_t major;
78 uint32_t minor;
79 uint32_t rev = 0;
80
81 id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
82 major = id & REV_ID_MAJOR_MASK;
83
84 switch (major) {
85 case REV_ID_MAJOR_AR71XX:
86 minor = id & AR71XX_REV_ID_MINOR_MASK;
87 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
88 rev &= AR71XX_REV_ID_REVISION_MASK;
89 ar71xx_cpu_ops = &ar71xx_chip_def;
90 switch (minor) {
91 case AR71XX_REV_ID_MINOR_AR7130:
92 ar71xx_soc = AR71XX_SOC_AR7130;
93 chip = "7130";
94 break;
95
96 case AR71XX_REV_ID_MINOR_AR7141:
97 ar71xx_soc = AR71XX_SOC_AR7141;
98 chip = "7141";
99 break;
100
101 case AR71XX_REV_ID_MINOR_AR7161:
102 ar71xx_soc = AR71XX_SOC_AR7161;
103 chip = "7161";
104 break;
105 }
106 break;
107
108 case REV_ID_MAJOR_AR7240:
109 ar71xx_soc = AR71XX_SOC_AR7240;
110 chip = "7240";
111 ar71xx_cpu_ops = &ar724x_chip_def;
112 rev = (id & AR724X_REV_ID_REVISION_MASK);
113 break;
114
115 case REV_ID_MAJOR_AR7241:
116 ar71xx_soc = AR71XX_SOC_AR7241;
117 chip = "7241";
118 ar71xx_cpu_ops = &ar724x_chip_def;
119 rev = (id & AR724X_REV_ID_REVISION_MASK);
120 break;
121
122 case REV_ID_MAJOR_AR7242:
123 ar71xx_soc = AR71XX_SOC_AR7242;
124 chip = "7242";
125 ar71xx_cpu_ops = &ar724x_chip_def;
126 rev = (id & AR724X_REV_ID_REVISION_MASK);
127 break;
128
129 case REV_ID_MAJOR_AR913X:
130 minor = id & AR91XX_REV_ID_MINOR_MASK;
131 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
132 rev &= AR91XX_REV_ID_REVISION_MASK;
133 ar71xx_cpu_ops = &ar91xx_chip_def;
134 switch (minor) {
135 case AR91XX_REV_ID_MINOR_AR9130:
136 ar71xx_soc = AR71XX_SOC_AR9130;
137 chip = "9130";
138 break;
139
140 case AR91XX_REV_ID_MINOR_AR9132:
141 ar71xx_soc = AR71XX_SOC_AR9132;
142 chip = "9132";
143 break;
144 }
145 break;
|
| 146 case REV_ID_MAJOR_AR9330:
147 minor = 0;
148 rev = (id & AR933X_REV_ID_REVISION_MASK);
149 chip = "9330";
150 ar71xx_cpu_ops = &ar933x_chip_def;
151 break;
152 case REV_ID_MAJOR_AR9331:
153 minor = 1;
154 rev = (id & AR933X_REV_ID_REVISION_MASK);
155 chip = "9331";
156 ar71xx_cpu_ops = &ar933x_chip_def;
157 break;
|
145
| 158
|
146
| |
147 default:
148 panic("ar71xx: unknown chip id:0x%08x\n", id);
149 }
150
151 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
152}
153
154const char *
155ar71xx_get_system_type(void)
156{
157 return ar71xx_sys_type;
158}
159
| 159 default:
160 panic("ar71xx: unknown chip id:0x%08x\n", id);
161 }
162
163 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
164}
165
166const char *
167ar71xx_get_system_type(void)
168{
169 return ar71xx_sys_type;
170}
171
|