| ar71xx_chip.c (234906) | ar71xx_chip.c (234907) |
|---|---|
| 1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_chip.c 234906 2012-05-02 01:21:57Z adrian $"); | 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_chip.c 234907 2012-05-02 04:51:43Z adrian $"); |
| 29 30#include "opt_ddb.h" 31 32#include <sys/param.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/bus.h> --- 180 unchanged lines hidden (view full) --- 217 val = ATH_READ_REG(reg); 218 val &= ~(MII_CTRL_IF_MASK << MII_CTRL_IF_SHIFT); 219 val |= (mii_if & MII_CTRL_IF_MASK) << MII_CTRL_IF_SHIFT; 220 ATH_WRITE_REG(reg, val); 221} 222 223/* Speed is either 10, 100 or 1000 */ 224static void | 29 30#include "opt_ddb.h" 31 32#include <sys/param.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/bus.h> --- 180 unchanged lines hidden (view full) --- 217 val = ATH_READ_REG(reg); 218 val &= ~(MII_CTRL_IF_MASK << MII_CTRL_IF_SHIFT); 219 val |= (mii_if & MII_CTRL_IF_MASK) << MII_CTRL_IF_SHIFT; 220 ATH_WRITE_REG(reg, val); 221} 222 223/* Speed is either 10, 100 or 1000 */ 224static void |
| 225ar71xx_chip_set_pll_ge(int unit, int speed) | 225ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll) |
| 226{ | 226{ |
| 227 uint32_t pll; | |
| 228 | 227 |
| 229 switch (speed) { 230 case 10: 231 pll = PLL_ETH_INT_CLK_10; 232 break; 233 case 100: 234 pll = PLL_ETH_INT_CLK_100; 235 break; 236 case 1000: 237 pll = PLL_ETH_INT_CLK_1000; 238 break; 239 default: 240 printf("%s%d: invalid speed %d\n", 241 __func__, unit, speed); 242 return; 243 } 244 | |
| 245 switch (unit) { 246 case 0: 247 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 248 AR71XX_PLL_ETH_INT0_CLK, pll, 249 AR71XX_PLL_ETH0_SHIFT); 250 break; 251 case 1: 252 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 253 AR71XX_PLL_ETH_INT1_CLK, pll, 254 AR71XX_PLL_ETH1_SHIFT); 255 break; 256 default: 257 printf("%s: invalid PLL set for arge unit: %d\n", 258 __func__, unit); 259 return; 260 } | 228 switch (unit) { 229 case 0: 230 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 231 AR71XX_PLL_ETH_INT0_CLK, pll, 232 AR71XX_PLL_ETH0_SHIFT); 233 break; 234 case 1: 235 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 236 AR71XX_PLL_ETH_INT1_CLK, pll, 237 AR71XX_PLL_ETH1_SHIFT); 238 break; 239 default: 240 printf("%s: invalid PLL set for arge unit: %d\n", 241 __func__, unit); 242 return; 243 } |
| 261 262 /* 263 * AR71xx and AR913x require this; AR724x doesn't require 264 * an MII clock change at all. 265 */ 266 ar71xx_chip_set_mii_speed(unit, speed); | |
| 267} 268 269static void 270ar71xx_chip_ddr_flush_ge(int unit) 271{ 272 273 switch (unit) { 274 case 0: --- 13 unchanged lines hidden (view full) --- 288ar71xx_chip_ddr_flush_ip2(void) 289{ 290 ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI); 291} 292 293static uint32_t 294ar71xx_chip_get_eth_pll(unsigned int mac, int speed) 295{ | 244} 245 246static void 247ar71xx_chip_ddr_flush_ge(int unit) 248{ 249 250 switch (unit) { 251 case 0: --- 13 unchanged lines hidden (view full) --- 265ar71xx_chip_ddr_flush_ip2(void) 266{ 267 ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI); 268} 269 270static uint32_t 271ar71xx_chip_get_eth_pll(unsigned int mac, int speed) 272{ |
| 296 return 0; | 273 uint32_t pll; 274 275 switch (speed) { 276 case 10: 277 pll = PLL_ETH_INT_CLK_10; 278 break; 279 case 100: 280 pll = PLL_ETH_INT_CLK_100; 281 break; 282 case 1000: 283 pll = PLL_ETH_INT_CLK_1000; 284 break; 285 default: 286 printf("%s%d: invalid speed %d\n", __func__, mac, speed); 287 pll = 0; 288 } 289 290 return (pll); |
| 297} 298 299static void 300ar71xx_chip_init_usb_peripheral(void) 301{ 302 303 ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | 304 RST_RESET_USB_HOST | RST_RESET_USB_PHY); --- 33 unchanged lines hidden --- | 291} 292 293static void 294ar71xx_chip_init_usb_peripheral(void) 295{ 296 297 ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | 298 RST_RESET_USB_HOST | RST_RESET_USB_PHY); --- 33 unchanged lines hidden --- |