| ar71xx_chip.c (234326) | ar71xx_chip.c (234906) |
|---|---|
| 1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_chip.c 234326 2012-04-15 22:34:22Z adrian $"); | 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_chip.c 234906 2012-05-02 01:21:57Z adrian $"); |
| 29 30#include "opt_ddb.h" 31 32#include <sys/param.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/bus.h> --- 134 unchanged lines hidden (view full) --- 171 } 172 173 val = ATH_READ_REG(reg); 174 val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); 175 val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; 176 ATH_WRITE_REG(reg, val); 177} 178 | 29 30#include "opt_ddb.h" 31 32#include <sys/param.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/bus.h> --- 134 unchanged lines hidden (view full) --- 171 } 172 173 val = ATH_READ_REG(reg); 174 val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); 175 val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; 176 ATH_WRITE_REG(reg, val); 177} 178 |
| 179void 180ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_mode) 181{ 182 uint32_t val, reg, mii_if; 183 184 switch (unit) { 185 case 0: 186 reg = AR71XX_MII0_CTRL; 187 if (mii_mode == AR71XX_MII_MODE_GMII) 188 mii_if = MII0_CTRL_IF_GMII; 189 else if (mii_mode == AR71XX_MII_MODE_MII) 190 mii_if = MII0_CTRL_IF_MII; 191 else if (mii_mode == AR71XX_MII_MODE_RGMII) 192 mii_if = MII0_CTRL_IF_RGMII; 193 else if (mii_mode == AR71XX_MII_MODE_RMII) 194 mii_if = MII0_CTRL_IF_RMII; 195 else 196 printf("%s: invalid MII mode (%d) for unit %d\n", 197 __func__, mii_mode, unit); 198 return; 199 break; 200 case 1: 201 reg = AR71XX_MII1_CTRL; 202 if (mii_mode == AR71XX_MII_MODE_RGMII) 203 mii_if = MII1_CTRL_IF_RGMII; 204 if (mii_mode == AR71XX_MII_MODE_RMII) 205 mii_if = MII1_CTRL_IF_RMII; 206 else 207 printf("%s: invalid MII mode (%d) for unit %d\n", 208 __func__, mii_mode, unit); 209 return; 210 break; 211 default: 212 printf("%s: invalid MII unit set for arge unit: %d\n", 213 __func__, unit); 214 return; 215 } 216 217 val = ATH_READ_REG(reg); 218 val &= ~(MII_CTRL_IF_MASK << MII_CTRL_IF_SHIFT); 219 val |= (mii_if & MII_CTRL_IF_MASK) << MII_CTRL_IF_SHIFT; 220 ATH_WRITE_REG(reg, val); 221} 222 |
|
| 179/* Speed is either 10, 100 or 1000 */ 180static void 181ar71xx_chip_set_pll_ge(int unit, int speed) 182{ 183 uint32_t pll; 184 185 switch (speed) { 186 case 10: --- 5 unchanged lines hidden (view full) --- 192 case 1000: 193 pll = PLL_ETH_INT_CLK_1000; 194 break; 195 default: 196 printf("%s%d: invalid speed %d\n", 197 __func__, unit, speed); 198 return; 199 } | 223/* Speed is either 10, 100 or 1000 */ 224static void 225ar71xx_chip_set_pll_ge(int unit, int speed) 226{ 227 uint32_t pll; 228 229 switch (speed) { 230 case 10: --- 5 unchanged lines hidden (view full) --- 236 case 1000: 237 pll = PLL_ETH_INT_CLK_1000; 238 break; 239 default: 240 printf("%s%d: invalid speed %d\n", 241 __func__, unit, speed); 242 return; 243 } |
| 244 |
|
| 200 switch (unit) { 201 case 0: 202 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 203 AR71XX_PLL_ETH_INT0_CLK, pll, 204 AR71XX_PLL_ETH0_SHIFT); 205 break; 206 case 1: 207 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 208 AR71XX_PLL_ETH_INT1_CLK, pll, 209 AR71XX_PLL_ETH1_SHIFT); 210 break; 211 default: 212 printf("%s: invalid PLL set for arge unit: %d\n", 213 __func__, unit); 214 return; 215 } | 245 switch (unit) { 246 case 0: 247 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 248 AR71XX_PLL_ETH_INT0_CLK, pll, 249 AR71XX_PLL_ETH0_SHIFT); 250 break; 251 case 1: 252 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 253 AR71XX_PLL_ETH_INT1_CLK, pll, 254 AR71XX_PLL_ETH1_SHIFT); 255 break; 256 default: 257 printf("%s: invalid PLL set for arge unit: %d\n", 258 __func__, unit); 259 return; 260 } |
| 261 262 /* 263 * AR71xx and AR913x require this; AR724x doesn't require 264 * an MII clock change at all. 265 */ 266 ar71xx_chip_set_mii_speed(unit, speed); |
|
| 216} 217 218static void 219ar71xx_chip_ddr_flush_ge(int unit) 220{ 221 222 switch (unit) { 223 case 0: --- 49 unchanged lines hidden (view full) --- 273struct ar71xx_cpu_def ar71xx_chip_def = { 274 &ar71xx_chip_detect_mem_size, 275 &ar71xx_chip_detect_sys_frequency, 276 &ar71xx_chip_device_stop, 277 &ar71xx_chip_device_start, 278 &ar71xx_chip_device_stopped, 279 &ar71xx_chip_set_pll_ge, 280 &ar71xx_chip_set_mii_speed, | 267} 268 269static void 270ar71xx_chip_ddr_flush_ge(int unit) 271{ 272 273 switch (unit) { 274 case 0: --- 49 unchanged lines hidden (view full) --- 324struct ar71xx_cpu_def ar71xx_chip_def = { 325 &ar71xx_chip_detect_mem_size, 326 &ar71xx_chip_detect_sys_frequency, 327 &ar71xx_chip_device_stop, 328 &ar71xx_chip_device_start, 329 &ar71xx_chip_device_stopped, 330 &ar71xx_chip_set_pll_ge, 331 &ar71xx_chip_set_mii_speed, |
| 332 &ar71xx_chip_set_mii_if, |
|
| 281 &ar71xx_chip_ddr_flush_ge, 282 &ar71xx_chip_get_eth_pll, 283 &ar71xx_chip_ddr_flush_ip2, 284 &ar71xx_chip_init_usb_peripheral, 285}; | 333 &ar71xx_chip_ddr_flush_ge, 334 &ar71xx_chip_get_eth_pll, 335 &ar71xx_chip_ddr_flush_ip2, 336 &ar71xx_chip_init_usb_peripheral, 337}; |