| ar71xx_chip.c (223562) | ar71xx_chip.c (228018) |
|---|---|
| 1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_chip.c 223562 2011-06-26 10:07:48Z kevlo $"); | 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_chip.c 228018 2011-11-27 11:15:59Z ray $"); |
| 29 30#include "opt_ddb.h" 31 32#include <sys/param.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/bus.h> --- 98 unchanged lines hidden (view full) --- 135 uint32_t reg; 136 137 reg = ATH_READ_REG(AR71XX_RST_RESET); 138 return ((reg & mask) == mask); 139} 140 141/* Speed is either 10, 100 or 1000 */ 142static void | 29 30#include "opt_ddb.h" 31 32#include <sys/param.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/bus.h> --- 98 unchanged lines hidden (view full) --- 135 uint32_t reg; 136 137 reg = ATH_READ_REG(AR71XX_RST_RESET); 138 return ((reg & mask) == mask); 139} 140 141/* Speed is either 10, 100 or 1000 */ 142static void |
| 143ar71xx_chip_set_pll_ge0(int speed) | 143ar71xx_chip_set_pll_ge(int unit, int speed) |
| 144{ 145 uint32_t pll; 146 147 switch(speed) { 148 case 10: 149 pll = PLL_ETH_INT_CLK_10; 150 break; 151 case 100: 152 pll = PLL_ETH_INT_CLK_100; 153 break; 154 case 1000: 155 pll = PLL_ETH_INT_CLK_1000; 156 break; 157 default: | 144{ 145 uint32_t pll; 146 147 switch(speed) { 148 case 10: 149 pll = PLL_ETH_INT_CLK_10; 150 break; 151 case 100: 152 pll = PLL_ETH_INT_CLK_100; 153 break; 154 case 1000: 155 pll = PLL_ETH_INT_CLK_1000; 156 break; 157 default: |
| 158 printf("ar71xx_chip_set_pll_ge0: invalid speed %d\n", speed); | 158 printf("%s%d: invalid speed %d\n", 159 __func__, unit, speed); |
| 159 return; 160 } | 160 return; 161 } |
| 161 162 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT0_CLK, pll, AR71XX_PLL_ETH0_SHIFT); | 162 switch (unit) { 163 case 0: 164 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 165 AR71XX_PLL_ETH_INT0_CLK, pll, 166 AR71XX_PLL_ETH0_SHIFT); 167 break; 168 case 1: 169 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 170 AR71XX_PLL_ETH_INT1_CLK, pll, 171 AR71XX_PLL_ETH1_SHIFT); 172 break; 173 default: 174 printf("%s: invalid PLL set for arge unit: %d\n", 175 __func__, unit); 176 return; 177 } |
| 163} 164 165static void | 178} 179 180static void |
| 166ar71xx_chip_set_pll_ge1(int speed) | 181ar71xx_chip_ddr_flush_ge(int unit) |
| 167{ | 182{ |
| 168 uint32_t pll; 169 170 switch(speed) { 171 case 10: 172 pll = PLL_ETH_INT_CLK_10; 173 break; 174 case 100: 175 pll = PLL_ETH_INT_CLK_100; 176 break; 177 case 1000: 178 pll = PLL_ETH_INT_CLK_1000; 179 break; 180 default: 181 printf("ar71xx_chip_set_pll_ge1: invalid speed %d\n", speed); 182 return; | 183 switch (unit) { 184 case 0: 185 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0); 186 break; 187 case 1: 188 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1); 189 break; 190 default: 191 printf("%s: invalid DDR flush for arge unit: %d\n", 192 __func__, unit); 193 return; |
| 183 } | 194 } |
| 184 185 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT1_CLK, pll, AR71XX_PLL_ETH1_SHIFT); | |
| 186} 187 188static void | 195} 196 197static void |
| 189ar71xx_chip_ddr_flush_ge0(void) 190{ 191 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0); 192} 193 194static void 195ar71xx_chip_ddr_flush_ge1(void) 196{ 197 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1); 198} 199 200static void | |
| 201ar71xx_chip_ddr_flush_ip2(void) 202{ 203 ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI); 204} 205 206static uint32_t 207ar71xx_chip_get_eth_pll(unsigned int mac, int speed) 208{ --- 20 unchanged lines hidden (view full) --- 229} 230 231struct ar71xx_cpu_def ar71xx_chip_def = { 232 &ar71xx_chip_detect_mem_size, 233 &ar71xx_chip_detect_sys_frequency, 234 &ar71xx_chip_device_stop, 235 &ar71xx_chip_device_start, 236 &ar71xx_chip_device_stopped, | 198ar71xx_chip_ddr_flush_ip2(void) 199{ 200 ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI); 201} 202 203static uint32_t 204ar71xx_chip_get_eth_pll(unsigned int mac, int speed) 205{ --- 20 unchanged lines hidden (view full) --- 226} 227 228struct ar71xx_cpu_def ar71xx_chip_def = { 229 &ar71xx_chip_detect_mem_size, 230 &ar71xx_chip_detect_sys_frequency, 231 &ar71xx_chip_device_stop, 232 &ar71xx_chip_device_start, 233 &ar71xx_chip_device_stopped, |
| 237 &ar71xx_chip_set_pll_ge0, 238 &ar71xx_chip_set_pll_ge1, 239 &ar71xx_chip_ddr_flush_ge0, 240 &ar71xx_chip_ddr_flush_ge1, | 234 &ar71xx_chip_set_pll_ge, 235 &ar71xx_chip_ddr_flush_ge, |
| 241 &ar71xx_chip_get_eth_pll, 242 &ar71xx_chip_ddr_flush_ip2, 243 &ar71xx_chip_init_usb_peripheral, 244}; | 236 &ar71xx_chip_get_eth_pll, 237 &ar71xx_chip_ddr_flush_ip2, 238 &ar71xx_chip_init_usb_peripheral, 239}; |