1/*- 2 * Copyright (c) 2001 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 *
| 1/*- 2 * Copyright (c) 2001 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 *
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30#include <contrib/dev/acpica/actables.h> 31 32#include <machine/md_var.h> 33 34extern u_int64_t ia64_lapic_address; 35 36struct sapic *sapic_create(int, int, u_int64_t); 37 38static void 39print_entry(APIC_HEADER *entry) 40{ 41 42 switch (entry->Type) { 43 case APIC_XRUPT_OVERRIDE: { 44 MADT_INTERRUPT_OVERRIDE *iso = 45 (MADT_INTERRUPT_OVERRIDE *)entry; 46 printf("\tInterrupt source override entry\n"); 47 printf("\t\tBus=%d, Source=%d, Irq=0x%x\n", iso->Bus, 48 iso->Source, iso->Interrupt); 49 break; 50 } 51 52 case APIC_IO: 53 printf("\tI/O APIC entry\n"); 54 break; 55 56 case APIC_IO_SAPIC: { 57 MADT_IO_SAPIC *sapic = (MADT_IO_SAPIC *)entry; 58 printf("\tI/O SAPIC entry\n"); 59 printf("\t\tId=0x%x, InterruptBase=0x%x, Address=0x%lx\n", 60 sapic->IoSapicId, sapic->InterruptBase, sapic->Address); 61 break; 62 } 63 64 case APIC_LOCAL_NMI: 65 printf("\tLocal APIC NMI entry\n"); 66 break; 67 68 case APIC_ADDRESS_OVERRIDE: { 69 MADT_ADDRESS_OVERRIDE *lapic = (MADT_ADDRESS_OVERRIDE *)entry; 70 printf("\tLocal APIC override entry\n"); 71 printf("\t\tLocal APIC address=0x%jx\n", lapic->Address); 72 break; 73 } 74 75 case APIC_LOCAL_SAPIC: { 76 MADT_LOCAL_SAPIC *sapic = (MADT_LOCAL_SAPIC *)entry; 77 printf("\tLocal SAPIC entry\n"); 78 printf("\t\tProcessorId=0x%x, Id=0x%x, Eid=0x%x", 79 sapic->ProcessorId, sapic->LocalSapicId, 80 sapic->LocalSapicEid); 81 if (!sapic->ProcessorEnabled) 82 printf(" (disabled)"); 83 printf("\n"); 84 break; 85 } 86 87 case APIC_NMI: 88 printf("\tNMI entry\n"); 89 break; 90 91 case APIC_XRUPT_SOURCE: { 92 MADT_INTERRUPT_SOURCE *pis = (MADT_INTERRUPT_SOURCE *)entry; 93 printf("\tPlatform interrupt entry\n"); 94 printf("\t\tPolarity=%d, TriggerMode=%d, Id=0x%x, " 95 "Eid=0x%x, Vector=0x%x, Irq=%d\n", 96 pis->Polarity, pis->TriggerMode, pis->ProcessorId, 97 pis->ProcessorEid, pis->IoSapicVector, pis->Interrupt); 98 break; 99 } 100 101 case APIC_PROCESSOR: 102 printf("\tLocal APIC entry\n"); 103 break; 104 105 default: 106 printf("\tUnknown type %d entry\n", entry->Type); 107 break; 108 } 109} 110 111void 112ia64_probe_sapics(void) 113{ 114 ACPI_POINTER rsdp_ptr; 115 APIC_HEADER *entry; 116 MULTIPLE_APIC_TABLE *table; 117 RSDP_DESCRIPTOR *rsdp; 118 XSDT_DESCRIPTOR *xsdt; 119 char *end, *p; 120 int t, tables; 121 122 if (AcpiOsGetRootPointer(ACPI_LOGICAL_ADDRESSING, &rsdp_ptr) != AE_OK) 123 return; 124 125 rsdp = (RSDP_DESCRIPTOR *)IA64_PHYS_TO_RR7(rsdp_ptr.Pointer.Physical); 126 xsdt = (XSDT_DESCRIPTOR *)IA64_PHYS_TO_RR7(rsdp->XsdtPhysicalAddress); 127 128 tables = (UINT64 *)((char *)xsdt + xsdt->Length) - 129 xsdt->TableOffsetEntry; 130 131 for (t = 0; t < tables; t++) { 132 table = (MULTIPLE_APIC_TABLE *) 133 IA64_PHYS_TO_RR7(xsdt->TableOffsetEntry[t]); 134 135 if (bootverbose) 136 printf("Table '%c%c%c%c' at %p\n", 137 table->Signature[0], table->Signature[1], 138 table->Signature[2], table->Signature[3], table); 139 140 if (strncmp(table->Signature, APIC_SIG, 4) != 0 || 141 ACPI_FAILURE(AcpiTbVerifyTableChecksum((void *)table))) 142 continue; 143 144 /* Save the address of the processor interrupt block. */ 145 if (bootverbose) 146 printf("\tLocal APIC address=0x%x\n", 147 table->LocalApicAddress); 148 ia64_lapic_address = table->LocalApicAddress; 149 150 end = (char *)table + table->Length; 151 p = (char *)(table + 1); 152 while (p < end) { 153 entry = (APIC_HEADER *)p; 154 155 if (bootverbose) 156 print_entry(entry); 157 158 switch (entry->Type) { 159 case APIC_IO_SAPIC: { 160 MADT_IO_SAPIC *sapic = (MADT_IO_SAPIC *)entry; 161 sapic_create(sapic->IoSapicId, 162 sapic->InterruptBase, sapic->Address); 163 break; 164 } 165 166 case APIC_ADDRESS_OVERRIDE: { 167 MADT_ADDRESS_OVERRIDE *lapic = 168 (MADT_ADDRESS_OVERRIDE*)entry; 169 ia64_lapic_address = lapic->Address; 170 break; 171 } 172 173#ifdef SMP 174 case APIC_LOCAL_SAPIC: { 175 MADT_LOCAL_SAPIC *sapic = 176 (MADT_LOCAL_SAPIC *)entry; 177 if (sapic->ProcessorEnabled) 178 cpu_mp_add(sapic->ProcessorId, 179 sapic->LocalSapicId, 180 sapic->LocalSapicEid); 181 break; 182 } 183#endif 184 185 default: 186 break; 187 } 188 189 p += entry->Length; 190 } 191 } 192} 193 194/* 195 * Count the number of local SAPIC entries in the APIC table. Every enabled 196 * entry corresponds to a processor. 197 */ 198int 199ia64_count_cpus(void) 200{ 201 ACPI_POINTER rsdp_ptr; 202 MULTIPLE_APIC_TABLE *table; 203 MADT_LOCAL_SAPIC *entry; 204 RSDP_DESCRIPTOR *rsdp; 205 XSDT_DESCRIPTOR *xsdt; 206 char *end, *p; 207 int cpus, t, tables; 208 209 if (AcpiOsGetRootPointer(ACPI_LOGICAL_ADDRESSING, &rsdp_ptr) != AE_OK) 210 return (0); 211 212 rsdp = (RSDP_DESCRIPTOR *)IA64_PHYS_TO_RR7(rsdp_ptr.Pointer.Physical); 213 xsdt = (XSDT_DESCRIPTOR *)IA64_PHYS_TO_RR7(rsdp->XsdtPhysicalAddress); 214 215 tables = (UINT64 *)((char *)xsdt + xsdt->Length) - 216 xsdt->TableOffsetEntry; 217 218 cpus = 0; 219 220 for (t = 0; t < tables; t++) { 221 table = (MULTIPLE_APIC_TABLE *) 222 IA64_PHYS_TO_RR7(xsdt->TableOffsetEntry[t]); 223 224 if (strncmp(table->Signature, APIC_SIG, 4) != 0 || 225 ACPI_FAILURE(AcpiTbVerifyTableChecksum((void *)table))) 226 continue; 227 228 end = (char *)table + table->Length; 229 p = (char *)(table + 1); 230 while (p < end) { 231 entry = (MADT_LOCAL_SAPIC *)p; 232 233 if (entry->Type == APIC_LOCAL_SAPIC && 234 entry->ProcessorEnabled) 235 cpus++; 236 237 p += entry->Length; 238 } 239 } 240 241 return (cpus); 242}
| 30#include <contrib/dev/acpica/actables.h> 31 32#include <machine/md_var.h> 33 34extern u_int64_t ia64_lapic_address; 35 36struct sapic *sapic_create(int, int, u_int64_t); 37 38static void 39print_entry(APIC_HEADER *entry) 40{ 41 42 switch (entry->Type) { 43 case APIC_XRUPT_OVERRIDE: { 44 MADT_INTERRUPT_OVERRIDE *iso = 45 (MADT_INTERRUPT_OVERRIDE *)entry; 46 printf("\tInterrupt source override entry\n"); 47 printf("\t\tBus=%d, Source=%d, Irq=0x%x\n", iso->Bus, 48 iso->Source, iso->Interrupt); 49 break; 50 } 51 52 case APIC_IO: 53 printf("\tI/O APIC entry\n"); 54 break; 55 56 case APIC_IO_SAPIC: { 57 MADT_IO_SAPIC *sapic = (MADT_IO_SAPIC *)entry; 58 printf("\tI/O SAPIC entry\n"); 59 printf("\t\tId=0x%x, InterruptBase=0x%x, Address=0x%lx\n", 60 sapic->IoSapicId, sapic->InterruptBase, sapic->Address); 61 break; 62 } 63 64 case APIC_LOCAL_NMI: 65 printf("\tLocal APIC NMI entry\n"); 66 break; 67 68 case APIC_ADDRESS_OVERRIDE: { 69 MADT_ADDRESS_OVERRIDE *lapic = (MADT_ADDRESS_OVERRIDE *)entry; 70 printf("\tLocal APIC override entry\n"); 71 printf("\t\tLocal APIC address=0x%jx\n", lapic->Address); 72 break; 73 } 74 75 case APIC_LOCAL_SAPIC: { 76 MADT_LOCAL_SAPIC *sapic = (MADT_LOCAL_SAPIC *)entry; 77 printf("\tLocal SAPIC entry\n"); 78 printf("\t\tProcessorId=0x%x, Id=0x%x, Eid=0x%x", 79 sapic->ProcessorId, sapic->LocalSapicId, 80 sapic->LocalSapicEid); 81 if (!sapic->ProcessorEnabled) 82 printf(" (disabled)"); 83 printf("\n"); 84 break; 85 } 86 87 case APIC_NMI: 88 printf("\tNMI entry\n"); 89 break; 90 91 case APIC_XRUPT_SOURCE: { 92 MADT_INTERRUPT_SOURCE *pis = (MADT_INTERRUPT_SOURCE *)entry; 93 printf("\tPlatform interrupt entry\n"); 94 printf("\t\tPolarity=%d, TriggerMode=%d, Id=0x%x, " 95 "Eid=0x%x, Vector=0x%x, Irq=%d\n", 96 pis->Polarity, pis->TriggerMode, pis->ProcessorId, 97 pis->ProcessorEid, pis->IoSapicVector, pis->Interrupt); 98 break; 99 } 100 101 case APIC_PROCESSOR: 102 printf("\tLocal APIC entry\n"); 103 break; 104 105 default: 106 printf("\tUnknown type %d entry\n", entry->Type); 107 break; 108 } 109} 110 111void 112ia64_probe_sapics(void) 113{ 114 ACPI_POINTER rsdp_ptr; 115 APIC_HEADER *entry; 116 MULTIPLE_APIC_TABLE *table; 117 RSDP_DESCRIPTOR *rsdp; 118 XSDT_DESCRIPTOR *xsdt; 119 char *end, *p; 120 int t, tables; 121 122 if (AcpiOsGetRootPointer(ACPI_LOGICAL_ADDRESSING, &rsdp_ptr) != AE_OK) 123 return; 124 125 rsdp = (RSDP_DESCRIPTOR *)IA64_PHYS_TO_RR7(rsdp_ptr.Pointer.Physical); 126 xsdt = (XSDT_DESCRIPTOR *)IA64_PHYS_TO_RR7(rsdp->XsdtPhysicalAddress); 127 128 tables = (UINT64 *)((char *)xsdt + xsdt->Length) - 129 xsdt->TableOffsetEntry; 130 131 for (t = 0; t < tables; t++) { 132 table = (MULTIPLE_APIC_TABLE *) 133 IA64_PHYS_TO_RR7(xsdt->TableOffsetEntry[t]); 134 135 if (bootverbose) 136 printf("Table '%c%c%c%c' at %p\n", 137 table->Signature[0], table->Signature[1], 138 table->Signature[2], table->Signature[3], table); 139 140 if (strncmp(table->Signature, APIC_SIG, 4) != 0 || 141 ACPI_FAILURE(AcpiTbVerifyTableChecksum((void *)table))) 142 continue; 143 144 /* Save the address of the processor interrupt block. */ 145 if (bootverbose) 146 printf("\tLocal APIC address=0x%x\n", 147 table->LocalApicAddress); 148 ia64_lapic_address = table->LocalApicAddress; 149 150 end = (char *)table + table->Length; 151 p = (char *)(table + 1); 152 while (p < end) { 153 entry = (APIC_HEADER *)p; 154 155 if (bootverbose) 156 print_entry(entry); 157 158 switch (entry->Type) { 159 case APIC_IO_SAPIC: { 160 MADT_IO_SAPIC *sapic = (MADT_IO_SAPIC *)entry; 161 sapic_create(sapic->IoSapicId, 162 sapic->InterruptBase, sapic->Address); 163 break; 164 } 165 166 case APIC_ADDRESS_OVERRIDE: { 167 MADT_ADDRESS_OVERRIDE *lapic = 168 (MADT_ADDRESS_OVERRIDE*)entry; 169 ia64_lapic_address = lapic->Address; 170 break; 171 } 172 173#ifdef SMP 174 case APIC_LOCAL_SAPIC: { 175 MADT_LOCAL_SAPIC *sapic = 176 (MADT_LOCAL_SAPIC *)entry; 177 if (sapic->ProcessorEnabled) 178 cpu_mp_add(sapic->ProcessorId, 179 sapic->LocalSapicId, 180 sapic->LocalSapicEid); 181 break; 182 } 183#endif 184 185 default: 186 break; 187 } 188 189 p += entry->Length; 190 } 191 } 192} 193 194/* 195 * Count the number of local SAPIC entries in the APIC table. Every enabled 196 * entry corresponds to a processor. 197 */ 198int 199ia64_count_cpus(void) 200{ 201 ACPI_POINTER rsdp_ptr; 202 MULTIPLE_APIC_TABLE *table; 203 MADT_LOCAL_SAPIC *entry; 204 RSDP_DESCRIPTOR *rsdp; 205 XSDT_DESCRIPTOR *xsdt; 206 char *end, *p; 207 int cpus, t, tables; 208 209 if (AcpiOsGetRootPointer(ACPI_LOGICAL_ADDRESSING, &rsdp_ptr) != AE_OK) 210 return (0); 211 212 rsdp = (RSDP_DESCRIPTOR *)IA64_PHYS_TO_RR7(rsdp_ptr.Pointer.Physical); 213 xsdt = (XSDT_DESCRIPTOR *)IA64_PHYS_TO_RR7(rsdp->XsdtPhysicalAddress); 214 215 tables = (UINT64 *)((char *)xsdt + xsdt->Length) - 216 xsdt->TableOffsetEntry; 217 218 cpus = 0; 219 220 for (t = 0; t < tables; t++) { 221 table = (MULTIPLE_APIC_TABLE *) 222 IA64_PHYS_TO_RR7(xsdt->TableOffsetEntry[t]); 223 224 if (strncmp(table->Signature, APIC_SIG, 4) != 0 || 225 ACPI_FAILURE(AcpiTbVerifyTableChecksum((void *)table))) 226 continue; 227 228 end = (char *)table + table->Length; 229 p = (char *)(table + 1); 230 while (p < end) { 231 entry = (MADT_LOCAL_SAPIC *)p; 232 233 if (entry->Type == APIC_LOCAL_SAPIC && 234 entry->ProcessorEnabled) 235 cpus++; 236 237 p += entry->Length; 238 } 239 } 240 241 return (cpus); 242}
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