| if_wbreg.h (67087) | if_wbreg.h (72200) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_wbreg.h 67087 2000-10-13 17:54:19Z wpaul $ | 32 * $FreeBSD: head/sys/pci/if_wbreg.h 72200 2001-02-09 06:11:45Z bmilekic $ |
| 33 */ 34 35/* 36 * Winbond register definitions. 37 */ 38 39#define WB_BUSCTL 0x00 /* bus control */ 40#define WB_TXSTART 0x04 /* tx start demand */ --- 335 unchanged lines hidden (view full) --- 376 int wb_cachesize; 377 caddr_t wb_ldata_ptr; 378 struct wb_list_data *wb_ldata; 379 struct wb_chain_data wb_cdata; 380 struct callout_handle wb_stat_ch; 381 struct mtx wb_mtx; 382}; 383 | 33 */ 34 35/* 36 * Winbond register definitions. 37 */ 38 39#define WB_BUSCTL 0x00 /* bus control */ 40#define WB_TXSTART 0x04 /* tx start demand */ --- 335 unchanged lines hidden (view full) --- 376 int wb_cachesize; 377 caddr_t wb_ldata_ptr; 378 struct wb_list_data *wb_ldata; 379 struct wb_chain_data wb_cdata; 380 struct callout_handle wb_stat_ch; 381 struct mtx wb_mtx; 382}; 383 |
| 384#define WB_LOCK(_sc) mtx_enter(&(_sc)->wb_mtx, MTX_DEF) 385#define WB_UNLOCK(_sc) mtx_exit(&(_sc)->wb_mtx, MTX_DEF) | 384#define WB_LOCK(_sc) mtx_lock(&(_sc)->wb_mtx) 385#define WB_UNLOCK(_sc) mtx_unlock(&(_sc)->wb_mtx) |
| 386 387/* 388 * register space access macros 389 */ 390#define CSR_WRITE_4(sc, reg, val) \ 391 bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val) 392#define CSR_WRITE_2(sc, reg, val) \ 393 bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val) --- 75 unchanged lines hidden --- | 386 387/* 388 * register space access macros 389 */ 390#define CSR_WRITE_4(sc, reg, val) \ 391 bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val) 392#define CSR_WRITE_2(sc, reg, val) \ 393 bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val) --- 75 unchanged lines hidden --- |