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if_wbreg.h (50477) if_wbreg.h (50675)
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/pci/if_wbreg.h 50477 1999-08-28 01:08:13Z peter $
32 * $FreeBSD: head/sys/pci/if_wbreg.h 50675 1999-08-30 23:08:32Z wpaul $
33 */
34
35/*
36 * Winbond register definitions.
37 */
38
39#define WB_BUSCTL 0x00 /* bus control */
40#define WB_TXSTART 0x04 /* tx start demand */

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64#define WB_BUSCTL_RESET 0x00000001
65#define WB_BUSCTL_ARBITRATION 0x00000002
66#define WB_BUSCTL_SKIPLEN 0x0000007C
67#define WB_BUSCTL_BUF_BIGENDIAN 0x00000080
68#define WB_BUSCTL_BURSTLEN 0x00003F00
69#define WB_BUSCTL_CACHEALIGN 0x0000C000
70#define WB_BUSCTL_DES_BIGENDIAN 0x00100000
71#define WB_BUSCTL_WAIT 0x00200000
33 */
34
35/*
36 * Winbond register definitions.
37 */
38
39#define WB_BUSCTL 0x00 /* bus control */
40#define WB_TXSTART 0x04 /* tx start demand */

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64#define WB_BUSCTL_RESET 0x00000001
65#define WB_BUSCTL_ARBITRATION 0x00000002
66#define WB_BUSCTL_SKIPLEN 0x0000007C
67#define WB_BUSCTL_BUF_BIGENDIAN 0x00000080
68#define WB_BUSCTL_BURSTLEN 0x00003F00
69#define WB_BUSCTL_CACHEALIGN 0x0000C000
70#define WB_BUSCTL_DES_BIGENDIAN 0x00100000
71#define WB_BUSCTL_WAIT 0x00200000
72#define WB_BUSCTL_MUSTBEONE 0x00400000
72
73#define WB_SKIPLEN_1LONG 0x00000004
74#define WB_SKIPLEN_2LONG 0x00000008
75#define WB_SKIPLEN_3LONG 0x00000010
76#define WB_SKIPLEN_4LONG 0x00000020
77#define WB_SKIPLEN_5LONG 0x00000040
78
73
74#define WB_SKIPLEN_1LONG 0x00000004
75#define WB_SKIPLEN_2LONG 0x00000008
76#define WB_SKIPLEN_3LONG 0x00000010
77#define WB_SKIPLEN_4LONG 0x00000020
78#define WB_SKIPLEN_5LONG 0x00000040
79
80#define WB_CACHEALIGN_NONE 0x00000000
79#define WB_CACHEALIGN_8LONG 0x00004000
80#define WB_CACHEALIGN_16LONG 0x00008000
81#define WB_CACHEALIGN_32LONG 0x0000C000
82
83#define WB_BURSTLEN_USECA 0x00000000
84#define WB_BURSTLEN_1LONG 0x00000100
85#define WB_BURSTLEN_2LONG 0x00000200
86#define WB_BURSTLEN_4LONG 0x00000400

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292#define WB_TXSTATUS(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status
293#define WB_TXCTL(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl
294#define WB_TXDATA(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data
295
296#define WB_TXOWN(x) x->wb_ptr->wb_frag[0].wb_status
297
298#define WB_UNSENT 0x1234
299
81#define WB_CACHEALIGN_8LONG 0x00004000
82#define WB_CACHEALIGN_16LONG 0x00008000
83#define WB_CACHEALIGN_32LONG 0x0000C000
84
85#define WB_BURSTLEN_USECA 0x00000000
86#define WB_BURSTLEN_1LONG 0x00000100
87#define WB_BURSTLEN_2LONG 0x00000200
88#define WB_BURSTLEN_4LONG 0x00000400

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294#define WB_TXSTATUS(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status
295#define WB_TXCTL(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl
296#define WB_TXDATA(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data
297
298#define WB_TXOWN(x) x->wb_ptr->wb_frag[0].wb_status
299
300#define WB_UNSENT 0x1234
301
302#define WB_BUFBYTES (1024 * sizeof(u_int32_t))
303
304struct wb_buf {
305 u_int32_t wb_data[1024];
306};
307
300struct wb_list_data {
308struct wb_list_data {
309 struct wb_buf wb_rxbufs[WB_RX_LIST_CNT];
301 struct wb_desc wb_rx_list[WB_RX_LIST_CNT];
302 struct wb_txdesc wb_tx_list[WB_TX_LIST_CNT];
303};
304
305struct wb_chain {
306 struct wb_txdesc *wb_ptr;
307 struct mbuf *wb_mbuf;
308 struct wb_chain *wb_nextdesc;
309 u_int8_t wb_lastdesc;
310};
311
312struct wb_chain_onefrag {
313 struct wb_desc *wb_ptr;
314 struct mbuf *wb_mbuf;
310 struct wb_desc wb_rx_list[WB_RX_LIST_CNT];
311 struct wb_txdesc wb_tx_list[WB_TX_LIST_CNT];
312};
313
314struct wb_chain {
315 struct wb_txdesc *wb_ptr;
316 struct mbuf *wb_mbuf;
317 struct wb_chain *wb_nextdesc;
318 u_int8_t wb_lastdesc;
319};
320
321struct wb_chain_onefrag {
322 struct wb_desc *wb_ptr;
323 struct mbuf *wb_mbuf;
324 void *wb_buf;
315 struct wb_chain_onefrag *wb_nextdesc;
316 u_int8_t wb_rlast;
317};
318
319struct wb_chain_data {
320 u_int8_t wb_pad[WB_MIN_FRAMELEN];
321 struct wb_chain_onefrag wb_rx_chain[WB_RX_LIST_CNT];
322 struct wb_chain wb_tx_chain[WB_TX_LIST_CNT];

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346/*
347 * MII constants
348 */
349#define WB_MII_STARTDELIM 0x01
350#define WB_MII_READOP 0x02
351#define WB_MII_WRITEOP 0x01
352#define WB_MII_TURNAROUND 0x02
353
325 struct wb_chain_onefrag *wb_nextdesc;
326 u_int8_t wb_rlast;
327};
328
329struct wb_chain_data {
330 u_int8_t wb_pad[WB_MIN_FRAMELEN];
331 struct wb_chain_onefrag wb_rx_chain[WB_RX_LIST_CNT];
332 struct wb_chain wb_tx_chain[WB_TX_LIST_CNT];

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356/*
357 * MII constants
358 */
359#define WB_MII_STARTDELIM 0x01
360#define WB_MII_READOP 0x02
361#define WB_MII_WRITEOP 0x01
362#define WB_MII_TURNAROUND 0x02
363
354#define WB_FLAG_FORCEDELAY 1
355#define WB_FLAG_SCHEDDELAY 2
356#define WB_FLAG_DELAYTIMEO 3
357
358struct wb_softc {
359 struct arpcom arpcom; /* interface info */
364struct wb_softc {
365 struct arpcom arpcom; /* interface info */
360 struct ifmedia ifmedia; /* media info */
366 device_t wb_miibus;
361 bus_space_handle_t wb_bhandle;
362 bus_space_tag_t wb_btag;
363 struct resource *wb_res;
364 struct resource *wb_irq;
365 void *wb_intrhand;
366 struct wb_type *wb_info; /* Winbond adapter info */
367 bus_space_handle_t wb_bhandle;
368 bus_space_tag_t wb_btag;
369 struct resource *wb_res;
370 struct resource *wb_irq;
371 void *wb_intrhand;
372 struct wb_type *wb_info; /* Winbond adapter info */
367 struct wb_type *wb_pinfo; /* phy info */
368 u_int8_t wb_unit; /* interface number */
369 u_int8_t wb_type;
373 u_int8_t wb_unit; /* interface number */
374 u_int8_t wb_type;
370 u_int8_t wb_phy_addr; /* PHY address */
371 u_int8_t wb_tx_pend; /* TX pending */
372 u_int8_t wb_want_auto;
373 u_int8_t wb_autoneg;
374 u_int16_t wb_txthresh;
375 u_int16_t wb_txthresh;
376 int wb_cachesize;
375 caddr_t wb_ldata_ptr;
376 struct wb_list_data *wb_ldata;
377 struct wb_chain_data wb_cdata;
377 caddr_t wb_ldata_ptr;
378 struct wb_list_data *wb_ldata;
379 struct wb_chain_data wb_cdata;
380 struct callout_handle wb_stat_ch;
378};
379
380/*
381 * register space access macros
382 */
383#define CSR_WRITE_4(sc, reg, val) \
384 bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
385#define CSR_WRITE_2(sc, reg, val) \

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414#define CP_VENDORID 0x11F6
415
416/*
417 * Compex device IDs.
418 */
419#define CP_DEVICEID_RL100 0x2011
420
421/*
381};
382
383/*
384 * register space access macros
385 */
386#define CSR_WRITE_4(sc, reg, val) \
387 bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
388#define CSR_WRITE_2(sc, reg, val) \

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417#define CP_VENDORID 0x11F6
418
419/*
420 * Compex device IDs.
421 */
422#define CP_DEVICEID_RL100 0x2011
423
424/*
422 * Texas Instruments PHY identifiers
423 */
424#define TI_PHY_VENDORID 0x4000
425#define TI_PHY_10BT 0x501F
426#define TI_PHY_100VGPMI 0x502F
427
428/*
429 * These ID values are for the NS DP83840A 10/100 PHY
430 */
431#define NS_PHY_VENDORID 0x2000
432#define NS_PHY_83840A 0x5C0F
433
434/*
435 * Level 1 10/100 PHY
436 */
437#define LEVEL1_PHY_VENDORID 0x7810
438#define LEVEL1_PHY_LXT970 0x000F
439
440/*
441 * Intel 82555 10/100 PHY
442 */
443#define INTEL_PHY_VENDORID 0x0A28
444#define INTEL_PHY_82555 0x015F
445
446/*
447 * SEEQ 80220 10/100 PHY
448 */
449#define SEEQ_PHY_VENDORID 0x0016
450#define SEEQ_PHY_80220 0xF83F
451
452
453/*
454 * PCI low memory base and low I/O base register, and
425 * PCI low memory base and low I/O base register, and
455 * other PCI registers. Note: some are only available on
456 * the 3c905B, in particular those that related to power management.
426 * other PCI registers.
457 */
458
459#define WB_PCI_VENDOR_ID 0x00
460#define WB_PCI_DEVICE_ID 0x02
461#define WB_PCI_COMMAND 0x04
462#define WB_PCI_STATUS 0x06
463#define WB_PCI_CLASSCODE 0x09
427 */
428
429#define WB_PCI_VENDOR_ID 0x00
430#define WB_PCI_DEVICE_ID 0x02
431#define WB_PCI_COMMAND 0x04
432#define WB_PCI_STATUS 0x06
433#define WB_PCI_CLASSCODE 0x09
434#define WB_PCI_CACHELEN 0x0C
464#define WB_PCI_LATENCY_TIMER 0x0D
465#define WB_PCI_HEADER_TYPE 0x0E
466#define WB_PCI_LOIO 0x10
467#define WB_PCI_LOMEM 0x14
468#define WB_PCI_BIOSROM 0x30
469#define WB_PCI_INTLINE 0x3C
470#define WB_PCI_INTPIN 0x3D
471#define WB_PCI_MINGNT 0x3E

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482#define WB_PSTATE_MASK 0x0003
483#define WB_PSTATE_D0 0x0000
484#define WB_PSTATE_D1 0x0002
485#define WB_PSTATE_D2 0x0002
486#define WB_PSTATE_D3 0x0003
487#define WB_PME_EN 0x0010
488#define WB_PME_STATUS 0x8000
489
435#define WB_PCI_LATENCY_TIMER 0x0D
436#define WB_PCI_HEADER_TYPE 0x0E
437#define WB_PCI_LOIO 0x10
438#define WB_PCI_LOMEM 0x14
439#define WB_PCI_BIOSROM 0x30
440#define WB_PCI_INTLINE 0x3C
441#define WB_PCI_INTPIN 0x3D
442#define WB_PCI_MINGNT 0x3E

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453#define WB_PSTATE_MASK 0x0003
454#define WB_PSTATE_D0 0x0000
455#define WB_PSTATE_D1 0x0002
456#define WB_PSTATE_D2 0x0002
457#define WB_PSTATE_D3 0x0003
458#define WB_PME_EN 0x0010
459#define WB_PME_STATUS 0x8000
460
490#define PHY_UNKNOWN 6
491
492#define WB_PHYADDR_MIN 0x00
493#define WB_PHYADDR_MAX 0x1F
494
495#define PHY_BMCR 0x00
496#define PHY_BMSR 0x01
497#define PHY_VENID 0x02
498#define PHY_DEVID 0x03
499#define PHY_ANAR 0x04
500#define PHY_LPAR 0x05
501#define PHY_ANEXP 0x06
502
503#define PHY_ANAR_NEXTPAGE 0x8000
504#define PHY_ANAR_RSVD0 0x4000
505#define PHY_ANAR_TLRFLT 0x2000
506#define PHY_ANAR_RSVD1 0x1000
507#define PHY_ANAR_RSVD2 0x0800
508#define PHY_ANAR_RSVD3 0x0400
509#define PHY_ANAR_100BT4 0x0200
510#define PHY_ANAR_100BTXFULL 0x0100
511#define PHY_ANAR_100BTXHALF 0x0080
512#define PHY_ANAR_10BTFULL 0x0040
513#define PHY_ANAR_10BTHALF 0x0020
514#define PHY_ANAR_PROTO4 0x0010
515#define PHY_ANAR_PROTO3 0x0008
516#define PHY_ANAR_PROTO2 0x0004
517#define PHY_ANAR_PROTO1 0x0002
518#define PHY_ANAR_PROTO0 0x0001
519
520/*
521 * These are the register definitions for the PHY (physical layer
522 * interface chip).
523 */
524/*
525 * PHY BMCR Basic Mode Control Register
526 */
527#define PHY_BMCR_RESET 0x8000
528#define PHY_BMCR_LOOPBK 0x4000
529#define PHY_BMCR_SPEEDSEL 0x2000
530#define PHY_BMCR_AUTONEGENBL 0x1000
531#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
532#define PHY_BMCR_ISOLATE 0x0400
533#define PHY_BMCR_AUTONEGRSTR 0x0200
534#define PHY_BMCR_DUPLEX 0x0100
535#define PHY_BMCR_COLLTEST 0x0080
536#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
537#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
538#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
539#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
540#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
541#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
542#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
543/*
544 * RESET: 1 == software reset, 0 == normal operation
545 * Resets status and control registers to default values.
546 * Relatches all hardware config values.
547 *
548 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
549 *
550 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
551 * Link speed is selected byt his bit or if auto-negotiation if bit
552 * 12 (AUTONEGENBL) is set (in which case the value of this register
553 * is ignored).
554 *
555 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
556 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
557 * determine speed and mode. Should be cleared and then set if PHY configured
558 * for no autoneg on startup.
559 *
560 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
561 *
562 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
563 *
564 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
565 *
566 * COLLTEST: 1 == collision test enabled, 0 == normal operation
567 */
568
569/*
570 * PHY, BMSR Basic Mode Status Register
571 */
572#define PHY_BMSR_100BT4 0x8000
573#define PHY_BMSR_100BTXFULL 0x4000
574#define PHY_BMSR_100BTXHALF 0x2000
575#define PHY_BMSR_10BTFULL 0x1000
576#define PHY_BMSR_10BTHALF 0x0800
577#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
578#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
579#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
580#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
581#define PHY_BMSR_MFPRESUP 0x0040
582#define PHY_BMSR_AUTONEGCOMP 0x0020
583#define PHY_BMSR_REMFAULT 0x0010
584#define PHY_BMSR_CANAUTONEG 0x0008
585#define PHY_BMSR_LINKSTAT 0x0004
586#define PHY_BMSR_JABBER 0x0002
587#define PHY_BMSR_EXTENDED 0x0001
588
589#ifdef __alpha__
590#undef vtophys
591#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
592#endif
461#ifdef __alpha__
462#undef vtophys
463#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
464#endif