| if_vrreg.h (180551) | if_vrreg.h (180552) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/vr/if_vrreg.h 180551 2008-07-16 08:02:23Z yongari $ | 32 * $FreeBSD: head/sys/dev/vr/if_vrreg.h 180552 2008-07-16 08:35:29Z yongari $ |
| 33 */ 34 35/* 36 * Rhine register definitions. 37 */ 38 39#define VR_PAR0 0x00 /* node address 0 to 4 */ 40#define VR_PAR1 0x04 /* node address 2 to 6 */ 41#define VR_RXCFG 0x06 /* receiver config register */ 42#define VR_TXCFG 0x07 /* transmit config register */ 43#define VR_CR0 0x08 /* command register 0 */ 44#define VR_CR1 0x09 /* command register 1 */ 45#define VR_TQW 0x0A /* tx queue wake 6105M, 8bits */ 46#define VR_ISR 0x0C /* interrupt/status register */ 47#define VR_IMR 0x0E /* interrupt mask register */ 48#define VR_MAR0 0x10 /* multicast hash 0 */ 49#define VR_MAR1 0x14 /* multicast hash 1 */ | 33 */ 34 35/* 36 * Rhine register definitions. 37 */ 38 39#define VR_PAR0 0x00 /* node address 0 to 4 */ 40#define VR_PAR1 0x04 /* node address 2 to 6 */ 41#define VR_RXCFG 0x06 /* receiver config register */ 42#define VR_TXCFG 0x07 /* transmit config register */ 43#define VR_CR0 0x08 /* command register 0 */ 44#define VR_CR1 0x09 /* command register 1 */ 45#define VR_TQW 0x0A /* tx queue wake 6105M, 8bits */ 46#define VR_ISR 0x0C /* interrupt/status register */ 47#define VR_IMR 0x0E /* interrupt mask register */ 48#define VR_MAR0 0x10 /* multicast hash 0 */ 49#define VR_MAR1 0x14 /* multicast hash 1 */ |
| 50#define VR_MCAM0 0x10 51#define VR_MCAM1 0x11 52#define VR_MCAM2 0x12 53#define VR_MCAM3 0x13 54#define VR_MCAM4 0x14 55#define VR_MCAM5 0x15 56#define VR_VCAM0 0x16 57#define VR_VCAM1 0x17 |
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| 50#define VR_RXADDR 0x18 /* rx descriptor list start addr */ 51#define VR_TXADDR 0x1C /* tx descriptor list start addr */ 52#define VR_CURRXDESC0 0x20 53#define VR_CURRXDESC1 0x24 54#define VR_CURRXDESC2 0x28 55#define VR_CURRXDESC3 0x2C 56#define VR_NEXTRXDESC0 0x30 57#define VR_NEXTRXDESC1 0x34 --- 305 unchanged lines hidden (view full) --- 363#define VR_BCR1_TX_THRESH 0x38 364#define VR_BCR1_TXTHRESHCFG 0x00 365#define VR_BCR1_TXTHRESH64BYTES 0x08 366#define VR_BCR1_TXTHRESH128BYTES 0x10 367#define VR_BCR1_TXTHRESH256BYTES 0x18 368#define VR_BCR1_TXTHRESH512BYTES 0x20 369#define VR_BCR1_TXTHRESH1024BYTES 0x28 370#define VR_BCR1_TXTHRESHSTORENFWD 0x38 | 58#define VR_RXADDR 0x18 /* rx descriptor list start addr */ 59#define VR_TXADDR 0x1C /* tx descriptor list start addr */ 60#define VR_CURRXDESC0 0x20 61#define VR_CURRXDESC1 0x24 62#define VR_CURRXDESC2 0x28 63#define VR_CURRXDESC3 0x2C 64#define VR_NEXTRXDESC0 0x30 65#define VR_NEXTRXDESC1 0x34 --- 305 unchanged lines hidden (view full) --- 371#define VR_BCR1_TX_THRESH 0x38 372#define VR_BCR1_TXTHRESHCFG 0x00 373#define VR_BCR1_TXTHRESH64BYTES 0x08 374#define VR_BCR1_TXTHRESH128BYTES 0x10 375#define VR_BCR1_TXTHRESH256BYTES 0x18 376#define VR_BCR1_TXTHRESH512BYTES 0x20 377#define VR_BCR1_TXTHRESH1024BYTES 0x28 378#define VR_BCR1_TXTHRESHSTORENFWD 0x38 |
| 379#define VR_BCR1_VLANFILT_ENB 0x80 /* VT6105M */ |
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| 371 372/* 373 * CAMCTL register bits. (VT6105M only) 374 */ 375#define VR_CAMCTL_ENA 0x01 376#define VR_CAMCTL_VLAN 0x02 377#define VR_CAMCTL_MCAST 0x00 378#define VR_CAMCTL_WRITE 0x04 --- 367 unchanged lines hidden (view full) --- 746#define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg) 747#define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg) 748 749#define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 750#define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 751 752#define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 753#define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) | 380 381/* 382 * CAMCTL register bits. (VT6105M only) 383 */ 384#define VR_CAMCTL_ENA 0x01 385#define VR_CAMCTL_VLAN 0x02 386#define VR_CAMCTL_MCAST 0x00 387#define VR_CAMCTL_WRITE 0x04 --- 367 unchanged lines hidden (view full) --- 755#define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg) 756#define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg) 757 758#define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 759#define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 760 761#define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 762#define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) |
| 763 764#define VR_MCAST_CAM 0 765#define VR_VLAN_CAM 1 |
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