1/*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
| 1/*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
32 * $FreeBSD: head/sys/dev/vr/if_vrreg.h 180551 2008-07-16 08:02:23Z yongari $
| 32 * $FreeBSD: head/sys/dev/vr/if_vrreg.h 180552 2008-07-16 08:35:29Z yongari $
|
33 */
34
35/*
36 * Rhine register definitions.
37 */
38
39#define VR_PAR0 0x00 /* node address 0 to 4 */
40#define VR_PAR1 0x04 /* node address 2 to 6 */
41#define VR_RXCFG 0x06 /* receiver config register */
42#define VR_TXCFG 0x07 /* transmit config register */
43#define VR_CR0 0x08 /* command register 0 */
44#define VR_CR1 0x09 /* command register 1 */
45#define VR_TQW 0x0A /* tx queue wake 6105M, 8bits */
46#define VR_ISR 0x0C /* interrupt/status register */
47#define VR_IMR 0x0E /* interrupt mask register */
48#define VR_MAR0 0x10 /* multicast hash 0 */
49#define VR_MAR1 0x14 /* multicast hash 1 */
| 33 */
34
35/*
36 * Rhine register definitions.
37 */
38
39#define VR_PAR0 0x00 /* node address 0 to 4 */
40#define VR_PAR1 0x04 /* node address 2 to 6 */
41#define VR_RXCFG 0x06 /* receiver config register */
42#define VR_TXCFG 0x07 /* transmit config register */
43#define VR_CR0 0x08 /* command register 0 */
44#define VR_CR1 0x09 /* command register 1 */
45#define VR_TQW 0x0A /* tx queue wake 6105M, 8bits */
46#define VR_ISR 0x0C /* interrupt/status register */
47#define VR_IMR 0x0E /* interrupt mask register */
48#define VR_MAR0 0x10 /* multicast hash 0 */
49#define VR_MAR1 0x14 /* multicast hash 1 */
|
| 50#define VR_MCAM0 0x10
51#define VR_MCAM1 0x11
52#define VR_MCAM2 0x12
53#define VR_MCAM3 0x13
54#define VR_MCAM4 0x14
55#define VR_MCAM5 0x15
56#define VR_VCAM0 0x16
57#define VR_VCAM1 0x17
|
50#define VR_RXADDR 0x18 /* rx descriptor list start addr */
51#define VR_TXADDR 0x1C /* tx descriptor list start addr */
52#define VR_CURRXDESC0 0x20
53#define VR_CURRXDESC1 0x24
54#define VR_CURRXDESC2 0x28
55#define VR_CURRXDESC3 0x2C
56#define VR_NEXTRXDESC0 0x30
57#define VR_NEXTRXDESC1 0x34
58#define VR_NEXTRXDESC2 0x38
59#define VR_NEXTRXDESC3 0x3C
60#define VR_CURTXDESC0 0x40
61#define VR_CURTXDESC1 0x44
62#define VR_CURTXDESC2 0x48
63#define VR_CURTXDESC3 0x4C
64#define VR_NEXTTXDESC0 0x50
65#define VR_NEXTTXDESC1 0x54
66#define VR_NEXTTXDESC2 0x58
67#define VR_NEXTTXDESC3 0x5C
68#define VR_CURRXDMA 0x60 /* current RX DMA address */
69#define VR_CURTXDMA 0x64 /* current TX DMA address */
70#define VR_TALLYCNT 0x68 /* tally counter test register */
71#define VR_PHYADDR 0x6C
72#define VR_MIISTAT 0x6D
73#define VR_BCR0 0x6E
74#define VR_BCR1 0x6F
75#define VR_MIICMD 0x70
76#define VR_MIIADDR 0x71
77#define VR_MIIDATA 0x72
78#define VR_EECSR 0x74
79#define VR_TEST 0x75
80#define VR_GPIO 0x76
81#define VR_CFGA 0x78
82#define VR_CFGB 0x79
83#define VR_CFGC 0x7A
84#define VR_CFGD 0x7B
85#define VR_MPA_CNT 0x7C
86#define VR_CRC_CNT 0x7E
87#define VR_MISC_CR0 0x80 /* VT6102, 8bits */
88#define VR_MISC_CR1 0x81
89#define VR_STICKHW 0x83
90#define VR_MII_ISR 0x84
91#define VR_MII_IMR 0x86
92#define VR_CAMMASK 0x88 /* VT6105M, 32bits */
93#define VR_CAMCTL 0x92 /* VT6105M, 8bits */
94#define VR_CAMADDR 0x93 /* VT6105M, 8bits */
95#define VR_FLOWCR0 0x98
96#define VR_FLOWCR1 0x99
97#define VR_PAUSETIMER 0x9A /* 16bit */
98#define VR_WOLCR_SET 0xA0
99#define VR_PWRCFG_SET 0xA1
100#define VR_TESTREG_SET 0xA2
101#define VR_WOLCFG_SET 0xA3
102#define VR_WOLCR_CLR 0xA4
103#define VR_PWRCFG_CLR 0xA5
104#define VR_TESTREG_CLR 0xA6
105#define VR_WOLCFG_CLR 0xA7
106#define VR_PWRCSR_SET 0xA8
107#define VR_PWRCSR1_SET 0xA9
108#define VR_PWRCSR_CLR 0xAC
109#define VR_PWRCSR1_CLR 0xAD
110
111/* Misc Registers */
112#define VR_MISCCR0_RXPAUSE 0x08
113#define VR_MISCCR1_FORSRST 0x40
114
115/*
116 * RX config bits.
117 */
118#define VR_RXCFG_RX_ERRPKTS 0x01
119#define VR_RXCFG_RX_RUNT 0x02
120#define VR_RXCFG_RX_MULTI 0x04
121#define VR_RXCFG_RX_BROAD 0x08
122#define VR_RXCFG_RX_PROMISC 0x10
123#define VR_RXCFG_RX_THRESH 0xE0
124
125#define VR_RXTHRESH_32BYTES 0x00
126#define VR_RXTHRESH_64BYTES 0x20
127#define VR_RXTHRESH_128BYTES 0x40
128#define VR_RXTHRESH_256BYTES 0x60
129#define VR_RXTHRESH_512BYTES 0x80
130#define VR_RXTHRESH_768BYTES 0xA0
131#define VR_RXTHRESH_1024BYTES 0xC0
132#define VR_RXTHRESH_STORENFWD 0xE0
133
134/*
135 * TX config bits.
136 */
137#define VR_TXCFG_TXTAGEN 0x01 /* 6105M */
138#define VR_TXCFG_LOOPBKMODE 0x06
139#define VR_TXCFG_BACKOFF 0x08
140#define VR_TXCFG_RXTAGCTL 0x10 /* 6105M */
141#define VR_TXCFG_TX_THRESH 0xE0
142
143#define VR_TXTHRESH_32BYTES 0x00
144#define VR_TXTHRESH_64BYTES 0x20
145#define VR_TXTHRESH_128BYTES 0x40
146#define VR_TXTHRESH_256BYTES 0x60
147#define VR_TXTHRESH_512BYTES 0x80
148#define VR_TXTHRESH_768BYTES 0xA0
149#define VR_TXTHRESH_1024BYTES 0xC0
150#define VR_TXTHRESH_STORENFWD 0xE0
151#define VR_TXTHRESH_MIN 1 /* 64 bytes */
152#define VR_TXTHRESH_MAX 5 /* store and forward */
153
154/*
155 * Command register bits.
156 */
157#define VR_CR0_INIT 0x01
158#define VR_CR0_START 0x02
159#define VR_CR0_STOP 0x04
160#define VR_CR0_RX_ON 0x08
161#define VR_CR0_TX_ON 0x10
162#define VR_CR0_TX_GO 0x20
163#define VR_CR0_RX_GO 0x40
164#define VR_CR0_RSVD 0x80
165#define VR_CR1_RX_EARLY 0x01
166#define VR_CR1_TX_EARLY 0x02
167#define VR_CR1_FULLDUPLEX 0x04
168#define VR_CR1_TX_NOPOLL 0x08
169
170#define VR_CR1_RESET 0x80
171
172/*
173 * Interrupt status bits.
174 */
175#define VR_ISR_RX_OK 0x0001 /* packet rx ok */
176#define VR_ISR_TX_OK 0x0002 /* packet tx ok */
177#define VR_ISR_RX_ERR 0x0004 /* packet rx with err */
178#define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
179#define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
180#define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */
181#define VR_ISR_BUSERR 0x0040 /* PCI bus error */
182#define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */
183#define VR_ISR_RX_EARLY 0x0100 /* rx early */
184#define VR_ISR_LINKSTAT 0x0200 /* MII status change */
185#define VR_ISR_ETI 0x0200 /* Tx early (3043/3071) */
186#define VR_ISR_UDFI 0x0200 /* Tx FIFO underflow (6102) */
187#define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */
188#define VR_ISR_RX_DROPPED 0x0800
189#define VR_ISR_RX_NOBUF2 0x1000 /* Rx descriptor running up */
190#define VR_ISR_TX_ABRT2 0x2000
191#define VR_ISR_LINKSTAT2 0x4000
192#define VR_ISR_MAGICPACKET 0x8000
193
194#define VR_ISR_ERR_BITS "\20" \
195 "\3RXERR\4TXABRT\5TXUNDERRUN" \
196 "\6RXNOBUF\7BUSERR\10STATSOFLOW" \
197 "\12TXUDF\13RXOFLOW\14RXDROPPED" \
198 "\15RXNOBUF2\16TXABRT2"
199/*
200 * Interrupt mask bits.
201 */
202#define VR_IMR_RX_OK 0x0001 /* packet rx ok */
203#define VR_IMR_TX_OK 0x0002 /* packet tx ok */
204#define VR_IMR_RX_ERR 0x0004 /* packet rx with err */
205#define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
206#define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
207#define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */
208#define VR_IMR_BUSERR 0x0040 /* PCI bus error */
209#define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */
210#define VR_IMR_RX_EARLY 0x0100 /* rx early */
211#define VR_IMR_LINKSTAT 0x0200 /* MII status change */
212#define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */
213#define VR_IMR_RX_DROPPED 0x0800
214#define VR_IMR_RX_NOBUF2 0x1000
215#define VR_IMR_TX_ABRT2 0x2000
216#define VR_IMR_LINKSTAT2 0x4000
217#define VR_IMR_MAGICPACKET 0x8000
218
219#define VR_INTRS \
220 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \
221 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \
222 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED)
223
224/*
225 * MII status register.
226 */
227
228#define VR_MIISTAT_SPEED 0x01
229#define VR_MIISTAT_LINKFAULT 0x02
230#define VR_MIISTAT_MGTREADERR 0x04
231#define VR_MIISTAT_MIIERR 0x08
232#define VR_MIISTAT_PHYOPT 0x10
233#define VR_MIISTAT_MDC_SPEED 0x20
234#define VR_MIISTAT_RSVD 0x40
235#define VR_MIISTAT_GPIO1POLL 0x80
236
237/*
238 * MII command register bits.
239 */
240#define VR_MIICMD_CLK 0x01
241#define VR_MIICMD_DATAOUT 0x02
242#define VR_MIICMD_DATAIN 0x04
243#define VR_MIICMD_DIR 0x08
244#define VR_MIICMD_DIRECTPGM 0x10
245#define VR_MIICMD_WRITE_ENB 0x20
246#define VR_MIICMD_READ_ENB 0x40
247#define VR_MIICMD_AUTOPOLL 0x80
248
249/*
250 * EEPROM control bits.
251 */
252#define VR_EECSR_DATAIN 0x01 /* data out */
253#define VR_EECSR_DATAOUT 0x02 /* data in */
254#define VR_EECSR_CLK 0x04 /* clock */
255#define VR_EECSR_CS 0x08 /* chip select */
256#define VR_EECSR_DPM 0x10
257#define VR_EECSR_LOAD 0x20
258#define VR_EECSR_EMBP 0x40
259#define VR_EECSR_EEPR 0x80
260
261#define VR_EECMD_WRITE 0x140
262#define VR_EECMD_READ 0x180
263#define VR_EECMD_ERASE 0x1c0
264
265/*
266 * Test register bits.
267 */
268#define VR_TEST_TEST0 0x01
269#define VR_TEST_TEST1 0x02
270#define VR_TEST_TEST2 0x04
271#define VR_TEST_TSTUD 0x08
272#define VR_TEST_TSTOV 0x10
273#define VR_TEST_BKOFF 0x20
274#define VR_TEST_FCOL 0x40
275#define VR_TEST_HBDES 0x80
276
277/*
278 * Config A register bits.
279 */
280#define VR_CFG_GPIO2OUTENB 0x01
281#define VR_CFG_GPIO2OUT 0x02 /* gen. purp. pin */
282#define VR_CFG_GPIO2IN 0x04 /* gen. purp. pin */
283#define VR_CFG_AUTOOPT 0x08 /* enable rx/tx autopoll */
284#define VR_CFG_MIIOPT 0x10
285#define VR_CFG_MMIENB 0x20 /* memory mapped mode enb */
286#define VR_CFG_JUMPER 0x40 /* PHY and oper. mode select */
287#define VR_CFG_EELOAD 0x80 /* enable EEPROM programming */
288
289/*
290 * Config B register bits.
291 */
292#define VR_CFG_LATMENB 0x01 /* larency timer effect enb. */
293#define VR_CFG_MRREADWAIT 0x02
294#define VR_CFG_MRWRITEWAIT 0x04
295#define VR_CFG_RX_ARB 0x08
296#define VR_CFG_TX_ARB 0x10
297#define VR_CFG_READMULTI 0x20
298#define VR_CFG_TX_PACE 0x40
299#define VR_CFG_TX_QDIS 0x80
300
301/*
302 * Config C register bits.
303 */
304#define VR_CFG_ROMSEL0 0x01
305#define VR_CFG_ROMSEL1 0x02
306#define VR_CFG_ROMSEL2 0x04
307#define VR_CFG_ROMTIMESEL 0x08
308#define VR_CFG_RSVD0 0x10
309#define VR_CFG_ROMDLY 0x20
310#define VR_CFG_ROMOPT 0x40
311#define VR_CFG_RSVD1 0x80
312
313/*
314 * Config D register bits.
315 */
316#define VR_CFG_BACKOFFOPT 0x01
317#define VR_CFG_BACKOFFMOD 0x02
318#define VR_CFG_CAPEFFECT 0x04
319#define VR_CFG_BACKOFFRAND 0x08
320#define VR_CFG_MAGICKPACKET 0x10
321#define VR_CFG_PCIREADLINE 0x20
322#define VR_CFG_DIAG 0x40
323#define VR_CFG_GPIOEN 0x80
324
325/* Sticky HW bits */
326#define VR_STICKHW_DS0 0x01
327#define VR_STICKHW_DS1 0x02
328#define VR_STICKHW_WOL_ENB 0x04
329#define VR_STICKHW_WOL_STS 0x08
330#define VR_STICKHW_LEGWOL_ENB 0x80
331
332/*
333 * BCR0 register bits. (At least for the VT6102 chip.)
334 */
335#define VR_BCR0_DMA_LENGTH 0x07
336
337#define VR_BCR0_DMA_32BYTES 0x00
338#define VR_BCR0_DMA_64BYTES 0x01
339#define VR_BCR0_DMA_128BYTES 0x02
340#define VR_BCR0_DMA_256BYTES 0x03
341#define VR_BCR0_DMA_512BYTES 0x04
342#define VR_BCR0_DMA_1024BYTES 0x05
343#define VR_BCR0_DMA_STORENFWD 0x07
344
345#define VR_BCR0_RX_THRESH 0x38
346
347#define VR_BCR0_RXTHRESHCFG 0x00
348#define VR_BCR0_RXTHRESH64BYTES 0x08
349#define VR_BCR0_RXTHRESH128BYTES 0x10
350#define VR_BCR0_RXTHRESH256BYTES 0x18
351#define VR_BCR0_RXTHRESH512BYTES 0x20
352#define VR_BCR0_RXTHRESH1024BYTES 0x28
353#define VR_BCR0_RXTHRESHSTORENFWD 0x38
354#define VR_BCR0_EXTLED 0x40
355#define VR_BCR0_MED2 0x80
356
357/*
358 * BCR1 register bits. (At least for the VT6102 chip.)
359 */
360#define VR_BCR1_POT0 0x01
361#define VR_BCR1_POT1 0x02
362#define VR_BCR1_POT2 0x04
363#define VR_BCR1_TX_THRESH 0x38
364#define VR_BCR1_TXTHRESHCFG 0x00
365#define VR_BCR1_TXTHRESH64BYTES 0x08
366#define VR_BCR1_TXTHRESH128BYTES 0x10
367#define VR_BCR1_TXTHRESH256BYTES 0x18
368#define VR_BCR1_TXTHRESH512BYTES 0x20
369#define VR_BCR1_TXTHRESH1024BYTES 0x28
370#define VR_BCR1_TXTHRESHSTORENFWD 0x38
| 58#define VR_RXADDR 0x18 /* rx descriptor list start addr */
59#define VR_TXADDR 0x1C /* tx descriptor list start addr */
60#define VR_CURRXDESC0 0x20
61#define VR_CURRXDESC1 0x24
62#define VR_CURRXDESC2 0x28
63#define VR_CURRXDESC3 0x2C
64#define VR_NEXTRXDESC0 0x30
65#define VR_NEXTRXDESC1 0x34
66#define VR_NEXTRXDESC2 0x38
67#define VR_NEXTRXDESC3 0x3C
68#define VR_CURTXDESC0 0x40
69#define VR_CURTXDESC1 0x44
70#define VR_CURTXDESC2 0x48
71#define VR_CURTXDESC3 0x4C
72#define VR_NEXTTXDESC0 0x50
73#define VR_NEXTTXDESC1 0x54
74#define VR_NEXTTXDESC2 0x58
75#define VR_NEXTTXDESC3 0x5C
76#define VR_CURRXDMA 0x60 /* current RX DMA address */
77#define VR_CURTXDMA 0x64 /* current TX DMA address */
78#define VR_TALLYCNT 0x68 /* tally counter test register */
79#define VR_PHYADDR 0x6C
80#define VR_MIISTAT 0x6D
81#define VR_BCR0 0x6E
82#define VR_BCR1 0x6F
83#define VR_MIICMD 0x70
84#define VR_MIIADDR 0x71
85#define VR_MIIDATA 0x72
86#define VR_EECSR 0x74
87#define VR_TEST 0x75
88#define VR_GPIO 0x76
89#define VR_CFGA 0x78
90#define VR_CFGB 0x79
91#define VR_CFGC 0x7A
92#define VR_CFGD 0x7B
93#define VR_MPA_CNT 0x7C
94#define VR_CRC_CNT 0x7E
95#define VR_MISC_CR0 0x80 /* VT6102, 8bits */
96#define VR_MISC_CR1 0x81
97#define VR_STICKHW 0x83
98#define VR_MII_ISR 0x84
99#define VR_MII_IMR 0x86
100#define VR_CAMMASK 0x88 /* VT6105M, 32bits */
101#define VR_CAMCTL 0x92 /* VT6105M, 8bits */
102#define VR_CAMADDR 0x93 /* VT6105M, 8bits */
103#define VR_FLOWCR0 0x98
104#define VR_FLOWCR1 0x99
105#define VR_PAUSETIMER 0x9A /* 16bit */
106#define VR_WOLCR_SET 0xA0
107#define VR_PWRCFG_SET 0xA1
108#define VR_TESTREG_SET 0xA2
109#define VR_WOLCFG_SET 0xA3
110#define VR_WOLCR_CLR 0xA4
111#define VR_PWRCFG_CLR 0xA5
112#define VR_TESTREG_CLR 0xA6
113#define VR_WOLCFG_CLR 0xA7
114#define VR_PWRCSR_SET 0xA8
115#define VR_PWRCSR1_SET 0xA9
116#define VR_PWRCSR_CLR 0xAC
117#define VR_PWRCSR1_CLR 0xAD
118
119/* Misc Registers */
120#define VR_MISCCR0_RXPAUSE 0x08
121#define VR_MISCCR1_FORSRST 0x40
122
123/*
124 * RX config bits.
125 */
126#define VR_RXCFG_RX_ERRPKTS 0x01
127#define VR_RXCFG_RX_RUNT 0x02
128#define VR_RXCFG_RX_MULTI 0x04
129#define VR_RXCFG_RX_BROAD 0x08
130#define VR_RXCFG_RX_PROMISC 0x10
131#define VR_RXCFG_RX_THRESH 0xE0
132
133#define VR_RXTHRESH_32BYTES 0x00
134#define VR_RXTHRESH_64BYTES 0x20
135#define VR_RXTHRESH_128BYTES 0x40
136#define VR_RXTHRESH_256BYTES 0x60
137#define VR_RXTHRESH_512BYTES 0x80
138#define VR_RXTHRESH_768BYTES 0xA0
139#define VR_RXTHRESH_1024BYTES 0xC0
140#define VR_RXTHRESH_STORENFWD 0xE0
141
142/*
143 * TX config bits.
144 */
145#define VR_TXCFG_TXTAGEN 0x01 /* 6105M */
146#define VR_TXCFG_LOOPBKMODE 0x06
147#define VR_TXCFG_BACKOFF 0x08
148#define VR_TXCFG_RXTAGCTL 0x10 /* 6105M */
149#define VR_TXCFG_TX_THRESH 0xE0
150
151#define VR_TXTHRESH_32BYTES 0x00
152#define VR_TXTHRESH_64BYTES 0x20
153#define VR_TXTHRESH_128BYTES 0x40
154#define VR_TXTHRESH_256BYTES 0x60
155#define VR_TXTHRESH_512BYTES 0x80
156#define VR_TXTHRESH_768BYTES 0xA0
157#define VR_TXTHRESH_1024BYTES 0xC0
158#define VR_TXTHRESH_STORENFWD 0xE0
159#define VR_TXTHRESH_MIN 1 /* 64 bytes */
160#define VR_TXTHRESH_MAX 5 /* store and forward */
161
162/*
163 * Command register bits.
164 */
165#define VR_CR0_INIT 0x01
166#define VR_CR0_START 0x02
167#define VR_CR0_STOP 0x04
168#define VR_CR0_RX_ON 0x08
169#define VR_CR0_TX_ON 0x10
170#define VR_CR0_TX_GO 0x20
171#define VR_CR0_RX_GO 0x40
172#define VR_CR0_RSVD 0x80
173#define VR_CR1_RX_EARLY 0x01
174#define VR_CR1_TX_EARLY 0x02
175#define VR_CR1_FULLDUPLEX 0x04
176#define VR_CR1_TX_NOPOLL 0x08
177
178#define VR_CR1_RESET 0x80
179
180/*
181 * Interrupt status bits.
182 */
183#define VR_ISR_RX_OK 0x0001 /* packet rx ok */
184#define VR_ISR_TX_OK 0x0002 /* packet tx ok */
185#define VR_ISR_RX_ERR 0x0004 /* packet rx with err */
186#define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
187#define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
188#define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */
189#define VR_ISR_BUSERR 0x0040 /* PCI bus error */
190#define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */
191#define VR_ISR_RX_EARLY 0x0100 /* rx early */
192#define VR_ISR_LINKSTAT 0x0200 /* MII status change */
193#define VR_ISR_ETI 0x0200 /* Tx early (3043/3071) */
194#define VR_ISR_UDFI 0x0200 /* Tx FIFO underflow (6102) */
195#define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */
196#define VR_ISR_RX_DROPPED 0x0800
197#define VR_ISR_RX_NOBUF2 0x1000 /* Rx descriptor running up */
198#define VR_ISR_TX_ABRT2 0x2000
199#define VR_ISR_LINKSTAT2 0x4000
200#define VR_ISR_MAGICPACKET 0x8000
201
202#define VR_ISR_ERR_BITS "\20" \
203 "\3RXERR\4TXABRT\5TXUNDERRUN" \
204 "\6RXNOBUF\7BUSERR\10STATSOFLOW" \
205 "\12TXUDF\13RXOFLOW\14RXDROPPED" \
206 "\15RXNOBUF2\16TXABRT2"
207/*
208 * Interrupt mask bits.
209 */
210#define VR_IMR_RX_OK 0x0001 /* packet rx ok */
211#define VR_IMR_TX_OK 0x0002 /* packet tx ok */
212#define VR_IMR_RX_ERR 0x0004 /* packet rx with err */
213#define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
214#define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
215#define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */
216#define VR_IMR_BUSERR 0x0040 /* PCI bus error */
217#define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */
218#define VR_IMR_RX_EARLY 0x0100 /* rx early */
219#define VR_IMR_LINKSTAT 0x0200 /* MII status change */
220#define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */
221#define VR_IMR_RX_DROPPED 0x0800
222#define VR_IMR_RX_NOBUF2 0x1000
223#define VR_IMR_TX_ABRT2 0x2000
224#define VR_IMR_LINKSTAT2 0x4000
225#define VR_IMR_MAGICPACKET 0x8000
226
227#define VR_INTRS \
228 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \
229 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \
230 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED)
231
232/*
233 * MII status register.
234 */
235
236#define VR_MIISTAT_SPEED 0x01
237#define VR_MIISTAT_LINKFAULT 0x02
238#define VR_MIISTAT_MGTREADERR 0x04
239#define VR_MIISTAT_MIIERR 0x08
240#define VR_MIISTAT_PHYOPT 0x10
241#define VR_MIISTAT_MDC_SPEED 0x20
242#define VR_MIISTAT_RSVD 0x40
243#define VR_MIISTAT_GPIO1POLL 0x80
244
245/*
246 * MII command register bits.
247 */
248#define VR_MIICMD_CLK 0x01
249#define VR_MIICMD_DATAOUT 0x02
250#define VR_MIICMD_DATAIN 0x04
251#define VR_MIICMD_DIR 0x08
252#define VR_MIICMD_DIRECTPGM 0x10
253#define VR_MIICMD_WRITE_ENB 0x20
254#define VR_MIICMD_READ_ENB 0x40
255#define VR_MIICMD_AUTOPOLL 0x80
256
257/*
258 * EEPROM control bits.
259 */
260#define VR_EECSR_DATAIN 0x01 /* data out */
261#define VR_EECSR_DATAOUT 0x02 /* data in */
262#define VR_EECSR_CLK 0x04 /* clock */
263#define VR_EECSR_CS 0x08 /* chip select */
264#define VR_EECSR_DPM 0x10
265#define VR_EECSR_LOAD 0x20
266#define VR_EECSR_EMBP 0x40
267#define VR_EECSR_EEPR 0x80
268
269#define VR_EECMD_WRITE 0x140
270#define VR_EECMD_READ 0x180
271#define VR_EECMD_ERASE 0x1c0
272
273/*
274 * Test register bits.
275 */
276#define VR_TEST_TEST0 0x01
277#define VR_TEST_TEST1 0x02
278#define VR_TEST_TEST2 0x04
279#define VR_TEST_TSTUD 0x08
280#define VR_TEST_TSTOV 0x10
281#define VR_TEST_BKOFF 0x20
282#define VR_TEST_FCOL 0x40
283#define VR_TEST_HBDES 0x80
284
285/*
286 * Config A register bits.
287 */
288#define VR_CFG_GPIO2OUTENB 0x01
289#define VR_CFG_GPIO2OUT 0x02 /* gen. purp. pin */
290#define VR_CFG_GPIO2IN 0x04 /* gen. purp. pin */
291#define VR_CFG_AUTOOPT 0x08 /* enable rx/tx autopoll */
292#define VR_CFG_MIIOPT 0x10
293#define VR_CFG_MMIENB 0x20 /* memory mapped mode enb */
294#define VR_CFG_JUMPER 0x40 /* PHY and oper. mode select */
295#define VR_CFG_EELOAD 0x80 /* enable EEPROM programming */
296
297/*
298 * Config B register bits.
299 */
300#define VR_CFG_LATMENB 0x01 /* larency timer effect enb. */
301#define VR_CFG_MRREADWAIT 0x02
302#define VR_CFG_MRWRITEWAIT 0x04
303#define VR_CFG_RX_ARB 0x08
304#define VR_CFG_TX_ARB 0x10
305#define VR_CFG_READMULTI 0x20
306#define VR_CFG_TX_PACE 0x40
307#define VR_CFG_TX_QDIS 0x80
308
309/*
310 * Config C register bits.
311 */
312#define VR_CFG_ROMSEL0 0x01
313#define VR_CFG_ROMSEL1 0x02
314#define VR_CFG_ROMSEL2 0x04
315#define VR_CFG_ROMTIMESEL 0x08
316#define VR_CFG_RSVD0 0x10
317#define VR_CFG_ROMDLY 0x20
318#define VR_CFG_ROMOPT 0x40
319#define VR_CFG_RSVD1 0x80
320
321/*
322 * Config D register bits.
323 */
324#define VR_CFG_BACKOFFOPT 0x01
325#define VR_CFG_BACKOFFMOD 0x02
326#define VR_CFG_CAPEFFECT 0x04
327#define VR_CFG_BACKOFFRAND 0x08
328#define VR_CFG_MAGICKPACKET 0x10
329#define VR_CFG_PCIREADLINE 0x20
330#define VR_CFG_DIAG 0x40
331#define VR_CFG_GPIOEN 0x80
332
333/* Sticky HW bits */
334#define VR_STICKHW_DS0 0x01
335#define VR_STICKHW_DS1 0x02
336#define VR_STICKHW_WOL_ENB 0x04
337#define VR_STICKHW_WOL_STS 0x08
338#define VR_STICKHW_LEGWOL_ENB 0x80
339
340/*
341 * BCR0 register bits. (At least for the VT6102 chip.)
342 */
343#define VR_BCR0_DMA_LENGTH 0x07
344
345#define VR_BCR0_DMA_32BYTES 0x00
346#define VR_BCR0_DMA_64BYTES 0x01
347#define VR_BCR0_DMA_128BYTES 0x02
348#define VR_BCR0_DMA_256BYTES 0x03
349#define VR_BCR0_DMA_512BYTES 0x04
350#define VR_BCR0_DMA_1024BYTES 0x05
351#define VR_BCR0_DMA_STORENFWD 0x07
352
353#define VR_BCR0_RX_THRESH 0x38
354
355#define VR_BCR0_RXTHRESHCFG 0x00
356#define VR_BCR0_RXTHRESH64BYTES 0x08
357#define VR_BCR0_RXTHRESH128BYTES 0x10
358#define VR_BCR0_RXTHRESH256BYTES 0x18
359#define VR_BCR0_RXTHRESH512BYTES 0x20
360#define VR_BCR0_RXTHRESH1024BYTES 0x28
361#define VR_BCR0_RXTHRESHSTORENFWD 0x38
362#define VR_BCR0_EXTLED 0x40
363#define VR_BCR0_MED2 0x80
364
365/*
366 * BCR1 register bits. (At least for the VT6102 chip.)
367 */
368#define VR_BCR1_POT0 0x01
369#define VR_BCR1_POT1 0x02
370#define VR_BCR1_POT2 0x04
371#define VR_BCR1_TX_THRESH 0x38
372#define VR_BCR1_TXTHRESHCFG 0x00
373#define VR_BCR1_TXTHRESH64BYTES 0x08
374#define VR_BCR1_TXTHRESH128BYTES 0x10
375#define VR_BCR1_TXTHRESH256BYTES 0x18
376#define VR_BCR1_TXTHRESH512BYTES 0x20
377#define VR_BCR1_TXTHRESH1024BYTES 0x28
378#define VR_BCR1_TXTHRESHSTORENFWD 0x38
|
| 379#define VR_BCR1_VLANFILT_ENB 0x80 /* VT6105M */
|
371
372/*
373 * CAMCTL register bits. (VT6105M only)
374 */
375#define VR_CAMCTL_ENA 0x01
376#define VR_CAMCTL_VLAN 0x02
377#define VR_CAMCTL_MCAST 0x00
378#define VR_CAMCTL_WRITE 0x04
379#define VR_CAMCTL_READ 0x08
380
381#define VR_CAM_MCAST_CNT 32
382#define VR_CAM_VLAN_CNT 32
383
384/*
385 * FLOWCR1 register bits. (VT6105LOM, VT6105M only)
386 */
387#define VR_FLOWCR1_TXLO4 0x00
388#define VR_FLOWCR1_TXLO8 0x40
389#define VR_FLOWCR1_TXLO16 0x80
390#define VR_FLOWCR1_TXLO24 0xC0
391#define VR_FLOWCR1_TXHI24 0x00
392#define VR_FLOWCR1_TXHI32 0x10
393#define VR_FLOWCR1_TXHI48 0x20
394#define VR_FLOWCR1_TXHI64 0x30
395#define VR_FLOWCR1_XONXOFF 0x08
396#define VR_FLOWCR1_TXPAUSE 0x04
397#define VR_FLOWCR1_RXPAUSE 0x02
398#define VR_FLOWCR1_HDX 0x01
399
400/*
401 * WOLCR register bits. (VT6102 or higher only)
402 */
403#define VR_WOLCR_PATTERN0 0x01
404#define VR_WOLCR_PATTERN1 0x02
405#define VR_WOLCR_PATTERN2 0x04
406#define VR_WOLCR_PATTERN3 0x08
407#define VR_WOLCR_UCAST 0x10
408#define VR_WOLCR_MAGIC 0x20
409#define VR_WOLCR_LINKON 0x40
410#define VR_WOLCR_LINKOFF 0x80
411
412/*
413 * PWRCFG register bits. (VT6102 or higher only)
414 */
415#define VR_PWRCFG_WOLEN 0x01
416#define VR_PWRCFG_WOLSR 0x02
417#define VR_PWRCFG_LEGACY_WOL 0x10
418#define VR_PWRCFG_WOLTYPE_PULSE 0x20
419#define VR_PWRCFG_SMIITIME 0x80
420
421/*
422 * WOLCFG register bits. (VT6102 or higher only)
423 */
424#define VR_WOLCFG_PATTERN_PAGE 0x04 /* VT6505 B0 */
425#define VR_WOLCFG_SMIIOPT 0x04
426#define VR_WOLCFG_SMIIACC 0x08
427#define VR_WOLCFG_SAB 0x10
428#define VR_WOLCFG_SAM 0x20
429#define VR_WOLCFG_SFDX 0x40
430#define VR_WOLCFG_PMEOVR 0x80
431
432/*
433 * Rhine TX/RX list structure.
434 */
435
436struct vr_desc {
437 uint32_t vr_status;
438 uint32_t vr_ctl;
439 uint32_t vr_data;
440 uint32_t vr_nextphys;
441};
442
443#define VR_RXSTAT_RXERR 0x00000001
444#define VR_RXSTAT_CRCERR 0x00000002
445#define VR_RXSTAT_FRAMEALIGNERR 0x00000004
446#define VR_RXSTAT_FIFOOFLOW 0x00000008
447#define VR_RXSTAT_GIANT 0x00000010
448#define VR_RXSTAT_RUNT 0x00000020
449#define VR_RXSTAT_BUSERR 0x00000040
450#define VR_RXSTAT_FRAG 0x00000040 /* 6105M */
451#define VR_RXSTAT_BUFFERR 0x00000080
452#define VR_RXSTAT_LASTFRAG 0x00000100
453#define VR_RXSTAT_FIRSTFRAG 0x00000200
454#define VR_RXSTAT_RLINK 0x00000400
455#define VR_RXSTAT_RX_PHYS 0x00000800
456#define VR_RXSTAT_RX_BROAD 0x00001000
457#define VR_RXSTAT_RX_MULTI 0x00002000
458#define VR_RXSTAT_RX_VIDHIT 0x00004000 /* 6105M */
459#define VR_RXSTAT_RX_OK 0x00008000
460#define VR_RXSTAT_RXLEN 0x07FF0000
461#define VR_RXSTAT_RXLEN_EXT 0x78000000
462#define VR_RXSTAT_OWN 0x80000000
463
464#define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16)
465#define VR_RXSTAT_ERR_BITS "\20" \
466 "\1RXERR\2CRCERR\3FRAMEALIGN" \
467 "\4FIFOOFLOW\5GIANT\6RUNT" \
468 "\10BUFERR"
469
470#define VR_RXCTL_BUFLEN 0x000007FF
471#define VR_RXCTL_BUFLEN_EXT 0x00007800
472#define VR_RXCTL_CHAIN 0x00008000
473#define VR_RXCTL_TAG 0x00010000
474#define VR_RXCTL_UDP 0x00020000
475#define VR_RXCTL_TCP 0x00040000
476#define VR_RXCTL_IP 0x00080000
477#define VR_RXCTL_TCPUDPOK 0x00100000
478#define VR_RXCTL_IPOK 0x00200000
479#define VR_RXCTL_SNAPTAG 0x00400000
480#define VR_RXCTL_RXLERR 0x00800000 /* 6105M */
481#define VR_RXCTL_RX_INTR 0x00800000
482
483
484#define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR)
485
486#define VR_TXSTAT_DEFER 0x00000001
487#define VR_TXSTAT_UNDERRUN 0x00000002
488#define VR_TXSTAT_COLLCNT 0x00000078
489#define VR_TXSTAT_SQE 0x00000080
490#define VR_TXSTAT_ABRT 0x00000100
491#define VR_TXSTAT_LATECOLL 0x00000200
492#define VR_TXSTAT_CARRLOST 0x00000400
493#define VR_TXSTAT_UDF 0x00000800
494#define VR_TXSTAT_TBUFF 0x00001000
495#define VR_TXSTAT_BUSERR 0x00002000
496#define VR_TXSTAT_JABTIMEO 0x00004000
497#define VR_TXSTAT_ERRSUM 0x00008000
498#define VR_TXSTAT_OWN 0x80000000
499
500#define VR_TXCTL_BUFLEN 0x000007FF
501#define VR_TXCTL_BUFLEN_EXT 0x00007800
502#define VR_TXCTL_TLINK 0x00008000
503#define VR_TXCTL_NOCRC 0x00010000
504#define VR_TXCTL_INSERTTAG 0x00020000
505#define VR_TXCTL_IPCSUM 0x00040000
506#define VR_TXCTL_UDPCSUM 0x00080000
507#define VR_TXCTL_TCPCSUM 0x00100000
508#define VR_TXCTL_FIRSTFRAG 0x00200000
509#define VR_TXCTL_LASTFRAG 0x00400000
510#define VR_TXCTL_FINT 0x00800000
511
512#define VR_MIN_FRAMELEN 60
513
514#define VR_FLAG_FORCEDELAY 1
515#define VR_FLAG_SCHEDDELAY 2
516#define VR_FLAG_DELAYTIMEO 3
517
518
519#define VR_TIMEOUT 1000
520#define VR_MII_TIMEOUT 10000
521
522#define VR_PHYADDR_MASK 0x1f
523
524/*
525 * General constants that are fun to know.
526 *
527 * VIA vendor ID
528 */
529#define VIA_VENDORID 0x1106
530
531/*
532 * VIA Rhine device IDs.
533 */
534#define VIA_DEVICEID_RHINE 0x3043
535#define VIA_DEVICEID_RHINE_II 0x6100
536#define VIA_DEVICEID_RHINE_II_2 0x3065
537#define VIA_DEVICEID_RHINE_III 0x3106
538#define VIA_DEVICEID_RHINE_III_M 0x3053
539
540/*
541 * Delta Electronics device ID.
542 */
543#define DELTA_VENDORID 0x1500
544
545/*
546 * Delta device IDs.
547 */
548#define DELTA_DEVICEID_RHINE_II 0x1320
549
550/*
551 * Addtron vendor ID.
552 */
553#define ADDTRON_VENDORID 0x4033
554
555/*
556 * Addtron device IDs.
557 */
558#define ADDTRON_DEVICEID_RHINE_II 0x1320
559
560/*
561 * VIA Rhine revision IDs
562 */
563
564#define REV_ID_VT3043_E 0x04
565#define REV_ID_VT3071_A 0x20
566#define REV_ID_VT3071_B 0x21
567#define REV_ID_VT6102_A 0x40
568#define REV_ID_VT6102_B 0x41
569#define REV_ID_VT6102_C 0x42
570#define REV_ID_VT6102_APOLLO 0x74
571#define REV_ID_VT6105_A0 0x80
572#define REV_ID_VT6105_B0 0x83
573#define REV_ID_VT6105_LOM 0x8A
574#define REV_ID_VT6107_A0 0x8C
575#define REV_ID_VT6107_A1 0x8D
576#define REV_ID_VT6105M_A0 0x90
577#define REV_ID_VT6105M_B1 0x94
578
579/*
580 * PCI low memory base and low I/O base register, and
581 * other PCI registers.
582 */
583
584#define VR_PCI_VENDOR_ID 0x00
585#define VR_PCI_DEVICE_ID 0x02
586#define VR_PCI_COMMAND 0x04
587#define VR_PCI_STATUS 0x06
588#define VR_PCI_REVID 0x08
589#define VR_PCI_CLASSCODE 0x09
590#define VR_PCI_LATENCY_TIMER 0x0D
591#define VR_PCI_HEADER_TYPE 0x0E
592#define VR_PCI_LOIO 0x10
593#define VR_PCI_LOMEM 0x14
594#define VR_PCI_BIOSROM 0x30
595#define VR_PCI_INTLINE 0x3C
596#define VR_PCI_INTPIN 0x3D
597#define VR_PCI_MINGNT 0x3E
598#define VR_PCI_MINLAT 0x0F
599#define VR_PCI_RESETOPT 0x48
600#define VR_PCI_EEPROM_DATA 0x4C
601#define VR_PCI_MODE0 0x50
602#define VR_PCI_MODE2 0x52
603#define VR_PCI_MODE3 0x53
604
605#define VR_MODE2_PCEROPT 0x80 /* VT6102 only */
606#define VR_MODE2_DISABT 0x40
607#define VR_MODE2_MRDPL 0x08 /* VT6107A1 and above */
608#define VR_MODE2_MODE10T 0x02
609
610#define VR_MODE3_XONOPT 0x80
611#define VR_MODE3_TPACEN 0x40
612#define VR_MODE3_BACKOPT 0x20
613#define VR_MODE3_DLTSEL 0x10
614#define VR_MODE3_MIIDMY 0x08
615#define VR_MODE3_MIION 0x04
616
617/* power management registers */
618#define VR_PCI_CAPID 0xDC /* 8 bits */
619#define VR_PCI_NEXTPTR 0xDD /* 8 bits */
620#define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */
621#define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
622
623#define VR_PSTATE_MASK 0x0003
624#define VR_PSTATE_D0 0x0000
625#define VR_PSTATE_D1 0x0002
626#define VR_PSTATE_D2 0x0002
627#define VR_PSTATE_D3 0x0003
628#define VR_PME_EN 0x0010
629#define VR_PME_STATUS 0x8000
630
631#define VR_RX_RING_CNT 128
632#define VR_TX_RING_CNT 128
633#define VR_TX_RING_SIZE sizeof(struct vr_desc) * VR_TX_RING_CNT
634#define VR_RX_RING_SIZE sizeof(struct vr_desc) * VR_RX_RING_CNT
635#define VR_RING_ALIGN sizeof(struct vr_desc)
636#define VR_RX_ALIGN sizeof(uint32_t)
637#define VR_MAXFRAGS 8
638#define VR_TX_INTR_THRESH 8
639
640#define VR_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff)
641#define VR_ADDR_HI(x) ((uint64_t)(x) >> 32)
642#define VR_TX_RING_ADDR(sc, i) \
643 ((sc)->vr_rdata.vr_tx_ring_paddr + sizeof(struct vr_desc) * (i))
644#define VR_RX_RING_ADDR(sc, i) \
645 ((sc)->vr_rdata.vr_rx_ring_paddr + sizeof(struct vr_desc) * (i))
646#define VR_INC(x,y) (x) = (((x) + 1) % y)
647
648struct vr_txdesc {
649 struct mbuf *tx_m;
650 bus_dmamap_t tx_dmamap;
651};
652
653struct vr_rxdesc {
654 struct mbuf *rx_m;
655 bus_dmamap_t rx_dmamap;
656 struct vr_desc *desc;
657};
658
659struct vr_chain_data {
660 bus_dma_tag_t vr_parent_tag;
661 bus_dma_tag_t vr_tx_tag;
662 struct vr_txdesc vr_txdesc[VR_TX_RING_CNT];
663 bus_dma_tag_t vr_rx_tag;
664 struct vr_rxdesc vr_rxdesc[VR_RX_RING_CNT];
665 bus_dma_tag_t vr_tx_ring_tag;
666 bus_dma_tag_t vr_rx_ring_tag;
667 bus_dmamap_t vr_tx_ring_map;
668 bus_dmamap_t vr_rx_ring_map;
669 bus_dmamap_t vr_rx_sparemap;
670 int vr_tx_pkts;
671 int vr_tx_prod;
672 int vr_tx_cons;
673 int vr_tx_cnt;
674 int vr_rx_cons;
675};
676
677struct vr_ring_data {
678 struct vr_desc *vr_rx_ring;
679 struct vr_desc *vr_tx_ring;
680 bus_addr_t vr_rx_ring_paddr;
681 bus_addr_t vr_tx_ring_paddr;
682};
683
684struct vr_statistics {
685 uint64_t tx_ok;
686 uint64_t rx_ok;
687 uint32_t tx_errors;
688 uint32_t rx_errors;
689 uint32_t rx_no_buffers;
690 uint32_t rx_no_mbufs;
691 uint32_t rx_crc_errors;
692 uint32_t rx_alignment;
693 uint32_t rx_fifo_overflows;
694 uint32_t rx_giants;
695 uint32_t rx_runts;
696 uint32_t tx_abort;
697 uint32_t tx_collisions;
698 uint32_t tx_late_collisions;
699 uint32_t tx_underrun;
700 uint32_t bus_errors;
701 uint32_t num_restart;
702};
703
704struct vr_softc {
705 struct ifnet *vr_ifp; /* interface info */
706 device_t vr_dev;
707 struct resource *vr_res;
708 int vr_res_id;
709 int vr_res_type;
710 struct resource *vr_irq;
711 void *vr_intrhand;
712 device_t vr_miibus;
713 uint8_t vr_revid; /* Rhine chip revision */
714 uint8_t vr_flags; /* See VR_F_* below */
715#define VR_F_RESTART 0x01 /* Restart unit on next tick */
716 int vr_phyaddr;
717 int vr_if_flags;
718 struct task vr_link_task;
719 struct vr_chain_data vr_cdata;
720 struct vr_ring_data vr_rdata;
721 struct vr_statistics vr_stat;
722 struct callout vr_stat_callout;
723 struct mtx vr_mtx;
724 int vr_suspended; /* if 1, sleeping/detaching */
725 int vr_quirks;
726 int vr_link;
727 int vr_watchdog_timer;
728 int vr_txthresh;
729 int vr_detach;
730#ifdef DEVICE_POLLING
731 int rxcycles;
732#endif
733};
734
735#define VR_LOCK(_sc) mtx_lock(&(_sc)->vr_mtx)
736#define VR_UNLOCK(_sc) mtx_unlock(&(_sc)->vr_mtx)
737#define VR_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vr_mtx, MA_OWNED)
738
739/*
740 * register space access macros
741 */
742#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->vr_res, reg, val)
743#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val)
744#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->vr_res, reg, val)
745
746#define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg)
747#define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg)
748
749#define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
750#define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
751
752#define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
753#define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
| 380
381/*
382 * CAMCTL register bits. (VT6105M only)
383 */
384#define VR_CAMCTL_ENA 0x01
385#define VR_CAMCTL_VLAN 0x02
386#define VR_CAMCTL_MCAST 0x00
387#define VR_CAMCTL_WRITE 0x04
388#define VR_CAMCTL_READ 0x08
389
390#define VR_CAM_MCAST_CNT 32
391#define VR_CAM_VLAN_CNT 32
392
393/*
394 * FLOWCR1 register bits. (VT6105LOM, VT6105M only)
395 */
396#define VR_FLOWCR1_TXLO4 0x00
397#define VR_FLOWCR1_TXLO8 0x40
398#define VR_FLOWCR1_TXLO16 0x80
399#define VR_FLOWCR1_TXLO24 0xC0
400#define VR_FLOWCR1_TXHI24 0x00
401#define VR_FLOWCR1_TXHI32 0x10
402#define VR_FLOWCR1_TXHI48 0x20
403#define VR_FLOWCR1_TXHI64 0x30
404#define VR_FLOWCR1_XONXOFF 0x08
405#define VR_FLOWCR1_TXPAUSE 0x04
406#define VR_FLOWCR1_RXPAUSE 0x02
407#define VR_FLOWCR1_HDX 0x01
408
409/*
410 * WOLCR register bits. (VT6102 or higher only)
411 */
412#define VR_WOLCR_PATTERN0 0x01
413#define VR_WOLCR_PATTERN1 0x02
414#define VR_WOLCR_PATTERN2 0x04
415#define VR_WOLCR_PATTERN3 0x08
416#define VR_WOLCR_UCAST 0x10
417#define VR_WOLCR_MAGIC 0x20
418#define VR_WOLCR_LINKON 0x40
419#define VR_WOLCR_LINKOFF 0x80
420
421/*
422 * PWRCFG register bits. (VT6102 or higher only)
423 */
424#define VR_PWRCFG_WOLEN 0x01
425#define VR_PWRCFG_WOLSR 0x02
426#define VR_PWRCFG_LEGACY_WOL 0x10
427#define VR_PWRCFG_WOLTYPE_PULSE 0x20
428#define VR_PWRCFG_SMIITIME 0x80
429
430/*
431 * WOLCFG register bits. (VT6102 or higher only)
432 */
433#define VR_WOLCFG_PATTERN_PAGE 0x04 /* VT6505 B0 */
434#define VR_WOLCFG_SMIIOPT 0x04
435#define VR_WOLCFG_SMIIACC 0x08
436#define VR_WOLCFG_SAB 0x10
437#define VR_WOLCFG_SAM 0x20
438#define VR_WOLCFG_SFDX 0x40
439#define VR_WOLCFG_PMEOVR 0x80
440
441/*
442 * Rhine TX/RX list structure.
443 */
444
445struct vr_desc {
446 uint32_t vr_status;
447 uint32_t vr_ctl;
448 uint32_t vr_data;
449 uint32_t vr_nextphys;
450};
451
452#define VR_RXSTAT_RXERR 0x00000001
453#define VR_RXSTAT_CRCERR 0x00000002
454#define VR_RXSTAT_FRAMEALIGNERR 0x00000004
455#define VR_RXSTAT_FIFOOFLOW 0x00000008
456#define VR_RXSTAT_GIANT 0x00000010
457#define VR_RXSTAT_RUNT 0x00000020
458#define VR_RXSTAT_BUSERR 0x00000040
459#define VR_RXSTAT_FRAG 0x00000040 /* 6105M */
460#define VR_RXSTAT_BUFFERR 0x00000080
461#define VR_RXSTAT_LASTFRAG 0x00000100
462#define VR_RXSTAT_FIRSTFRAG 0x00000200
463#define VR_RXSTAT_RLINK 0x00000400
464#define VR_RXSTAT_RX_PHYS 0x00000800
465#define VR_RXSTAT_RX_BROAD 0x00001000
466#define VR_RXSTAT_RX_MULTI 0x00002000
467#define VR_RXSTAT_RX_VIDHIT 0x00004000 /* 6105M */
468#define VR_RXSTAT_RX_OK 0x00008000
469#define VR_RXSTAT_RXLEN 0x07FF0000
470#define VR_RXSTAT_RXLEN_EXT 0x78000000
471#define VR_RXSTAT_OWN 0x80000000
472
473#define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16)
474#define VR_RXSTAT_ERR_BITS "\20" \
475 "\1RXERR\2CRCERR\3FRAMEALIGN" \
476 "\4FIFOOFLOW\5GIANT\6RUNT" \
477 "\10BUFERR"
478
479#define VR_RXCTL_BUFLEN 0x000007FF
480#define VR_RXCTL_BUFLEN_EXT 0x00007800
481#define VR_RXCTL_CHAIN 0x00008000
482#define VR_RXCTL_TAG 0x00010000
483#define VR_RXCTL_UDP 0x00020000
484#define VR_RXCTL_TCP 0x00040000
485#define VR_RXCTL_IP 0x00080000
486#define VR_RXCTL_TCPUDPOK 0x00100000
487#define VR_RXCTL_IPOK 0x00200000
488#define VR_RXCTL_SNAPTAG 0x00400000
489#define VR_RXCTL_RXLERR 0x00800000 /* 6105M */
490#define VR_RXCTL_RX_INTR 0x00800000
491
492
493#define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR)
494
495#define VR_TXSTAT_DEFER 0x00000001
496#define VR_TXSTAT_UNDERRUN 0x00000002
497#define VR_TXSTAT_COLLCNT 0x00000078
498#define VR_TXSTAT_SQE 0x00000080
499#define VR_TXSTAT_ABRT 0x00000100
500#define VR_TXSTAT_LATECOLL 0x00000200
501#define VR_TXSTAT_CARRLOST 0x00000400
502#define VR_TXSTAT_UDF 0x00000800
503#define VR_TXSTAT_TBUFF 0x00001000
504#define VR_TXSTAT_BUSERR 0x00002000
505#define VR_TXSTAT_JABTIMEO 0x00004000
506#define VR_TXSTAT_ERRSUM 0x00008000
507#define VR_TXSTAT_OWN 0x80000000
508
509#define VR_TXCTL_BUFLEN 0x000007FF
510#define VR_TXCTL_BUFLEN_EXT 0x00007800
511#define VR_TXCTL_TLINK 0x00008000
512#define VR_TXCTL_NOCRC 0x00010000
513#define VR_TXCTL_INSERTTAG 0x00020000
514#define VR_TXCTL_IPCSUM 0x00040000
515#define VR_TXCTL_UDPCSUM 0x00080000
516#define VR_TXCTL_TCPCSUM 0x00100000
517#define VR_TXCTL_FIRSTFRAG 0x00200000
518#define VR_TXCTL_LASTFRAG 0x00400000
519#define VR_TXCTL_FINT 0x00800000
520
521#define VR_MIN_FRAMELEN 60
522
523#define VR_FLAG_FORCEDELAY 1
524#define VR_FLAG_SCHEDDELAY 2
525#define VR_FLAG_DELAYTIMEO 3
526
527
528#define VR_TIMEOUT 1000
529#define VR_MII_TIMEOUT 10000
530
531#define VR_PHYADDR_MASK 0x1f
532
533/*
534 * General constants that are fun to know.
535 *
536 * VIA vendor ID
537 */
538#define VIA_VENDORID 0x1106
539
540/*
541 * VIA Rhine device IDs.
542 */
543#define VIA_DEVICEID_RHINE 0x3043
544#define VIA_DEVICEID_RHINE_II 0x6100
545#define VIA_DEVICEID_RHINE_II_2 0x3065
546#define VIA_DEVICEID_RHINE_III 0x3106
547#define VIA_DEVICEID_RHINE_III_M 0x3053
548
549/*
550 * Delta Electronics device ID.
551 */
552#define DELTA_VENDORID 0x1500
553
554/*
555 * Delta device IDs.
556 */
557#define DELTA_DEVICEID_RHINE_II 0x1320
558
559/*
560 * Addtron vendor ID.
561 */
562#define ADDTRON_VENDORID 0x4033
563
564/*
565 * Addtron device IDs.
566 */
567#define ADDTRON_DEVICEID_RHINE_II 0x1320
568
569/*
570 * VIA Rhine revision IDs
571 */
572
573#define REV_ID_VT3043_E 0x04
574#define REV_ID_VT3071_A 0x20
575#define REV_ID_VT3071_B 0x21
576#define REV_ID_VT6102_A 0x40
577#define REV_ID_VT6102_B 0x41
578#define REV_ID_VT6102_C 0x42
579#define REV_ID_VT6102_APOLLO 0x74
580#define REV_ID_VT6105_A0 0x80
581#define REV_ID_VT6105_B0 0x83
582#define REV_ID_VT6105_LOM 0x8A
583#define REV_ID_VT6107_A0 0x8C
584#define REV_ID_VT6107_A1 0x8D
585#define REV_ID_VT6105M_A0 0x90
586#define REV_ID_VT6105M_B1 0x94
587
588/*
589 * PCI low memory base and low I/O base register, and
590 * other PCI registers.
591 */
592
593#define VR_PCI_VENDOR_ID 0x00
594#define VR_PCI_DEVICE_ID 0x02
595#define VR_PCI_COMMAND 0x04
596#define VR_PCI_STATUS 0x06
597#define VR_PCI_REVID 0x08
598#define VR_PCI_CLASSCODE 0x09
599#define VR_PCI_LATENCY_TIMER 0x0D
600#define VR_PCI_HEADER_TYPE 0x0E
601#define VR_PCI_LOIO 0x10
602#define VR_PCI_LOMEM 0x14
603#define VR_PCI_BIOSROM 0x30
604#define VR_PCI_INTLINE 0x3C
605#define VR_PCI_INTPIN 0x3D
606#define VR_PCI_MINGNT 0x3E
607#define VR_PCI_MINLAT 0x0F
608#define VR_PCI_RESETOPT 0x48
609#define VR_PCI_EEPROM_DATA 0x4C
610#define VR_PCI_MODE0 0x50
611#define VR_PCI_MODE2 0x52
612#define VR_PCI_MODE3 0x53
613
614#define VR_MODE2_PCEROPT 0x80 /* VT6102 only */
615#define VR_MODE2_DISABT 0x40
616#define VR_MODE2_MRDPL 0x08 /* VT6107A1 and above */
617#define VR_MODE2_MODE10T 0x02
618
619#define VR_MODE3_XONOPT 0x80
620#define VR_MODE3_TPACEN 0x40
621#define VR_MODE3_BACKOPT 0x20
622#define VR_MODE3_DLTSEL 0x10
623#define VR_MODE3_MIIDMY 0x08
624#define VR_MODE3_MIION 0x04
625
626/* power management registers */
627#define VR_PCI_CAPID 0xDC /* 8 bits */
628#define VR_PCI_NEXTPTR 0xDD /* 8 bits */
629#define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */
630#define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
631
632#define VR_PSTATE_MASK 0x0003
633#define VR_PSTATE_D0 0x0000
634#define VR_PSTATE_D1 0x0002
635#define VR_PSTATE_D2 0x0002
636#define VR_PSTATE_D3 0x0003
637#define VR_PME_EN 0x0010
638#define VR_PME_STATUS 0x8000
639
640#define VR_RX_RING_CNT 128
641#define VR_TX_RING_CNT 128
642#define VR_TX_RING_SIZE sizeof(struct vr_desc) * VR_TX_RING_CNT
643#define VR_RX_RING_SIZE sizeof(struct vr_desc) * VR_RX_RING_CNT
644#define VR_RING_ALIGN sizeof(struct vr_desc)
645#define VR_RX_ALIGN sizeof(uint32_t)
646#define VR_MAXFRAGS 8
647#define VR_TX_INTR_THRESH 8
648
649#define VR_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff)
650#define VR_ADDR_HI(x) ((uint64_t)(x) >> 32)
651#define VR_TX_RING_ADDR(sc, i) \
652 ((sc)->vr_rdata.vr_tx_ring_paddr + sizeof(struct vr_desc) * (i))
653#define VR_RX_RING_ADDR(sc, i) \
654 ((sc)->vr_rdata.vr_rx_ring_paddr + sizeof(struct vr_desc) * (i))
655#define VR_INC(x,y) (x) = (((x) + 1) % y)
656
657struct vr_txdesc {
658 struct mbuf *tx_m;
659 bus_dmamap_t tx_dmamap;
660};
661
662struct vr_rxdesc {
663 struct mbuf *rx_m;
664 bus_dmamap_t rx_dmamap;
665 struct vr_desc *desc;
666};
667
668struct vr_chain_data {
669 bus_dma_tag_t vr_parent_tag;
670 bus_dma_tag_t vr_tx_tag;
671 struct vr_txdesc vr_txdesc[VR_TX_RING_CNT];
672 bus_dma_tag_t vr_rx_tag;
673 struct vr_rxdesc vr_rxdesc[VR_RX_RING_CNT];
674 bus_dma_tag_t vr_tx_ring_tag;
675 bus_dma_tag_t vr_rx_ring_tag;
676 bus_dmamap_t vr_tx_ring_map;
677 bus_dmamap_t vr_rx_ring_map;
678 bus_dmamap_t vr_rx_sparemap;
679 int vr_tx_pkts;
680 int vr_tx_prod;
681 int vr_tx_cons;
682 int vr_tx_cnt;
683 int vr_rx_cons;
684};
685
686struct vr_ring_data {
687 struct vr_desc *vr_rx_ring;
688 struct vr_desc *vr_tx_ring;
689 bus_addr_t vr_rx_ring_paddr;
690 bus_addr_t vr_tx_ring_paddr;
691};
692
693struct vr_statistics {
694 uint64_t tx_ok;
695 uint64_t rx_ok;
696 uint32_t tx_errors;
697 uint32_t rx_errors;
698 uint32_t rx_no_buffers;
699 uint32_t rx_no_mbufs;
700 uint32_t rx_crc_errors;
701 uint32_t rx_alignment;
702 uint32_t rx_fifo_overflows;
703 uint32_t rx_giants;
704 uint32_t rx_runts;
705 uint32_t tx_abort;
706 uint32_t tx_collisions;
707 uint32_t tx_late_collisions;
708 uint32_t tx_underrun;
709 uint32_t bus_errors;
710 uint32_t num_restart;
711};
712
713struct vr_softc {
714 struct ifnet *vr_ifp; /* interface info */
715 device_t vr_dev;
716 struct resource *vr_res;
717 int vr_res_id;
718 int vr_res_type;
719 struct resource *vr_irq;
720 void *vr_intrhand;
721 device_t vr_miibus;
722 uint8_t vr_revid; /* Rhine chip revision */
723 uint8_t vr_flags; /* See VR_F_* below */
724#define VR_F_RESTART 0x01 /* Restart unit on next tick */
725 int vr_phyaddr;
726 int vr_if_flags;
727 struct task vr_link_task;
728 struct vr_chain_data vr_cdata;
729 struct vr_ring_data vr_rdata;
730 struct vr_statistics vr_stat;
731 struct callout vr_stat_callout;
732 struct mtx vr_mtx;
733 int vr_suspended; /* if 1, sleeping/detaching */
734 int vr_quirks;
735 int vr_link;
736 int vr_watchdog_timer;
737 int vr_txthresh;
738 int vr_detach;
739#ifdef DEVICE_POLLING
740 int rxcycles;
741#endif
742};
743
744#define VR_LOCK(_sc) mtx_lock(&(_sc)->vr_mtx)
745#define VR_UNLOCK(_sc) mtx_unlock(&(_sc)->vr_mtx)
746#define VR_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vr_mtx, MA_OWNED)
747
748/*
749 * register space access macros
750 */
751#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->vr_res, reg, val)
752#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val)
753#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->vr_res, reg, val)
754
755#define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg)
756#define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg)
757
758#define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
759#define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
760
761#define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
762#define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
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| 763
764#define VR_MCAST_CAM 0
765#define VR_VLAN_CAM 1
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