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uart_dev_ns8250.c (119815) uart_dev_ns8250.c (119943)
1/*
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 119815 2003-09-06 23:13:47Z marcel $");
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 119943 2003-09-10 05:01:08Z marcel $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39#include <dev/uart/uart_dev_ns8250.h>
40
41#include "uart_if.h"
42
43#define DEFAULT_RCLK 1843200
44
45/*
46 * Clear pending interrupts. THRE is cleared by reading IIR. Data
47 * that may have been received gets lost here.
48 */
49static void
50ns8250_clrint(struct uart_bas *bas)
51{
52 uint8_t iir;
53
54 iir = uart_getreg(bas, REG_IIR);
55 while ((iir & IIR_NOPEND) == 0) {
56 iir &= IIR_IMASK;
57 if (iir == IIR_RLS)
58 (void)uart_getreg(bas, REG_LSR);
59 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
60 (void)uart_getreg(bas, REG_DATA);
61 else if (iir == IIR_MLSC)
62 (void)uart_getreg(bas, REG_MSR);
63 uart_barrier(bas);
64 iir = uart_getreg(bas, REG_IIR);
65 }
66}
67
68static int
69ns8250_delay(struct uart_bas *bas)
70{
71 int divisor;
72 u_char lcr;
73
74 lcr = uart_getreg(bas, REG_LCR);
75 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
76 uart_barrier(bas);
77 divisor = uart_getdreg(bas, REG_DL);
78 uart_barrier(bas);
79 uart_setreg(bas, REG_LCR, lcr);
80 uart_barrier(bas);
81
82 /* 1/10th the time to transmit 1 character (estimate). */
83 return (16000000 * divisor / bas->rclk);
84}
85
86static int
87ns8250_divisor(int rclk, int baudrate)
88{
89 int actual_baud, divisor;
90 int error;
91
92 if (baudrate == 0)
93 return (0);
94
95 divisor = (rclk / (baudrate << 3) + 1) >> 1;
96 if (divisor == 0 || divisor >= 65536)
97 return (0);
98 actual_baud = rclk / (divisor << 4);
99
100 /* 10 times error in percent: */
101 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
102
103 /* 3.0% maximum error tolerance: */
104 if (error < -30 || error > 30)
105 return (0);
106
107 return (divisor);
108}
109
110static int
111ns8250_drain(struct uart_bas *bas, int what)
112{
113 int delay, limit;
114
115 delay = ns8250_delay(bas);
116
117 if (what & UART_DRAIN_TRANSMITTER) {
118 /*
119 * Pick an arbitrary high limit to avoid getting stuck in
120 * an infinite loop when the hardware is broken. Make the
121 * limit high enough to handle large FIFOs.
122 */
123 limit = 10*1024;
124 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
125 DELAY(delay);
126 if (limit == 0) {
127 /* printf("ns8250: transmitter appears stuck... "); */
128 return (EIO);
129 }
130 }
131
132 if (what & UART_DRAIN_RECEIVER) {
133 /*
134 * Pick an arbitrary high limit to avoid getting stuck in
135 * an infinite loop when the hardware is broken. Make the
136 * limit high enough to handle large FIFOs and integrated
137 * UARTs. The HP rx2600 for example has 3 UARTs on the
138 * management board that tend to get a lot of data send
139 * to it when the UART is first activated.
140 */
141 limit=10*4096;
142 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
143 (void)uart_getreg(bas, REG_DATA);
144 uart_barrier(bas);
145 DELAY(delay << 2);
146 }
147 if (limit == 0) {
148 /* printf("ns8250: receiver appears broken... "); */
149 return (EIO);
150 }
151 }
152
153 return (0);
154}
155
156/*
157 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
158 * drained. WARNING: this function clobbers the FIFO setting!
159 */
160static void
161ns8250_flush(struct uart_bas *bas, int what)
162{
163 uint8_t fcr;
164
165 fcr = FCR_ENABLE;
166 if (what & UART_FLUSH_TRANSMITTER)
167 fcr |= FCR_XMT_RST;
168 if (what & UART_FLUSH_RECEIVER)
169 fcr |= FCR_RCV_RST;
170 uart_setreg(bas, REG_FCR, fcr);
171 uart_barrier(bas);
172}
173
174static int
175ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
176 int parity)
177{
178 int divisor;
179 uint8_t lcr;
180
181 lcr = 0;
182 if (databits >= 8)
183 lcr |= LCR_8BITS;
184 else if (databits == 7)
185 lcr |= LCR_7BITS;
186 else if (databits == 6)
187 lcr |= LCR_6BITS;
188 else
189 lcr |= LCR_5BITS;
190 if (stopbits > 1)
191 lcr |= LCR_STOPB;
192 lcr |= parity << 3;
193
194 /* Set baudrate. */
195 if (baudrate > 0) {
196 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
197 uart_barrier(bas);
198 divisor = ns8250_divisor(bas->rclk, baudrate);
199 if (divisor == 0)
200 return (EINVAL);
201 uart_setdreg(bas, REG_DL, divisor);
202 uart_barrier(bas);
203 }
204
205 /* Set LCR and clear DLAB. */
206 uart_setreg(bas, REG_LCR, lcr);
207 uart_barrier(bas);
208 return (0);
209}
210
211/*
212 * Low-level UART interface.
213 */
214static int ns8250_probe(struct uart_bas *bas);
215static void ns8250_init(struct uart_bas *bas, int, int, int, int);
216static void ns8250_term(struct uart_bas *bas);
217static void ns8250_putc(struct uart_bas *bas, int);
218static int ns8250_poll(struct uart_bas *bas);
219static int ns8250_getc(struct uart_bas *bas);
220
221struct uart_ops uart_ns8250_ops = {
222 .probe = ns8250_probe,
223 .init = ns8250_init,
224 .term = ns8250_term,
225 .putc = ns8250_putc,
226 .poll = ns8250_poll,
227 .getc = ns8250_getc,
228};
229
230static int
231ns8250_probe(struct uart_bas *bas)
232{
233 u_char lcr, val;
234
235 /* Check known 0 bits that don't depend on DLAB. */
236 val = uart_getreg(bas, REG_IIR);
237 if (val & 0x30)
238 return (ENXIO);
239 val = uart_getreg(bas, REG_MCR);
240 if (val & 0xe0)
241 return (ENXIO);
242
243 lcr = uart_getreg(bas, REG_LCR);
244 uart_setreg(bas, REG_LCR, lcr & ~LCR_DLAB);
245 uart_barrier(bas);
246
247 /* Check known 0 bits that depend on !DLAB. */
248 val = uart_getreg(bas, REG_IER);
249 if (val & 0xf0)
250 goto fail;
251
252 uart_setreg(bas, REG_LCR, lcr);
253 uart_barrier(bas);
254 return (0);
255
256 fail:
257 uart_setreg(bas, REG_LCR, lcr);
258 uart_barrier(bas);
259 return (ENXIO);
260}
261
262static void
263ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
264 int parity)
265{
266
267 if (bas->rclk == 0)
268 bas->rclk = DEFAULT_RCLK;
269 ns8250_param(bas, baudrate, databits, stopbits, parity);
270
271 /* Disable all interrupt sources. */
272 uart_setreg(bas, REG_IER, 0);
273 uart_barrier(bas);
274
275 /* Disable the FIFO (if present). */
276 uart_setreg(bas, REG_FCR, 0);
277 uart_barrier(bas);
278
279 /* Set RTS & DTR. */
280 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
281 uart_barrier(bas);
282
283 ns8250_clrint(bas);
284}
285
286static void
287ns8250_term(struct uart_bas *bas)
288{
289
290 /* Clear RTS & DTR. */
291 uart_setreg(bas, REG_MCR, MCR_IE);
292 uart_barrier(bas);
293}
294
295static void
296ns8250_putc(struct uart_bas *bas, int c)
297{
298 int delay, limit;
299
300 /* 1/10th the time to transmit 1 character (estimate). */
301 delay = ns8250_delay(bas);
302
303 limit = 20;
304 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
305 DELAY(delay);
306 uart_setreg(bas, REG_DATA, c);
307 limit = 40;
308 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
309 DELAY(delay);
310}
311
312static int
313ns8250_poll(struct uart_bas *bas)
314{
315
316 if (uart_getreg(bas, REG_LSR) & LSR_RXRDY)
317 return (uart_getreg(bas, REG_DATA));
318 return (-1);
319}
320
321static int
322ns8250_getc(struct uart_bas *bas)
323{
324 int delay;
325
326 /* 1/10th the time to transmit 1 character (estimate). */
327 delay = ns8250_delay(bas);
328
329 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0)
330 DELAY(delay);
331 return (uart_getreg(bas, REG_DATA));
332}
333
334/*
335 * High-level UART interface.
336 */
337struct ns8250_softc {
338 struct uart_softc base;
339 uint8_t fcr;
340 uint8_t ier;
341 uint8_t mcr;
342};
343
344static int ns8250_bus_attach(struct uart_softc *);
345static int ns8250_bus_detach(struct uart_softc *);
346static int ns8250_bus_flush(struct uart_softc *, int);
347static int ns8250_bus_getsig(struct uart_softc *);
348static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
349static int ns8250_bus_ipend(struct uart_softc *);
350static int ns8250_bus_param(struct uart_softc *, int, int, int, int);
351static int ns8250_bus_probe(struct uart_softc *);
352static int ns8250_bus_receive(struct uart_softc *);
353static int ns8250_bus_setsig(struct uart_softc *, int);
354static int ns8250_bus_transmit(struct uart_softc *);
355
356static kobj_method_t ns8250_methods[] = {
357 KOBJMETHOD(uart_attach, ns8250_bus_attach),
358 KOBJMETHOD(uart_detach, ns8250_bus_detach),
359 KOBJMETHOD(uart_flush, ns8250_bus_flush),
360 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
361 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
362 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
363 KOBJMETHOD(uart_param, ns8250_bus_param),
364 KOBJMETHOD(uart_probe, ns8250_bus_probe),
365 KOBJMETHOD(uart_receive, ns8250_bus_receive),
366 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
367 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
368 { 0, 0 }
369};
370
371struct uart_class uart_ns8250_class = {
372 "ns8250 class",
373 ns8250_methods,
374 sizeof(struct ns8250_softc),
375 .uc_range = 8,
376 .uc_rclk = DEFAULT_RCLK
377};
378
379#define SIGCHG(c, i, s, d) \
380 if (c) { \
381 i |= (i & s) ? s : s | d; \
382 } else { \
383 i = (i & s) ? (i & ~s) | d : i; \
384 }
385
386static int
387ns8250_bus_attach(struct uart_softc *sc)
388{
389 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
390 struct uart_bas *bas;
391
392 bas = &sc->sc_bas;
393
394 ns8250->mcr = uart_getreg(bas, REG_MCR);
395 ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH;
396 uart_setreg(bas, REG_FCR, ns8250->fcr);
397 uart_barrier(bas);
398 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
399
400 if (ns8250->mcr & MCR_DTR)
401 sc->sc_hwsig |= UART_SIG_DTR;
402 if (ns8250->mcr & MCR_RTS)
403 sc->sc_hwsig |= UART_SIG_RTS;
404 ns8250_bus_getsig(sc);
405
406 ns8250_clrint(bas);
407 ns8250->ier = IER_EMSC | IER_ERLS | IER_ERXRDY;
408 uart_setreg(bas, REG_IER, ns8250->ier);
409 uart_barrier(bas);
410 return (0);
411}
412
413static int
414ns8250_bus_detach(struct uart_softc *sc)
415{
416 struct uart_bas *bas;
417
418 bas = &sc->sc_bas;
419 uart_setreg(bas, REG_IER, 0);
420 uart_barrier(bas);
421 ns8250_clrint(bas);
422 return (0);
423}
424
425static int
426ns8250_bus_flush(struct uart_softc *sc, int what)
427{
428 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
429 struct uart_bas *bas;
430
431 bas = &sc->sc_bas;
432 if (sc->sc_hasfifo) {
433 ns8250_flush(bas, what);
434 uart_setreg(bas, REG_FCR, ns8250->fcr);
435 uart_barrier(bas);
436 return (0);
437 }
438 return (ns8250_drain(bas, what));
439}
440
441static int
442ns8250_bus_getsig(struct uart_softc *sc)
443{
444 uint32_t new, old, sig;
445 uint8_t msr;
446
447 do {
448 old = sc->sc_hwsig;
449 sig = old;
450 msr = uart_getreg(&sc->sc_bas, REG_MSR);
451 SIGCHG(msr & MSR_DSR, sig, UART_SIG_DSR, UART_SIG_DDSR);
452 SIGCHG(msr & MSR_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
453 SIGCHG(msr & MSR_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD);
454 SIGCHG(msr & MSR_RI, sig, UART_SIG_RI, UART_SIG_DRI);
455 new = sig & ~UART_SIGMASK_DELTA;
456 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
457 return (sig);
458}
459
460static int
461ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
462{
463 struct uart_bas *bas;
464 uint8_t lcr;
465
466 bas = &sc->sc_bas;
467 switch (request) {
468 case UART_IOCTL_BREAK:
469 lcr = uart_getreg(bas, REG_LCR);
470 if (data)
471 lcr |= LCR_SBREAK;
472 else
473 lcr &= ~LCR_SBREAK;
474 uart_setreg(bas, REG_LCR, lcr);
475 uart_barrier(bas);
476 break;
477 default:
478 return (EINVAL);
479 }
480 return (0);
481}
482
483static int
484ns8250_bus_ipend(struct uart_softc *sc)
485{
486 struct uart_bas *bas;
487 int ipend;
488 uint8_t iir, lsr;
489
490 bas = &sc->sc_bas;
491 iir = uart_getreg(bas, REG_IIR);
492 if (iir & IIR_NOPEND)
493 return (0);
494
495 ipend = 0;
496 if (iir & IIR_RXRDY) {
497 lsr = uart_getreg(bas, REG_LSR);
498 if (lsr & LSR_OE)
499 ipend |= UART_IPEND_OVERRUN;
500 if (lsr & LSR_BI)
501 ipend |= UART_IPEND_BREAK;
502 if (lsr & LSR_RXRDY)
503 ipend |= UART_IPEND_RXREADY;
504 } else {
505 if (iir & IIR_TXRDY)
506 ipend |= UART_IPEND_TXIDLE;
507 else
508 ipend |= UART_IPEND_SIGCHG;
509 }
510
511 return ((sc->sc_leaving) ? 0 : ipend);
512}
513
514static int
515ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
516 int stopbits, int parity)
517{
518 struct uart_bas *bas;
519
520 bas = &sc->sc_bas;
521 return (ns8250_param(bas, baudrate, databits, stopbits, parity));
522}
523
524static int
525ns8250_bus_probe(struct uart_softc *sc)
526{
527 struct uart_bas *bas;
528 int count, delay, error, limit;
529 uint8_t mcr;
530
531 bas = &sc->sc_bas;
532
533 error = ns8250_probe(bas);
534 if (error)
535 return (error);
536
537 mcr = MCR_IE;
538 if (sc->sc_sysdev == NULL) {
539 /* By using ns8250_init() we also set DTR and RTS. */
540 ns8250_init(bas, 9600, 8, 1, UART_PARITY_NONE);
541 } else
542 mcr |= MCR_DTR | MCR_RTS;
543
544 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
545 if (error)
546 return (error);
547
548 /*
549 * Set loopback mode. This avoids having garbage on the wire and
550 * also allows us send and receive data. We set DTR and RTS to
551 * avoid the possibility that automatic flow-control prevents
552 * any data from being sent. We clear IE to avoid raising interrupts.
553 */
554 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_DTR | MCR_RTS);
555 uart_barrier(bas);
556
557 /*
558 * Enable FIFOs. And check that the UART has them. If not, we're
559 * done. Otherwise we set DMA mode with the highest trigger level
560 * so that we can determine the FIFO size. Since this is the first
561 * time we enable the FIFOs, we reset them.
562 */
563 uart_setreg(bas, REG_FCR, FCR_ENABLE);
564 uart_barrier(bas);
565 sc->sc_hasfifo = (uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK) ? 1 : 0;
566 if (!sc->sc_hasfifo) {
567 /*
568 * NS16450 or INS8250. We don't bother to differentiate
569 * between them. They're too old to be interesting.
570 */
571 uart_setreg(bas, REG_MCR, mcr);
572 uart_barrier(bas);
573 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
574 return (0);
575 }
576
577 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_DMA | FCR_RX_HIGH |
578 FCR_XMT_RST | FCR_RCV_RST);
579 uart_barrier(bas);
580
581 count = 0;
582 delay = ns8250_delay(bas);
583
584 /* We have FIFOs. Drain the transmitter and receiver. */
585 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
586 if (error) {
587 uart_setreg(bas, REG_MCR, mcr);
588 uart_setreg(bas, REG_FCR, 0);
589 uart_barrier(bas);
590 goto describe;
591 }
592
593 uart_setreg(bas, REG_IER, IER_ERXRDY);
594 uart_barrier(bas);
595
596 /*
597 * We should have a sufficiently clean "pipe" to determine the
598 * size of the FIFOs. We send as much characters as is reasonable
599 * and wait for the the RX interrupt to be asserted, counting the
600 * characters as we send them. Based on that count we know the
601 * FIFO size.
602 */
603 while ((uart_getreg(bas, REG_IIR) & IIR_RXRDY) == 0 && count < 1030) {
604 uart_setreg(bas, REG_DATA, 0);
605 uart_barrier(bas);
606 count++;
607
608 limit = 30;
609 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
610 DELAY(delay);
611 if (limit == 0) {
612 uart_setreg(bas, REG_IER, 0);
613 uart_setreg(bas, REG_MCR, mcr);
614 uart_setreg(bas, REG_FCR, 0);
615 uart_barrier(bas);
616 count = 0;
617 goto describe;
618 }
619 }
620
621 uart_setreg(bas, REG_IER, 0);
622 uart_setreg(bas, REG_MCR, mcr);
623
624 /* Reset FIFOs. */
625 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
626
627 describe:
628 if (count >= 14 && count < 16) {
629 sc->sc_rxfifosz = 16;
630 device_set_desc(sc->sc_dev, "16550 or compatible");
631 } else if (count >= 28 && count < 32) {
632 sc->sc_rxfifosz = 32;
633 device_set_desc(sc->sc_dev, "16650 or compatible");
634 } else if (count >= 56 && count < 64) {
635 sc->sc_rxfifosz = 64;
636 device_set_desc(sc->sc_dev, "16750 or compatible");
637 } else if (count >= 112 && count < 128) {
638 sc->sc_rxfifosz = 128;
639 device_set_desc(sc->sc_dev, "16950 or compatible");
640 } else {
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39#include <dev/uart/uart_dev_ns8250.h>
40
41#include "uart_if.h"
42
43#define DEFAULT_RCLK 1843200
44
45/*
46 * Clear pending interrupts. THRE is cleared by reading IIR. Data
47 * that may have been received gets lost here.
48 */
49static void
50ns8250_clrint(struct uart_bas *bas)
51{
52 uint8_t iir;
53
54 iir = uart_getreg(bas, REG_IIR);
55 while ((iir & IIR_NOPEND) == 0) {
56 iir &= IIR_IMASK;
57 if (iir == IIR_RLS)
58 (void)uart_getreg(bas, REG_LSR);
59 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
60 (void)uart_getreg(bas, REG_DATA);
61 else if (iir == IIR_MLSC)
62 (void)uart_getreg(bas, REG_MSR);
63 uart_barrier(bas);
64 iir = uart_getreg(bas, REG_IIR);
65 }
66}
67
68static int
69ns8250_delay(struct uart_bas *bas)
70{
71 int divisor;
72 u_char lcr;
73
74 lcr = uart_getreg(bas, REG_LCR);
75 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
76 uart_barrier(bas);
77 divisor = uart_getdreg(bas, REG_DL);
78 uart_barrier(bas);
79 uart_setreg(bas, REG_LCR, lcr);
80 uart_barrier(bas);
81
82 /* 1/10th the time to transmit 1 character (estimate). */
83 return (16000000 * divisor / bas->rclk);
84}
85
86static int
87ns8250_divisor(int rclk, int baudrate)
88{
89 int actual_baud, divisor;
90 int error;
91
92 if (baudrate == 0)
93 return (0);
94
95 divisor = (rclk / (baudrate << 3) + 1) >> 1;
96 if (divisor == 0 || divisor >= 65536)
97 return (0);
98 actual_baud = rclk / (divisor << 4);
99
100 /* 10 times error in percent: */
101 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
102
103 /* 3.0% maximum error tolerance: */
104 if (error < -30 || error > 30)
105 return (0);
106
107 return (divisor);
108}
109
110static int
111ns8250_drain(struct uart_bas *bas, int what)
112{
113 int delay, limit;
114
115 delay = ns8250_delay(bas);
116
117 if (what & UART_DRAIN_TRANSMITTER) {
118 /*
119 * Pick an arbitrary high limit to avoid getting stuck in
120 * an infinite loop when the hardware is broken. Make the
121 * limit high enough to handle large FIFOs.
122 */
123 limit = 10*1024;
124 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
125 DELAY(delay);
126 if (limit == 0) {
127 /* printf("ns8250: transmitter appears stuck... "); */
128 return (EIO);
129 }
130 }
131
132 if (what & UART_DRAIN_RECEIVER) {
133 /*
134 * Pick an arbitrary high limit to avoid getting stuck in
135 * an infinite loop when the hardware is broken. Make the
136 * limit high enough to handle large FIFOs and integrated
137 * UARTs. The HP rx2600 for example has 3 UARTs on the
138 * management board that tend to get a lot of data send
139 * to it when the UART is first activated.
140 */
141 limit=10*4096;
142 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
143 (void)uart_getreg(bas, REG_DATA);
144 uart_barrier(bas);
145 DELAY(delay << 2);
146 }
147 if (limit == 0) {
148 /* printf("ns8250: receiver appears broken... "); */
149 return (EIO);
150 }
151 }
152
153 return (0);
154}
155
156/*
157 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
158 * drained. WARNING: this function clobbers the FIFO setting!
159 */
160static void
161ns8250_flush(struct uart_bas *bas, int what)
162{
163 uint8_t fcr;
164
165 fcr = FCR_ENABLE;
166 if (what & UART_FLUSH_TRANSMITTER)
167 fcr |= FCR_XMT_RST;
168 if (what & UART_FLUSH_RECEIVER)
169 fcr |= FCR_RCV_RST;
170 uart_setreg(bas, REG_FCR, fcr);
171 uart_barrier(bas);
172}
173
174static int
175ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
176 int parity)
177{
178 int divisor;
179 uint8_t lcr;
180
181 lcr = 0;
182 if (databits >= 8)
183 lcr |= LCR_8BITS;
184 else if (databits == 7)
185 lcr |= LCR_7BITS;
186 else if (databits == 6)
187 lcr |= LCR_6BITS;
188 else
189 lcr |= LCR_5BITS;
190 if (stopbits > 1)
191 lcr |= LCR_STOPB;
192 lcr |= parity << 3;
193
194 /* Set baudrate. */
195 if (baudrate > 0) {
196 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
197 uart_barrier(bas);
198 divisor = ns8250_divisor(bas->rclk, baudrate);
199 if (divisor == 0)
200 return (EINVAL);
201 uart_setdreg(bas, REG_DL, divisor);
202 uart_barrier(bas);
203 }
204
205 /* Set LCR and clear DLAB. */
206 uart_setreg(bas, REG_LCR, lcr);
207 uart_barrier(bas);
208 return (0);
209}
210
211/*
212 * Low-level UART interface.
213 */
214static int ns8250_probe(struct uart_bas *bas);
215static void ns8250_init(struct uart_bas *bas, int, int, int, int);
216static void ns8250_term(struct uart_bas *bas);
217static void ns8250_putc(struct uart_bas *bas, int);
218static int ns8250_poll(struct uart_bas *bas);
219static int ns8250_getc(struct uart_bas *bas);
220
221struct uart_ops uart_ns8250_ops = {
222 .probe = ns8250_probe,
223 .init = ns8250_init,
224 .term = ns8250_term,
225 .putc = ns8250_putc,
226 .poll = ns8250_poll,
227 .getc = ns8250_getc,
228};
229
230static int
231ns8250_probe(struct uart_bas *bas)
232{
233 u_char lcr, val;
234
235 /* Check known 0 bits that don't depend on DLAB. */
236 val = uart_getreg(bas, REG_IIR);
237 if (val & 0x30)
238 return (ENXIO);
239 val = uart_getreg(bas, REG_MCR);
240 if (val & 0xe0)
241 return (ENXIO);
242
243 lcr = uart_getreg(bas, REG_LCR);
244 uart_setreg(bas, REG_LCR, lcr & ~LCR_DLAB);
245 uart_barrier(bas);
246
247 /* Check known 0 bits that depend on !DLAB. */
248 val = uart_getreg(bas, REG_IER);
249 if (val & 0xf0)
250 goto fail;
251
252 uart_setreg(bas, REG_LCR, lcr);
253 uart_barrier(bas);
254 return (0);
255
256 fail:
257 uart_setreg(bas, REG_LCR, lcr);
258 uart_barrier(bas);
259 return (ENXIO);
260}
261
262static void
263ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
264 int parity)
265{
266
267 if (bas->rclk == 0)
268 bas->rclk = DEFAULT_RCLK;
269 ns8250_param(bas, baudrate, databits, stopbits, parity);
270
271 /* Disable all interrupt sources. */
272 uart_setreg(bas, REG_IER, 0);
273 uart_barrier(bas);
274
275 /* Disable the FIFO (if present). */
276 uart_setreg(bas, REG_FCR, 0);
277 uart_barrier(bas);
278
279 /* Set RTS & DTR. */
280 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
281 uart_barrier(bas);
282
283 ns8250_clrint(bas);
284}
285
286static void
287ns8250_term(struct uart_bas *bas)
288{
289
290 /* Clear RTS & DTR. */
291 uart_setreg(bas, REG_MCR, MCR_IE);
292 uart_barrier(bas);
293}
294
295static void
296ns8250_putc(struct uart_bas *bas, int c)
297{
298 int delay, limit;
299
300 /* 1/10th the time to transmit 1 character (estimate). */
301 delay = ns8250_delay(bas);
302
303 limit = 20;
304 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
305 DELAY(delay);
306 uart_setreg(bas, REG_DATA, c);
307 limit = 40;
308 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
309 DELAY(delay);
310}
311
312static int
313ns8250_poll(struct uart_bas *bas)
314{
315
316 if (uart_getreg(bas, REG_LSR) & LSR_RXRDY)
317 return (uart_getreg(bas, REG_DATA));
318 return (-1);
319}
320
321static int
322ns8250_getc(struct uart_bas *bas)
323{
324 int delay;
325
326 /* 1/10th the time to transmit 1 character (estimate). */
327 delay = ns8250_delay(bas);
328
329 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0)
330 DELAY(delay);
331 return (uart_getreg(bas, REG_DATA));
332}
333
334/*
335 * High-level UART interface.
336 */
337struct ns8250_softc {
338 struct uart_softc base;
339 uint8_t fcr;
340 uint8_t ier;
341 uint8_t mcr;
342};
343
344static int ns8250_bus_attach(struct uart_softc *);
345static int ns8250_bus_detach(struct uart_softc *);
346static int ns8250_bus_flush(struct uart_softc *, int);
347static int ns8250_bus_getsig(struct uart_softc *);
348static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
349static int ns8250_bus_ipend(struct uart_softc *);
350static int ns8250_bus_param(struct uart_softc *, int, int, int, int);
351static int ns8250_bus_probe(struct uart_softc *);
352static int ns8250_bus_receive(struct uart_softc *);
353static int ns8250_bus_setsig(struct uart_softc *, int);
354static int ns8250_bus_transmit(struct uart_softc *);
355
356static kobj_method_t ns8250_methods[] = {
357 KOBJMETHOD(uart_attach, ns8250_bus_attach),
358 KOBJMETHOD(uart_detach, ns8250_bus_detach),
359 KOBJMETHOD(uart_flush, ns8250_bus_flush),
360 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
361 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
362 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
363 KOBJMETHOD(uart_param, ns8250_bus_param),
364 KOBJMETHOD(uart_probe, ns8250_bus_probe),
365 KOBJMETHOD(uart_receive, ns8250_bus_receive),
366 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
367 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
368 { 0, 0 }
369};
370
371struct uart_class uart_ns8250_class = {
372 "ns8250 class",
373 ns8250_methods,
374 sizeof(struct ns8250_softc),
375 .uc_range = 8,
376 .uc_rclk = DEFAULT_RCLK
377};
378
379#define SIGCHG(c, i, s, d) \
380 if (c) { \
381 i |= (i & s) ? s : s | d; \
382 } else { \
383 i = (i & s) ? (i & ~s) | d : i; \
384 }
385
386static int
387ns8250_bus_attach(struct uart_softc *sc)
388{
389 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
390 struct uart_bas *bas;
391
392 bas = &sc->sc_bas;
393
394 ns8250->mcr = uart_getreg(bas, REG_MCR);
395 ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH;
396 uart_setreg(bas, REG_FCR, ns8250->fcr);
397 uart_barrier(bas);
398 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
399
400 if (ns8250->mcr & MCR_DTR)
401 sc->sc_hwsig |= UART_SIG_DTR;
402 if (ns8250->mcr & MCR_RTS)
403 sc->sc_hwsig |= UART_SIG_RTS;
404 ns8250_bus_getsig(sc);
405
406 ns8250_clrint(bas);
407 ns8250->ier = IER_EMSC | IER_ERLS | IER_ERXRDY;
408 uart_setreg(bas, REG_IER, ns8250->ier);
409 uart_barrier(bas);
410 return (0);
411}
412
413static int
414ns8250_bus_detach(struct uart_softc *sc)
415{
416 struct uart_bas *bas;
417
418 bas = &sc->sc_bas;
419 uart_setreg(bas, REG_IER, 0);
420 uart_barrier(bas);
421 ns8250_clrint(bas);
422 return (0);
423}
424
425static int
426ns8250_bus_flush(struct uart_softc *sc, int what)
427{
428 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
429 struct uart_bas *bas;
430
431 bas = &sc->sc_bas;
432 if (sc->sc_hasfifo) {
433 ns8250_flush(bas, what);
434 uart_setreg(bas, REG_FCR, ns8250->fcr);
435 uart_barrier(bas);
436 return (0);
437 }
438 return (ns8250_drain(bas, what));
439}
440
441static int
442ns8250_bus_getsig(struct uart_softc *sc)
443{
444 uint32_t new, old, sig;
445 uint8_t msr;
446
447 do {
448 old = sc->sc_hwsig;
449 sig = old;
450 msr = uart_getreg(&sc->sc_bas, REG_MSR);
451 SIGCHG(msr & MSR_DSR, sig, UART_SIG_DSR, UART_SIG_DDSR);
452 SIGCHG(msr & MSR_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
453 SIGCHG(msr & MSR_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD);
454 SIGCHG(msr & MSR_RI, sig, UART_SIG_RI, UART_SIG_DRI);
455 new = sig & ~UART_SIGMASK_DELTA;
456 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
457 return (sig);
458}
459
460static int
461ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
462{
463 struct uart_bas *bas;
464 uint8_t lcr;
465
466 bas = &sc->sc_bas;
467 switch (request) {
468 case UART_IOCTL_BREAK:
469 lcr = uart_getreg(bas, REG_LCR);
470 if (data)
471 lcr |= LCR_SBREAK;
472 else
473 lcr &= ~LCR_SBREAK;
474 uart_setreg(bas, REG_LCR, lcr);
475 uart_barrier(bas);
476 break;
477 default:
478 return (EINVAL);
479 }
480 return (0);
481}
482
483static int
484ns8250_bus_ipend(struct uart_softc *sc)
485{
486 struct uart_bas *bas;
487 int ipend;
488 uint8_t iir, lsr;
489
490 bas = &sc->sc_bas;
491 iir = uart_getreg(bas, REG_IIR);
492 if (iir & IIR_NOPEND)
493 return (0);
494
495 ipend = 0;
496 if (iir & IIR_RXRDY) {
497 lsr = uart_getreg(bas, REG_LSR);
498 if (lsr & LSR_OE)
499 ipend |= UART_IPEND_OVERRUN;
500 if (lsr & LSR_BI)
501 ipend |= UART_IPEND_BREAK;
502 if (lsr & LSR_RXRDY)
503 ipend |= UART_IPEND_RXREADY;
504 } else {
505 if (iir & IIR_TXRDY)
506 ipend |= UART_IPEND_TXIDLE;
507 else
508 ipend |= UART_IPEND_SIGCHG;
509 }
510
511 return ((sc->sc_leaving) ? 0 : ipend);
512}
513
514static int
515ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
516 int stopbits, int parity)
517{
518 struct uart_bas *bas;
519
520 bas = &sc->sc_bas;
521 return (ns8250_param(bas, baudrate, databits, stopbits, parity));
522}
523
524static int
525ns8250_bus_probe(struct uart_softc *sc)
526{
527 struct uart_bas *bas;
528 int count, delay, error, limit;
529 uint8_t mcr;
530
531 bas = &sc->sc_bas;
532
533 error = ns8250_probe(bas);
534 if (error)
535 return (error);
536
537 mcr = MCR_IE;
538 if (sc->sc_sysdev == NULL) {
539 /* By using ns8250_init() we also set DTR and RTS. */
540 ns8250_init(bas, 9600, 8, 1, UART_PARITY_NONE);
541 } else
542 mcr |= MCR_DTR | MCR_RTS;
543
544 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
545 if (error)
546 return (error);
547
548 /*
549 * Set loopback mode. This avoids having garbage on the wire and
550 * also allows us send and receive data. We set DTR and RTS to
551 * avoid the possibility that automatic flow-control prevents
552 * any data from being sent. We clear IE to avoid raising interrupts.
553 */
554 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_DTR | MCR_RTS);
555 uart_barrier(bas);
556
557 /*
558 * Enable FIFOs. And check that the UART has them. If not, we're
559 * done. Otherwise we set DMA mode with the highest trigger level
560 * so that we can determine the FIFO size. Since this is the first
561 * time we enable the FIFOs, we reset them.
562 */
563 uart_setreg(bas, REG_FCR, FCR_ENABLE);
564 uart_barrier(bas);
565 sc->sc_hasfifo = (uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK) ? 1 : 0;
566 if (!sc->sc_hasfifo) {
567 /*
568 * NS16450 or INS8250. We don't bother to differentiate
569 * between them. They're too old to be interesting.
570 */
571 uart_setreg(bas, REG_MCR, mcr);
572 uart_barrier(bas);
573 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
574 return (0);
575 }
576
577 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_DMA | FCR_RX_HIGH |
578 FCR_XMT_RST | FCR_RCV_RST);
579 uart_barrier(bas);
580
581 count = 0;
582 delay = ns8250_delay(bas);
583
584 /* We have FIFOs. Drain the transmitter and receiver. */
585 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
586 if (error) {
587 uart_setreg(bas, REG_MCR, mcr);
588 uart_setreg(bas, REG_FCR, 0);
589 uart_barrier(bas);
590 goto describe;
591 }
592
593 uart_setreg(bas, REG_IER, IER_ERXRDY);
594 uart_barrier(bas);
595
596 /*
597 * We should have a sufficiently clean "pipe" to determine the
598 * size of the FIFOs. We send as much characters as is reasonable
599 * and wait for the the RX interrupt to be asserted, counting the
600 * characters as we send them. Based on that count we know the
601 * FIFO size.
602 */
603 while ((uart_getreg(bas, REG_IIR) & IIR_RXRDY) == 0 && count < 1030) {
604 uart_setreg(bas, REG_DATA, 0);
605 uart_barrier(bas);
606 count++;
607
608 limit = 30;
609 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
610 DELAY(delay);
611 if (limit == 0) {
612 uart_setreg(bas, REG_IER, 0);
613 uart_setreg(bas, REG_MCR, mcr);
614 uart_setreg(bas, REG_FCR, 0);
615 uart_barrier(bas);
616 count = 0;
617 goto describe;
618 }
619 }
620
621 uart_setreg(bas, REG_IER, 0);
622 uart_setreg(bas, REG_MCR, mcr);
623
624 /* Reset FIFOs. */
625 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
626
627 describe:
628 if (count >= 14 && count < 16) {
629 sc->sc_rxfifosz = 16;
630 device_set_desc(sc->sc_dev, "16550 or compatible");
631 } else if (count >= 28 && count < 32) {
632 sc->sc_rxfifosz = 32;
633 device_set_desc(sc->sc_dev, "16650 or compatible");
634 } else if (count >= 56 && count < 64) {
635 sc->sc_rxfifosz = 64;
636 device_set_desc(sc->sc_dev, "16750 or compatible");
637 } else if (count >= 112 && count < 128) {
638 sc->sc_rxfifosz = 128;
639 device_set_desc(sc->sc_dev, "16950 or compatible");
640 } else {
641 sc->sc_rxfifosz = 1;
641 sc->sc_rxfifosz = 16;
642 device_set_desc(sc->sc_dev,
643 "Non-standard ns8250 class UART with FIFOs");
644 }
645
646 /*
647 * Force the Tx FIFO size to 16 bytes for now. We don't program the
648 * Tx trigger. Also, we assume that all data has been sent when the
649 * interrupt happens.
650 */
651 sc->sc_txfifosz = 16;
652
653 return (0);
654}
655
656static int
657ns8250_bus_receive(struct uart_softc *sc)
658{
659 struct uart_bas *bas;
660 int xc;
661 uint8_t lsr;
662
663 bas = &sc->sc_bas;
664 while (!uart_rx_full(sc)) {
665 lsr = uart_getreg(bas, REG_LSR);
666 if ((lsr & LSR_RXRDY) == 0)
667 break;
668 xc = uart_getreg(bas, REG_DATA);
669 if (lsr & LSR_FE)
670 xc |= UART_STAT_FRAMERR;
671 if (lsr & LSR_PE)
672 xc |= UART_STAT_PARERR;
673 uart_rx_put(sc, xc);
674 }
675 return (0);
676}
677
678static int
679ns8250_bus_setsig(struct uart_softc *sc, int sig)
680{
681 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
682 struct uart_bas *bas;
683 uint32_t new, old;
684
685 bas = &sc->sc_bas;
686 do {
687 old = sc->sc_hwsig;
688 new = old;
689 if (sig & UART_SIG_DDTR) {
690 SIGCHG(sig & UART_SIG_DTR, new, UART_SIG_DTR,
691 UART_SIG_DDTR);
692 }
693 if (sig & UART_SIG_DRTS) {
694 SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS,
695 UART_SIG_DRTS);
696 }
697 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
698 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
699 if (new & UART_SIG_DTR)
700 ns8250->mcr |= MCR_DTR;
701 if (new & UART_SIG_RTS)
702 ns8250->mcr |= MCR_RTS;
703 uart_setreg(bas, REG_MCR, ns8250->mcr);
704 uart_barrier(bas);
705 return (0);
706}
707
708static int
709ns8250_bus_transmit(struct uart_softc *sc)
710{
711 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
712 struct uart_bas *bas;
713 int i;
714
715 bas = &sc->sc_bas;
716 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
717 ;
718 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
719 uart_barrier(bas);
720 for (i = 0; i < sc->sc_txdatasz; i++) {
721 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
722 uart_barrier(bas);
723 }
724 sc->sc_txbusy = 1;
725 return (0);
726}
642 device_set_desc(sc->sc_dev,
643 "Non-standard ns8250 class UART with FIFOs");
644 }
645
646 /*
647 * Force the Tx FIFO size to 16 bytes for now. We don't program the
648 * Tx trigger. Also, we assume that all data has been sent when the
649 * interrupt happens.
650 */
651 sc->sc_txfifosz = 16;
652
653 return (0);
654}
655
656static int
657ns8250_bus_receive(struct uart_softc *sc)
658{
659 struct uart_bas *bas;
660 int xc;
661 uint8_t lsr;
662
663 bas = &sc->sc_bas;
664 while (!uart_rx_full(sc)) {
665 lsr = uart_getreg(bas, REG_LSR);
666 if ((lsr & LSR_RXRDY) == 0)
667 break;
668 xc = uart_getreg(bas, REG_DATA);
669 if (lsr & LSR_FE)
670 xc |= UART_STAT_FRAMERR;
671 if (lsr & LSR_PE)
672 xc |= UART_STAT_PARERR;
673 uart_rx_put(sc, xc);
674 }
675 return (0);
676}
677
678static int
679ns8250_bus_setsig(struct uart_softc *sc, int sig)
680{
681 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
682 struct uart_bas *bas;
683 uint32_t new, old;
684
685 bas = &sc->sc_bas;
686 do {
687 old = sc->sc_hwsig;
688 new = old;
689 if (sig & UART_SIG_DDTR) {
690 SIGCHG(sig & UART_SIG_DTR, new, UART_SIG_DTR,
691 UART_SIG_DDTR);
692 }
693 if (sig & UART_SIG_DRTS) {
694 SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS,
695 UART_SIG_DRTS);
696 }
697 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
698 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
699 if (new & UART_SIG_DTR)
700 ns8250->mcr |= MCR_DTR;
701 if (new & UART_SIG_RTS)
702 ns8250->mcr |= MCR_RTS;
703 uart_setreg(bas, REG_MCR, ns8250->mcr);
704 uart_barrier(bas);
705 return (0);
706}
707
708static int
709ns8250_bus_transmit(struct uart_softc *sc)
710{
711 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
712 struct uart_bas *bas;
713 int i;
714
715 bas = &sc->sc_bas;
716 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
717 ;
718 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
719 uart_barrier(bas);
720 for (i = 0; i < sc->sc_txdatasz; i++) {
721 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
722 uart_barrier(bas);
723 }
724 sc->sc_txbusy = 1;
725 return (0);
726}