uart_dev_ns8250.c (155973) | uart_dev_ns8250.c (157300) |
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1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 155973 2006-02-24 05:40:17Z marcel $"); | 28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 157300 2006-03-30 18:37:03Z marcel $"); |
29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> --- 390 unchanged lines hidden (view full) --- 427static int 428ns8250_bus_flush(struct uart_softc *sc, int what) 429{ 430 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 431 struct uart_bas *bas; 432 int error; 433 434 bas = &sc->sc_bas; | 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> --- 390 unchanged lines hidden (view full) --- 427static int 428ns8250_bus_flush(struct uart_softc *sc, int what) 429{ 430 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 431 struct uart_bas *bas; 432 int error; 433 434 bas = &sc->sc_bas; |
435 mtx_lock_spin(&sc->sc_hwmtx); | 435 uart_lock(sc->sc_hwmtx); |
436 if (sc->sc_hasfifo) { 437 ns8250_flush(bas, what); 438 uart_setreg(bas, REG_FCR, ns8250->fcr); 439 uart_barrier(bas); 440 error = 0; 441 } else 442 error = ns8250_drain(bas, what); | 436 if (sc->sc_hasfifo) { 437 ns8250_flush(bas, what); 438 uart_setreg(bas, REG_FCR, ns8250->fcr); 439 uart_barrier(bas); 440 error = 0; 441 } else 442 error = ns8250_drain(bas, what); |
443 mtx_unlock_spin(&sc->sc_hwmtx); | 443 uart_unlock(sc->sc_hwmtx); |
444 return (error); 445} 446 447static int 448ns8250_bus_getsig(struct uart_softc *sc) 449{ 450 uint32_t new, old, sig; 451 uint8_t msr; 452 453 do { 454 old = sc->sc_hwsig; 455 sig = old; | 444 return (error); 445} 446 447static int 448ns8250_bus_getsig(struct uart_softc *sc) 449{ 450 uint32_t new, old, sig; 451 uint8_t msr; 452 453 do { 454 old = sc->sc_hwsig; 455 sig = old; |
456 mtx_lock_spin(&sc->sc_hwmtx); | 456 uart_lock(sc->sc_hwmtx); |
457 msr = uart_getreg(&sc->sc_bas, REG_MSR); | 457 msr = uart_getreg(&sc->sc_bas, REG_MSR); |
458 mtx_unlock_spin(&sc->sc_hwmtx); | 458 uart_unlock(sc->sc_hwmtx); |
459 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 460 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 461 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 462 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 463 new = sig & ~SER_MASK_DELTA; 464 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 465 return (sig); 466} 467 468static int 469ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 470{ 471 struct uart_bas *bas; 472 int baudrate, divisor, error; 473 uint8_t efr, lcr; 474 475 bas = &sc->sc_bas; 476 error = 0; | 459 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 460 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 461 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 462 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 463 new = sig & ~SER_MASK_DELTA; 464 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 465 return (sig); 466} 467 468static int 469ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 470{ 471 struct uart_bas *bas; 472 int baudrate, divisor, error; 473 uint8_t efr, lcr; 474 475 bas = &sc->sc_bas; 476 error = 0; |
477 mtx_lock_spin(&sc->sc_hwmtx); | 477 uart_lock(sc->sc_hwmtx); |
478 switch (request) { 479 case UART_IOCTL_BREAK: 480 lcr = uart_getreg(bas, REG_LCR); 481 if (data) 482 lcr |= LCR_SBREAK; 483 else 484 lcr &= ~LCR_SBREAK; 485 uart_setreg(bas, REG_LCR, lcr); --- 42 unchanged lines hidden (view full) --- 528 *(int*)data = baudrate; 529 else 530 error = ENXIO; 531 break; 532 default: 533 error = EINVAL; 534 break; 535 } | 478 switch (request) { 479 case UART_IOCTL_BREAK: 480 lcr = uart_getreg(bas, REG_LCR); 481 if (data) 482 lcr |= LCR_SBREAK; 483 else 484 lcr &= ~LCR_SBREAK; 485 uart_setreg(bas, REG_LCR, lcr); --- 42 unchanged lines hidden (view full) --- 528 *(int*)data = baudrate; 529 else 530 error = ENXIO; 531 break; 532 default: 533 error = EINVAL; 534 break; 535 } |
536 mtx_unlock_spin(&sc->sc_hwmtx); | 536 uart_unlock(sc->sc_hwmtx); |
537 return (error); 538} 539 540static int 541ns8250_bus_ipend(struct uart_softc *sc) 542{ 543 struct uart_bas *bas; 544 int ipend; 545 uint8_t iir, lsr; 546 547 bas = &sc->sc_bas; | 537 return (error); 538} 539 540static int 541ns8250_bus_ipend(struct uart_softc *sc) 542{ 543 struct uart_bas *bas; 544 int ipend; 545 uint8_t iir, lsr; 546 547 bas = &sc->sc_bas; |
548 mtx_lock_spin(&sc->sc_hwmtx); | 548 uart_lock(sc->sc_hwmtx); |
549 iir = uart_getreg(bas, REG_IIR); 550 if (iir & IIR_NOPEND) { | 549 iir = uart_getreg(bas, REG_IIR); 550 if (iir & IIR_NOPEND) { |
551 mtx_unlock_spin(&sc->sc_hwmtx); | 551 uart_unlock(sc->sc_hwmtx); |
552 return (0); 553 } 554 ipend = 0; 555 if (iir & IIR_RXRDY) { 556 lsr = uart_getreg(bas, REG_LSR); | 552 return (0); 553 } 554 ipend = 0; 555 if (iir & IIR_RXRDY) { 556 lsr = uart_getreg(bas, REG_LSR); |
557 mtx_unlock_spin(&sc->sc_hwmtx); | 557 uart_unlock(sc->sc_hwmtx); |
558 if (lsr & LSR_OE) 559 ipend |= SER_INT_OVERRUN; 560 if (lsr & LSR_BI) 561 ipend |= SER_INT_BREAK; 562 if (lsr & LSR_RXRDY) 563 ipend |= SER_INT_RXREADY; 564 } else { | 558 if (lsr & LSR_OE) 559 ipend |= SER_INT_OVERRUN; 560 if (lsr & LSR_BI) 561 ipend |= SER_INT_BREAK; 562 if (lsr & LSR_RXRDY) 563 ipend |= SER_INT_RXREADY; 564 } else { |
565 mtx_unlock_spin(&sc->sc_hwmtx); | 565 uart_unlock(sc->sc_hwmtx); |
566 if (iir & IIR_TXRDY) 567 ipend |= SER_INT_TXIDLE; 568 else 569 ipend |= SER_INT_SIGCHG; 570 } 571 return ((sc->sc_leaving) ? 0 : ipend); 572} 573 574static int 575ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 576 int stopbits, int parity) 577{ 578 struct uart_bas *bas; 579 int error; 580 581 bas = &sc->sc_bas; | 566 if (iir & IIR_TXRDY) 567 ipend |= SER_INT_TXIDLE; 568 else 569 ipend |= SER_INT_SIGCHG; 570 } 571 return ((sc->sc_leaving) ? 0 : ipend); 572} 573 574static int 575ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 576 int stopbits, int parity) 577{ 578 struct uart_bas *bas; 579 int error; 580 581 bas = &sc->sc_bas; |
582 mtx_lock_spin(&sc->sc_hwmtx); | 582 uart_lock(sc->sc_hwmtx); |
583 error = ns8250_param(bas, baudrate, databits, stopbits, parity); | 583 error = ns8250_param(bas, baudrate, databits, stopbits, parity); |
584 mtx_unlock_spin(&sc->sc_hwmtx); | 584 uart_unlock(sc->sc_hwmtx); |
585 return (error); 586} 587 588static int 589ns8250_bus_probe(struct uart_softc *sc) 590{ 591 struct uart_bas *bas; 592 int count, delay, error, limit; --- 142 unchanged lines hidden (view full) --- 735static int 736ns8250_bus_receive(struct uart_softc *sc) 737{ 738 struct uart_bas *bas; 739 int xc; 740 uint8_t lsr; 741 742 bas = &sc->sc_bas; | 585 return (error); 586} 587 588static int 589ns8250_bus_probe(struct uart_softc *sc) 590{ 591 struct uart_bas *bas; 592 int count, delay, error, limit; --- 142 unchanged lines hidden (view full) --- 735static int 736ns8250_bus_receive(struct uart_softc *sc) 737{ 738 struct uart_bas *bas; 739 int xc; 740 uint8_t lsr; 741 742 bas = &sc->sc_bas; |
743 mtx_lock_spin(&sc->sc_hwmtx); | 743 uart_lock(sc->sc_hwmtx); |
744 lsr = uart_getreg(bas, REG_LSR); 745 while (lsr & LSR_RXRDY) { 746 if (uart_rx_full(sc)) { 747 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 748 break; 749 } 750 xc = uart_getreg(bas, REG_DATA); 751 if (lsr & LSR_FE) --- 4 unchanged lines hidden (view full) --- 756 lsr = uart_getreg(bas, REG_LSR); 757 } 758 /* Discard everything left in the Rx FIFO. */ 759 while (lsr & LSR_RXRDY) { 760 (void)uart_getreg(bas, REG_DATA); 761 uart_barrier(bas); 762 lsr = uart_getreg(bas, REG_LSR); 763 } | 744 lsr = uart_getreg(bas, REG_LSR); 745 while (lsr & LSR_RXRDY) { 746 if (uart_rx_full(sc)) { 747 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 748 break; 749 } 750 xc = uart_getreg(bas, REG_DATA); 751 if (lsr & LSR_FE) --- 4 unchanged lines hidden (view full) --- 756 lsr = uart_getreg(bas, REG_LSR); 757 } 758 /* Discard everything left in the Rx FIFO. */ 759 while (lsr & LSR_RXRDY) { 760 (void)uart_getreg(bas, REG_DATA); 761 uart_barrier(bas); 762 lsr = uart_getreg(bas, REG_LSR); 763 } |
764 mtx_unlock_spin(&sc->sc_hwmtx); | 764 uart_unlock(sc->sc_hwmtx); |
765 return (0); 766} 767 768static int 769ns8250_bus_setsig(struct uart_softc *sc, int sig) 770{ 771 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 772 struct uart_bas *bas; --- 7 unchanged lines hidden (view full) --- 780 SIGCHG(sig & SER_DTR, new, SER_DTR, 781 SER_DDTR); 782 } 783 if (sig & SER_DRTS) { 784 SIGCHG(sig & SER_RTS, new, SER_RTS, 785 SER_DRTS); 786 } 787 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); | 765 return (0); 766} 767 768static int 769ns8250_bus_setsig(struct uart_softc *sc, int sig) 770{ 771 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 772 struct uart_bas *bas; --- 7 unchanged lines hidden (view full) --- 780 SIGCHG(sig & SER_DTR, new, SER_DTR, 781 SER_DDTR); 782 } 783 if (sig & SER_DRTS) { 784 SIGCHG(sig & SER_RTS, new, SER_RTS, 785 SER_DRTS); 786 } 787 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); |
788 mtx_lock_spin(&sc->sc_hwmtx); | 788 uart_lock(sc->sc_hwmtx); |
789 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 790 if (new & SER_DTR) 791 ns8250->mcr |= MCR_DTR; 792 if (new & SER_RTS) 793 ns8250->mcr |= MCR_RTS; 794 uart_setreg(bas, REG_MCR, ns8250->mcr); 795 uart_barrier(bas); | 789 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 790 if (new & SER_DTR) 791 ns8250->mcr |= MCR_DTR; 792 if (new & SER_RTS) 793 ns8250->mcr |= MCR_RTS; 794 uart_setreg(bas, REG_MCR, ns8250->mcr); 795 uart_barrier(bas); |
796 mtx_unlock_spin(&sc->sc_hwmtx); | 796 uart_unlock(sc->sc_hwmtx); |
797 return (0); 798} 799 800static int 801ns8250_bus_transmit(struct uart_softc *sc) 802{ 803 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 804 struct uart_bas *bas; 805 int i; 806 807 bas = &sc->sc_bas; | 797 return (0); 798} 799 800static int 801ns8250_bus_transmit(struct uart_softc *sc) 802{ 803 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 804 struct uart_bas *bas; 805 int i; 806 807 bas = &sc->sc_bas; |
808 mtx_lock_spin(&sc->sc_hwmtx); | 808 uart_lock(sc->sc_hwmtx); |
809 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 810 ; 811 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 812 uart_barrier(bas); 813 for (i = 0; i < sc->sc_txdatasz; i++) { 814 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 815 uart_barrier(bas); 816 } 817 sc->sc_txbusy = 1; | 809 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 810 ; 811 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 812 uart_barrier(bas); 813 for (i = 0; i < sc->sc_txdatasz; i++) { 814 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 815 uart_barrier(bas); 816 } 817 sc->sc_txbusy = 1; |
818 mtx_unlock_spin(&sc->sc_hwmtx); | 818 uart_unlock(sc->sc_hwmtx); |
819 return (0); 820} | 819 return (0); 820} |