1/*-
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 157300 2006-03-30 18:37:03Z marcel $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39
40#include <dev/ic/ns16550.h>
41
42#include "uart_if.h"
43
44#define DEFAULT_RCLK 1843200
45
46/*
47 * Clear pending interrupts. THRE is cleared by reading IIR. Data
48 * that may have been received gets lost here.
49 */
50static void
51ns8250_clrint(struct uart_bas *bas)
52{
53 uint8_t iir;
54
55 iir = uart_getreg(bas, REG_IIR);
56 while ((iir & IIR_NOPEND) == 0) {
57 iir &= IIR_IMASK;
58 if (iir == IIR_RLS)
59 (void)uart_getreg(bas, REG_LSR);
60 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
61 (void)uart_getreg(bas, REG_DATA);
62 else if (iir == IIR_MLSC)
63 (void)uart_getreg(bas, REG_MSR);
64 uart_barrier(bas);
65 iir = uart_getreg(bas, REG_IIR);
66 }
67}
68
69static int
70ns8250_delay(struct uart_bas *bas)
71{
72 int divisor;
73 u_char lcr;
74
75 lcr = uart_getreg(bas, REG_LCR);
76 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
77 uart_barrier(bas);
78 divisor = uart_getdreg(bas, REG_DL);
79 uart_barrier(bas);
80 uart_setreg(bas, REG_LCR, lcr);
81 uart_barrier(bas);
82
83 /* 1/10th the time to transmit 1 character (estimate). */
84 return (16000000 * divisor / bas->rclk);
85}
86
87static int
88ns8250_divisor(int rclk, int baudrate)
89{
90 int actual_baud, divisor;
91 int error;
92
93 if (baudrate == 0)
94 return (0);
95
96 divisor = (rclk / (baudrate << 3) + 1) >> 1;
97 if (divisor == 0 || divisor >= 65536)
98 return (0);
99 actual_baud = rclk / (divisor << 4);
100
101 /* 10 times error in percent: */
102 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
103
104 /* 3.0% maximum error tolerance: */
105 if (error < -30 || error > 30)
106 return (0);
107
108 return (divisor);
109}
110
111static int
112ns8250_drain(struct uart_bas *bas, int what)
113{
114 int delay, limit;
115
116 delay = ns8250_delay(bas);
117
118 if (what & UART_DRAIN_TRANSMITTER) {
119 /*
120 * Pick an arbitrary high limit to avoid getting stuck in
121 * an infinite loop when the hardware is broken. Make the
122 * limit high enough to handle large FIFOs.
123 */
124 limit = 10*1024;
125 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
126 DELAY(delay);
127 if (limit == 0) {
128 /* printf("ns8250: transmitter appears stuck... "); */
129 return (EIO);
130 }
131 }
132
133 if (what & UART_DRAIN_RECEIVER) {
134 /*
135 * Pick an arbitrary high limit to avoid getting stuck in
136 * an infinite loop when the hardware is broken. Make the
137 * limit high enough to handle large FIFOs and integrated
138 * UARTs. The HP rx2600 for example has 3 UARTs on the
139 * management board that tend to get a lot of data send
140 * to it when the UART is first activated.
141 */
142 limit=10*4096;
143 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
144 (void)uart_getreg(bas, REG_DATA);
145 uart_barrier(bas);
146 DELAY(delay << 2);
147 }
148 if (limit == 0) {
149 /* printf("ns8250: receiver appears broken... "); */
150 return (EIO);
151 }
152 }
153
154 return (0);
155}
156
157/*
158 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
159 * drained. WARNING: this function clobbers the FIFO setting!
160 */
161static void
162ns8250_flush(struct uart_bas *bas, int what)
163{
164 uint8_t fcr;
165
166 fcr = FCR_ENABLE;
167 if (what & UART_FLUSH_TRANSMITTER)
168 fcr |= FCR_XMT_RST;
169 if (what & UART_FLUSH_RECEIVER)
170 fcr |= FCR_RCV_RST;
171 uart_setreg(bas, REG_FCR, fcr);
172 uart_barrier(bas);
173}
174
175static int
176ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
177 int parity)
178{
179 int divisor;
180 uint8_t lcr;
181
182 lcr = 0;
183 if (databits >= 8)
184 lcr |= LCR_8BITS;
185 else if (databits == 7)
186 lcr |= LCR_7BITS;
187 else if (databits == 6)
188 lcr |= LCR_6BITS;
189 else
190 lcr |= LCR_5BITS;
191 if (stopbits > 1)
192 lcr |= LCR_STOPB;
193 lcr |= parity << 3;
194
195 /* Set baudrate. */
196 if (baudrate > 0) {
197 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
198 uart_barrier(bas);
199 divisor = ns8250_divisor(bas->rclk, baudrate);
200 if (divisor == 0)
201 return (EINVAL);
202 uart_setdreg(bas, REG_DL, divisor);
203 uart_barrier(bas);
204 }
205
206 /* Set LCR and clear DLAB. */
207 uart_setreg(bas, REG_LCR, lcr);
208 uart_barrier(bas);
209 return (0);
210}
211
212/*
213 * Low-level UART interface.
214 */
215static int ns8250_probe(struct uart_bas *bas);
216static void ns8250_init(struct uart_bas *bas, int, int, int, int);
217static void ns8250_term(struct uart_bas *bas);
218static void ns8250_putc(struct uart_bas *bas, int);
219static int ns8250_poll(struct uart_bas *bas);
220static int ns8250_getc(struct uart_bas *bas);
221
222struct uart_ops uart_ns8250_ops = {
223 .probe = ns8250_probe,
224 .init = ns8250_init,
225 .term = ns8250_term,
226 .putc = ns8250_putc,
227 .poll = ns8250_poll,
228 .getc = ns8250_getc,
229};
230
231static int
232ns8250_probe(struct uart_bas *bas)
233{
234 u_char lcr, val;
235
236 /* Check known 0 bits that don't depend on DLAB. */
237 val = uart_getreg(bas, REG_IIR);
238 if (val & 0x30)
239 return (ENXIO);
240 val = uart_getreg(bas, REG_MCR);
241 if (val & 0xe0)
242 return (ENXIO);
243
244 lcr = uart_getreg(bas, REG_LCR);
245 uart_setreg(bas, REG_LCR, lcr & ~LCR_DLAB);
246 uart_barrier(bas);
247
248 /* Check known 0 bits that depend on !DLAB. */
249 val = uart_getreg(bas, REG_IER);
250 if (val & 0xf0)
251 goto fail;
252
253 uart_setreg(bas, REG_LCR, lcr);
254 uart_barrier(bas);
255 return (0);
256
257 fail:
258 uart_setreg(bas, REG_LCR, lcr);
259 uart_barrier(bas);
260 return (ENXIO);
261}
262
263static void
264ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
265 int parity)
266{
267
268 if (bas->rclk == 0)
269 bas->rclk = DEFAULT_RCLK;
270 ns8250_param(bas, baudrate, databits, stopbits, parity);
271
272 /* Disable all interrupt sources. */
273 uart_setreg(bas, REG_IER, 0);
274 uart_barrier(bas);
275
276 /* Disable the FIFO (if present). */
277 uart_setreg(bas, REG_FCR, 0);
278 uart_barrier(bas);
279
280 /* Set RTS & DTR. */
281 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
282 uart_barrier(bas);
283
284 ns8250_clrint(bas);
285}
286
287static void
288ns8250_term(struct uart_bas *bas)
289{
290
291 /* Clear RTS & DTR. */
292 uart_setreg(bas, REG_MCR, MCR_IE);
293 uart_barrier(bas);
294}
295
296static void
297ns8250_putc(struct uart_bas *bas, int c)
298{
299 int delay, limit;
300
301 /* 1/10th the time to transmit 1 character (estimate). */
302 delay = ns8250_delay(bas);
303
304 limit = 20;
305 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
306 DELAY(delay);
307 uart_setreg(bas, REG_DATA, c);
308 uart_barrier(bas);
309 limit = 40;
310 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
311 DELAY(delay);
312}
313
314static int
315ns8250_poll(struct uart_bas *bas)
316{
317
318 if (uart_getreg(bas, REG_LSR) & LSR_RXRDY)
319 return (uart_getreg(bas, REG_DATA));
320 return (-1);
321}
322
323static int
324ns8250_getc(struct uart_bas *bas)
325{
326 int delay;
327
328 /* 1/10th the time to transmit 1 character (estimate). */
329 delay = ns8250_delay(bas);
330
331 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0)
332 DELAY(delay);
333 return (uart_getreg(bas, REG_DATA));
334}
335
336/*
337 * High-level UART interface.
338 */
339struct ns8250_softc {
340 struct uart_softc base;
341 uint8_t fcr;
342 uint8_t ier;
343 uint8_t mcr;
344};
345
346static int ns8250_bus_attach(struct uart_softc *);
347static int ns8250_bus_detach(struct uart_softc *);
348static int ns8250_bus_flush(struct uart_softc *, int);
349static int ns8250_bus_getsig(struct uart_softc *);
350static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
351static int ns8250_bus_ipend(struct uart_softc *);
352static int ns8250_bus_param(struct uart_softc *, int, int, int, int);
353static int ns8250_bus_probe(struct uart_softc *);
354static int ns8250_bus_receive(struct uart_softc *);
355static int ns8250_bus_setsig(struct uart_softc *, int);
356static int ns8250_bus_transmit(struct uart_softc *);
357
358static kobj_method_t ns8250_methods[] = {
359 KOBJMETHOD(uart_attach, ns8250_bus_attach),
360 KOBJMETHOD(uart_detach, ns8250_bus_detach),
361 KOBJMETHOD(uart_flush, ns8250_bus_flush),
362 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
363 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
364 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
365 KOBJMETHOD(uart_param, ns8250_bus_param),
366 KOBJMETHOD(uart_probe, ns8250_bus_probe),
367 KOBJMETHOD(uart_receive, ns8250_bus_receive),
368 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
369 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
370 { 0, 0 }
371};
372
373struct uart_class uart_ns8250_class = {
374 "ns8250 class",
375 ns8250_methods,
376 sizeof(struct ns8250_softc),
377 .uc_range = 8,
378 .uc_rclk = DEFAULT_RCLK
379};
380
381#define SIGCHG(c, i, s, d) \
382 if (c) { \
383 i |= (i & s) ? s : s | d; \
384 } else { \
385 i = (i & s) ? (i & ~s) | d : i; \
386 }
387
388static int
389ns8250_bus_attach(struct uart_softc *sc)
390{
391 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
392 struct uart_bas *bas;
393
394 bas = &sc->sc_bas;
395
396 ns8250->mcr = uart_getreg(bas, REG_MCR);
397 ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH;
398 uart_setreg(bas, REG_FCR, ns8250->fcr);
399 uart_barrier(bas);
400 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
401
402 if (ns8250->mcr & MCR_DTR)
403 sc->sc_hwsig |= SER_DTR;
404 if (ns8250->mcr & MCR_RTS)
405 sc->sc_hwsig |= SER_RTS;
406 ns8250_bus_getsig(sc);
407
408 ns8250_clrint(bas);
409 ns8250->ier = IER_EMSC | IER_ERLS | IER_ERXRDY;
410 uart_setreg(bas, REG_IER, ns8250->ier);
411 uart_barrier(bas);
412 return (0);
413}
414
415static int
416ns8250_bus_detach(struct uart_softc *sc)
417{
418 struct uart_bas *bas;
419
420 bas = &sc->sc_bas;
421 uart_setreg(bas, REG_IER, 0);
422 uart_barrier(bas);
423 ns8250_clrint(bas);
424 return (0);
425}
426
427static int
428ns8250_bus_flush(struct uart_softc *sc, int what)
429{
430 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
431 struct uart_bas *bas;
432 int error;
433
434 bas = &sc->sc_bas;
435 uart_lock(sc->sc_hwmtx);
436 if (sc->sc_hasfifo) {
437 ns8250_flush(bas, what);
438 uart_setreg(bas, REG_FCR, ns8250->fcr);
439 uart_barrier(bas);
440 error = 0;
441 } else
442 error = ns8250_drain(bas, what);
443 uart_unlock(sc->sc_hwmtx);
444 return (error);
445}
446
447static int
448ns8250_bus_getsig(struct uart_softc *sc)
449{
450 uint32_t new, old, sig;
451 uint8_t msr;
452
453 do {
454 old = sc->sc_hwsig;
455 sig = old;
456 uart_lock(sc->sc_hwmtx);
457 msr = uart_getreg(&sc->sc_bas, REG_MSR);
458 uart_unlock(sc->sc_hwmtx);
459 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
460 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
461 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
462 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
463 new = sig & ~SER_MASK_DELTA;
464 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
465 return (sig);
466}
467
468static int
469ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
470{
471 struct uart_bas *bas;
472 int baudrate, divisor, error;
473 uint8_t efr, lcr;
474
475 bas = &sc->sc_bas;
476 error = 0;
477 uart_lock(sc->sc_hwmtx);
478 switch (request) {
479 case UART_IOCTL_BREAK:
480 lcr = uart_getreg(bas, REG_LCR);
481 if (data)
482 lcr |= LCR_SBREAK;
483 else
484 lcr &= ~LCR_SBREAK;
485 uart_setreg(bas, REG_LCR, lcr);
486 uart_barrier(bas);
487 break;
488 case UART_IOCTL_IFLOW:
489 lcr = uart_getreg(bas, REG_LCR);
490 uart_barrier(bas);
491 uart_setreg(bas, REG_LCR, 0xbf);
492 uart_barrier(bas);
493 efr = uart_getreg(bas, REG_EFR);
494 if (data)
495 efr |= EFR_RTS;
496 else
497 efr &= ~EFR_RTS;
498 uart_setreg(bas, REG_EFR, efr);
499 uart_barrier(bas);
500 uart_setreg(bas, REG_LCR, lcr);
501 uart_barrier(bas);
502 break;
503 case UART_IOCTL_OFLOW:
504 lcr = uart_getreg(bas, REG_LCR);
505 uart_barrier(bas);
506 uart_setreg(bas, REG_LCR, 0xbf);
507 uart_barrier(bas);
508 efr = uart_getreg(bas, REG_EFR);
509 if (data)
510 efr |= EFR_CTS;
511 else
512 efr &= ~EFR_CTS;
513 uart_setreg(bas, REG_EFR, efr);
514 uart_barrier(bas);
515 uart_setreg(bas, REG_LCR, lcr);
516 uart_barrier(bas);
517 break;
518 case UART_IOCTL_BAUD:
519 lcr = uart_getreg(bas, REG_LCR);
520 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
521 uart_barrier(bas);
522 divisor = uart_getdreg(bas, REG_DL);
523 uart_barrier(bas);
524 uart_setreg(bas, REG_LCR, lcr);
525 uart_barrier(bas);
526 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
527 if (baudrate > 0)
528 *(int*)data = baudrate;
529 else
530 error = ENXIO;
531 break;
532 default:
533 error = EINVAL;
534 break;
535 }
536 uart_unlock(sc->sc_hwmtx);
537 return (error);
538}
539
540static int
541ns8250_bus_ipend(struct uart_softc *sc)
542{
543 struct uart_bas *bas;
544 int ipend;
545 uint8_t iir, lsr;
546
547 bas = &sc->sc_bas;
548 uart_lock(sc->sc_hwmtx);
549 iir = uart_getreg(bas, REG_IIR);
550 if (iir & IIR_NOPEND) {
551 uart_unlock(sc->sc_hwmtx);
552 return (0);
553 }
554 ipend = 0;
555 if (iir & IIR_RXRDY) {
556 lsr = uart_getreg(bas, REG_LSR);
557 uart_unlock(sc->sc_hwmtx);
558 if (lsr & LSR_OE)
559 ipend |= SER_INT_OVERRUN;
560 if (lsr & LSR_BI)
561 ipend |= SER_INT_BREAK;
562 if (lsr & LSR_RXRDY)
563 ipend |= SER_INT_RXREADY;
564 } else {
565 uart_unlock(sc->sc_hwmtx);
566 if (iir & IIR_TXRDY)
567 ipend |= SER_INT_TXIDLE;
568 else
569 ipend |= SER_INT_SIGCHG;
570 }
571 return ((sc->sc_leaving) ? 0 : ipend);
572}
573
574static int
575ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
576 int stopbits, int parity)
577{
578 struct uart_bas *bas;
579 int error;
580
581 bas = &sc->sc_bas;
582 uart_lock(sc->sc_hwmtx);
583 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
584 uart_unlock(sc->sc_hwmtx);
585 return (error);
586}
587
588static int
589ns8250_bus_probe(struct uart_softc *sc)
590{
591 struct uart_bas *bas;
592 int count, delay, error, limit;
593 uint8_t lsr, mcr;
594
595 bas = &sc->sc_bas;
596
597 error = ns8250_probe(bas);
598 if (error)
599 return (error);
600
601 mcr = MCR_IE;
602 if (sc->sc_sysdev == NULL) {
603 /* By using ns8250_init() we also set DTR and RTS. */
604 ns8250_init(bas, 9600, 8, 1, UART_PARITY_NONE);
605 } else
606 mcr |= MCR_DTR | MCR_RTS;
607
608 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
609 if (error)
610 return (error);
611
612 /*
613 * Set loopback mode. This avoids having garbage on the wire and
614 * also allows us send and receive data. We set DTR and RTS to
615 * avoid the possibility that automatic flow-control prevents
616 * any data from being sent.
617 */
618 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
619 uart_barrier(bas);
620
621 /*
622 * Enable FIFOs. And check that the UART has them. If not, we're
623 * done. Since this is the first time we enable the FIFOs, we reset
624 * them.
625 */
626 uart_setreg(bas, REG_FCR, FCR_ENABLE);
627 uart_barrier(bas);
628 sc->sc_hasfifo = (uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK) ? 1 : 0;
629 if (!sc->sc_hasfifo) {
630 /*
631 * NS16450 or INS8250. We don't bother to differentiate
632 * between them. They're too old to be interesting.
633 */
634 uart_setreg(bas, REG_MCR, mcr);
635 uart_barrier(bas);
636 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
637 return (0);
638 }
639
640 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
641 uart_barrier(bas);
642
643 count = 0;
644 delay = ns8250_delay(bas);
645
646 /* We have FIFOs. Drain the transmitter and receiver. */
647 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
648 if (error) {
649 uart_setreg(bas, REG_MCR, mcr);
650 uart_setreg(bas, REG_FCR, 0);
651 uart_barrier(bas);
652 goto describe;
653 }
654
655 /*
656 * We should have a sufficiently clean "pipe" to determine the
657 * size of the FIFOs. We send as much characters as is reasonable
658 * and wait for the the overflow bit in the LSR register to be
659 * asserted, counting the characters as we send them. Based on
660 * that count we know the FIFO size.
661 */
662 do {
663 uart_setreg(bas, REG_DATA, 0);
664 uart_barrier(bas);
665 count++;
666
667 limit = 30;
668 lsr = 0;
669 /*
670 * LSR bits are cleared upon read, so we must accumulate
671 * them to be able to test LSR_OE below.
672 */
673 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
674 --limit)
675 DELAY(delay);
676 if (limit == 0) {
677 uart_setreg(bas, REG_IER, 0);
678 uart_setreg(bas, REG_MCR, mcr);
679 uart_setreg(bas, REG_FCR, 0);
680 uart_barrier(bas);
681 count = 0;
682 goto describe;
683 }
684 } while ((lsr & LSR_OE) == 0 && count < 130);
685 count--;
686
687 uart_setreg(bas, REG_MCR, mcr);
688
689 /* Reset FIFOs. */
690 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
691
692 describe:
693 if (count >= 14 && count <= 16) {
694 sc->sc_rxfifosz = 16;
695 device_set_desc(sc->sc_dev, "16550 or compatible");
696 } else if (count >= 28 && count <= 32) {
697 sc->sc_rxfifosz = 32;
698 device_set_desc(sc->sc_dev, "16650 or compatible");
699 } else if (count >= 56 && count <= 64) {
700 sc->sc_rxfifosz = 64;
701 device_set_desc(sc->sc_dev, "16750 or compatible");
702 } else if (count >= 112 && count <= 128) {
703 sc->sc_rxfifosz = 128;
704 device_set_desc(sc->sc_dev, "16950 or compatible");
705 } else {
706 sc->sc_rxfifosz = 16;
707 device_set_desc(sc->sc_dev,
708 "Non-standard ns8250 class UART with FIFOs");
709 }
710
711 /*
712 * Force the Tx FIFO size to 16 bytes for now. We don't program the
713 * Tx trigger. Also, we assume that all data has been sent when the
714 * interrupt happens.
715 */
716 sc->sc_txfifosz = 16;
717
718#if 0
719 /*
720 * XXX there are some issues related to hardware flow control and
721 * it's likely that uart(4) is the cause. This basicly needs more
722 * investigation, but we avoid using for hardware flow control
723 * until then.
724 */
725 /* 16650s or higher have automatic flow control. */
726 if (sc->sc_rxfifosz > 16) {
727 sc->sc_hwiflow = 1;
728 sc->sc_hwoflow = 1;
729 }
730#endif
731
732 return (0);
733}
734
735static int
736ns8250_bus_receive(struct uart_softc *sc)
737{
738 struct uart_bas *bas;
739 int xc;
740 uint8_t lsr;
741
742 bas = &sc->sc_bas;
743 uart_lock(sc->sc_hwmtx);
744 lsr = uart_getreg(bas, REG_LSR);
745 while (lsr & LSR_RXRDY) {
746 if (uart_rx_full(sc)) {
747 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
748 break;
749 }
750 xc = uart_getreg(bas, REG_DATA);
751 if (lsr & LSR_FE)
752 xc |= UART_STAT_FRAMERR;
753 if (lsr & LSR_PE)
754 xc |= UART_STAT_PARERR;
755 uart_rx_put(sc, xc);
756 lsr = uart_getreg(bas, REG_LSR);
757 }
758 /* Discard everything left in the Rx FIFO. */
759 while (lsr & LSR_RXRDY) {
760 (void)uart_getreg(bas, REG_DATA);
761 uart_barrier(bas);
762 lsr = uart_getreg(bas, REG_LSR);
763 }
764 uart_unlock(sc->sc_hwmtx);
765 return (0);
766}
767
768static int
769ns8250_bus_setsig(struct uart_softc *sc, int sig)
770{
771 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
772 struct uart_bas *bas;
773 uint32_t new, old;
774
775 bas = &sc->sc_bas;
776 do {
777 old = sc->sc_hwsig;
778 new = old;
779 if (sig & SER_DDTR) {
780 SIGCHG(sig & SER_DTR, new, SER_DTR,
781 SER_DDTR);
782 }
783 if (sig & SER_DRTS) {
784 SIGCHG(sig & SER_RTS, new, SER_RTS,
785 SER_DRTS);
786 }
787 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
788 uart_lock(sc->sc_hwmtx);
789 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
790 if (new & SER_DTR)
791 ns8250->mcr |= MCR_DTR;
792 if (new & SER_RTS)
793 ns8250->mcr |= MCR_RTS;
794 uart_setreg(bas, REG_MCR, ns8250->mcr);
795 uart_barrier(bas);
796 uart_unlock(sc->sc_hwmtx);
797 return (0);
798}
799
800static int
801ns8250_bus_transmit(struct uart_softc *sc)
802{
803 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
804 struct uart_bas *bas;
805 int i;
806
807 bas = &sc->sc_bas;
808 uart_lock(sc->sc_hwmtx);
809 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
810 ;
811 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
812 uart_barrier(bas);
813 for (i = 0; i < sc->sc_txdatasz; i++) {
814 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
815 uart_barrier(bas);
816 }
817 sc->sc_txbusy = 1;
818 uart_unlock(sc->sc_hwmtx);
819 return (0);
820}
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 157300 2006-03-30 18:37:03Z marcel $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39
40#include <dev/ic/ns16550.h>
41
42#include "uart_if.h"
43
44#define DEFAULT_RCLK 1843200
45
46/*
47 * Clear pending interrupts. THRE is cleared by reading IIR. Data
48 * that may have been received gets lost here.
49 */
50static void
51ns8250_clrint(struct uart_bas *bas)
52{
53 uint8_t iir;
54
55 iir = uart_getreg(bas, REG_IIR);
56 while ((iir & IIR_NOPEND) == 0) {
57 iir &= IIR_IMASK;
58 if (iir == IIR_RLS)
59 (void)uart_getreg(bas, REG_LSR);
60 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
61 (void)uart_getreg(bas, REG_DATA);
62 else if (iir == IIR_MLSC)
63 (void)uart_getreg(bas, REG_MSR);
64 uart_barrier(bas);
65 iir = uart_getreg(bas, REG_IIR);
66 }
67}
68
69static int
70ns8250_delay(struct uart_bas *bas)
71{
72 int divisor;
73 u_char lcr;
74
75 lcr = uart_getreg(bas, REG_LCR);
76 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
77 uart_barrier(bas);
78 divisor = uart_getdreg(bas, REG_DL);
79 uart_barrier(bas);
80 uart_setreg(bas, REG_LCR, lcr);
81 uart_barrier(bas);
82
83 /* 1/10th the time to transmit 1 character (estimate). */
84 return (16000000 * divisor / bas->rclk);
85}
86
87static int
88ns8250_divisor(int rclk, int baudrate)
89{
90 int actual_baud, divisor;
91 int error;
92
93 if (baudrate == 0)
94 return (0);
95
96 divisor = (rclk / (baudrate << 3) + 1) >> 1;
97 if (divisor == 0 || divisor >= 65536)
98 return (0);
99 actual_baud = rclk / (divisor << 4);
100
101 /* 10 times error in percent: */
102 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
103
104 /* 3.0% maximum error tolerance: */
105 if (error < -30 || error > 30)
106 return (0);
107
108 return (divisor);
109}
110
111static int
112ns8250_drain(struct uart_bas *bas, int what)
113{
114 int delay, limit;
115
116 delay = ns8250_delay(bas);
117
118 if (what & UART_DRAIN_TRANSMITTER) {
119 /*
120 * Pick an arbitrary high limit to avoid getting stuck in
121 * an infinite loop when the hardware is broken. Make the
122 * limit high enough to handle large FIFOs.
123 */
124 limit = 10*1024;
125 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
126 DELAY(delay);
127 if (limit == 0) {
128 /* printf("ns8250: transmitter appears stuck... "); */
129 return (EIO);
130 }
131 }
132
133 if (what & UART_DRAIN_RECEIVER) {
134 /*
135 * Pick an arbitrary high limit to avoid getting stuck in
136 * an infinite loop when the hardware is broken. Make the
137 * limit high enough to handle large FIFOs and integrated
138 * UARTs. The HP rx2600 for example has 3 UARTs on the
139 * management board that tend to get a lot of data send
140 * to it when the UART is first activated.
141 */
142 limit=10*4096;
143 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
144 (void)uart_getreg(bas, REG_DATA);
145 uart_barrier(bas);
146 DELAY(delay << 2);
147 }
148 if (limit == 0) {
149 /* printf("ns8250: receiver appears broken... "); */
150 return (EIO);
151 }
152 }
153
154 return (0);
155}
156
157/*
158 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
159 * drained. WARNING: this function clobbers the FIFO setting!
160 */
161static void
162ns8250_flush(struct uart_bas *bas, int what)
163{
164 uint8_t fcr;
165
166 fcr = FCR_ENABLE;
167 if (what & UART_FLUSH_TRANSMITTER)
168 fcr |= FCR_XMT_RST;
169 if (what & UART_FLUSH_RECEIVER)
170 fcr |= FCR_RCV_RST;
171 uart_setreg(bas, REG_FCR, fcr);
172 uart_barrier(bas);
173}
174
175static int
176ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
177 int parity)
178{
179 int divisor;
180 uint8_t lcr;
181
182 lcr = 0;
183 if (databits >= 8)
184 lcr |= LCR_8BITS;
185 else if (databits == 7)
186 lcr |= LCR_7BITS;
187 else if (databits == 6)
188 lcr |= LCR_6BITS;
189 else
190 lcr |= LCR_5BITS;
191 if (stopbits > 1)
192 lcr |= LCR_STOPB;
193 lcr |= parity << 3;
194
195 /* Set baudrate. */
196 if (baudrate > 0) {
197 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
198 uart_barrier(bas);
199 divisor = ns8250_divisor(bas->rclk, baudrate);
200 if (divisor == 0)
201 return (EINVAL);
202 uart_setdreg(bas, REG_DL, divisor);
203 uart_barrier(bas);
204 }
205
206 /* Set LCR and clear DLAB. */
207 uart_setreg(bas, REG_LCR, lcr);
208 uart_barrier(bas);
209 return (0);
210}
211
212/*
213 * Low-level UART interface.
214 */
215static int ns8250_probe(struct uart_bas *bas);
216static void ns8250_init(struct uart_bas *bas, int, int, int, int);
217static void ns8250_term(struct uart_bas *bas);
218static void ns8250_putc(struct uart_bas *bas, int);
219static int ns8250_poll(struct uart_bas *bas);
220static int ns8250_getc(struct uart_bas *bas);
221
222struct uart_ops uart_ns8250_ops = {
223 .probe = ns8250_probe,
224 .init = ns8250_init,
225 .term = ns8250_term,
226 .putc = ns8250_putc,
227 .poll = ns8250_poll,
228 .getc = ns8250_getc,
229};
230
231static int
232ns8250_probe(struct uart_bas *bas)
233{
234 u_char lcr, val;
235
236 /* Check known 0 bits that don't depend on DLAB. */
237 val = uart_getreg(bas, REG_IIR);
238 if (val & 0x30)
239 return (ENXIO);
240 val = uart_getreg(bas, REG_MCR);
241 if (val & 0xe0)
242 return (ENXIO);
243
244 lcr = uart_getreg(bas, REG_LCR);
245 uart_setreg(bas, REG_LCR, lcr & ~LCR_DLAB);
246 uart_barrier(bas);
247
248 /* Check known 0 bits that depend on !DLAB. */
249 val = uart_getreg(bas, REG_IER);
250 if (val & 0xf0)
251 goto fail;
252
253 uart_setreg(bas, REG_LCR, lcr);
254 uart_barrier(bas);
255 return (0);
256
257 fail:
258 uart_setreg(bas, REG_LCR, lcr);
259 uart_barrier(bas);
260 return (ENXIO);
261}
262
263static void
264ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
265 int parity)
266{
267
268 if (bas->rclk == 0)
269 bas->rclk = DEFAULT_RCLK;
270 ns8250_param(bas, baudrate, databits, stopbits, parity);
271
272 /* Disable all interrupt sources. */
273 uart_setreg(bas, REG_IER, 0);
274 uart_barrier(bas);
275
276 /* Disable the FIFO (if present). */
277 uart_setreg(bas, REG_FCR, 0);
278 uart_barrier(bas);
279
280 /* Set RTS & DTR. */
281 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
282 uart_barrier(bas);
283
284 ns8250_clrint(bas);
285}
286
287static void
288ns8250_term(struct uart_bas *bas)
289{
290
291 /* Clear RTS & DTR. */
292 uart_setreg(bas, REG_MCR, MCR_IE);
293 uart_barrier(bas);
294}
295
296static void
297ns8250_putc(struct uart_bas *bas, int c)
298{
299 int delay, limit;
300
301 /* 1/10th the time to transmit 1 character (estimate). */
302 delay = ns8250_delay(bas);
303
304 limit = 20;
305 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
306 DELAY(delay);
307 uart_setreg(bas, REG_DATA, c);
308 uart_barrier(bas);
309 limit = 40;
310 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
311 DELAY(delay);
312}
313
314static int
315ns8250_poll(struct uart_bas *bas)
316{
317
318 if (uart_getreg(bas, REG_LSR) & LSR_RXRDY)
319 return (uart_getreg(bas, REG_DATA));
320 return (-1);
321}
322
323static int
324ns8250_getc(struct uart_bas *bas)
325{
326 int delay;
327
328 /* 1/10th the time to transmit 1 character (estimate). */
329 delay = ns8250_delay(bas);
330
331 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0)
332 DELAY(delay);
333 return (uart_getreg(bas, REG_DATA));
334}
335
336/*
337 * High-level UART interface.
338 */
339struct ns8250_softc {
340 struct uart_softc base;
341 uint8_t fcr;
342 uint8_t ier;
343 uint8_t mcr;
344};
345
346static int ns8250_bus_attach(struct uart_softc *);
347static int ns8250_bus_detach(struct uart_softc *);
348static int ns8250_bus_flush(struct uart_softc *, int);
349static int ns8250_bus_getsig(struct uart_softc *);
350static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
351static int ns8250_bus_ipend(struct uart_softc *);
352static int ns8250_bus_param(struct uart_softc *, int, int, int, int);
353static int ns8250_bus_probe(struct uart_softc *);
354static int ns8250_bus_receive(struct uart_softc *);
355static int ns8250_bus_setsig(struct uart_softc *, int);
356static int ns8250_bus_transmit(struct uart_softc *);
357
358static kobj_method_t ns8250_methods[] = {
359 KOBJMETHOD(uart_attach, ns8250_bus_attach),
360 KOBJMETHOD(uart_detach, ns8250_bus_detach),
361 KOBJMETHOD(uart_flush, ns8250_bus_flush),
362 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
363 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
364 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
365 KOBJMETHOD(uart_param, ns8250_bus_param),
366 KOBJMETHOD(uart_probe, ns8250_bus_probe),
367 KOBJMETHOD(uart_receive, ns8250_bus_receive),
368 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
369 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
370 { 0, 0 }
371};
372
373struct uart_class uart_ns8250_class = {
374 "ns8250 class",
375 ns8250_methods,
376 sizeof(struct ns8250_softc),
377 .uc_range = 8,
378 .uc_rclk = DEFAULT_RCLK
379};
380
381#define SIGCHG(c, i, s, d) \
382 if (c) { \
383 i |= (i & s) ? s : s | d; \
384 } else { \
385 i = (i & s) ? (i & ~s) | d : i; \
386 }
387
388static int
389ns8250_bus_attach(struct uart_softc *sc)
390{
391 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
392 struct uart_bas *bas;
393
394 bas = &sc->sc_bas;
395
396 ns8250->mcr = uart_getreg(bas, REG_MCR);
397 ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH;
398 uart_setreg(bas, REG_FCR, ns8250->fcr);
399 uart_barrier(bas);
400 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
401
402 if (ns8250->mcr & MCR_DTR)
403 sc->sc_hwsig |= SER_DTR;
404 if (ns8250->mcr & MCR_RTS)
405 sc->sc_hwsig |= SER_RTS;
406 ns8250_bus_getsig(sc);
407
408 ns8250_clrint(bas);
409 ns8250->ier = IER_EMSC | IER_ERLS | IER_ERXRDY;
410 uart_setreg(bas, REG_IER, ns8250->ier);
411 uart_barrier(bas);
412 return (0);
413}
414
415static int
416ns8250_bus_detach(struct uart_softc *sc)
417{
418 struct uart_bas *bas;
419
420 bas = &sc->sc_bas;
421 uart_setreg(bas, REG_IER, 0);
422 uart_barrier(bas);
423 ns8250_clrint(bas);
424 return (0);
425}
426
427static int
428ns8250_bus_flush(struct uart_softc *sc, int what)
429{
430 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
431 struct uart_bas *bas;
432 int error;
433
434 bas = &sc->sc_bas;
435 uart_lock(sc->sc_hwmtx);
436 if (sc->sc_hasfifo) {
437 ns8250_flush(bas, what);
438 uart_setreg(bas, REG_FCR, ns8250->fcr);
439 uart_barrier(bas);
440 error = 0;
441 } else
442 error = ns8250_drain(bas, what);
443 uart_unlock(sc->sc_hwmtx);
444 return (error);
445}
446
447static int
448ns8250_bus_getsig(struct uart_softc *sc)
449{
450 uint32_t new, old, sig;
451 uint8_t msr;
452
453 do {
454 old = sc->sc_hwsig;
455 sig = old;
456 uart_lock(sc->sc_hwmtx);
457 msr = uart_getreg(&sc->sc_bas, REG_MSR);
458 uart_unlock(sc->sc_hwmtx);
459 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
460 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
461 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
462 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
463 new = sig & ~SER_MASK_DELTA;
464 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
465 return (sig);
466}
467
468static int
469ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
470{
471 struct uart_bas *bas;
472 int baudrate, divisor, error;
473 uint8_t efr, lcr;
474
475 bas = &sc->sc_bas;
476 error = 0;
477 uart_lock(sc->sc_hwmtx);
478 switch (request) {
479 case UART_IOCTL_BREAK:
480 lcr = uart_getreg(bas, REG_LCR);
481 if (data)
482 lcr |= LCR_SBREAK;
483 else
484 lcr &= ~LCR_SBREAK;
485 uart_setreg(bas, REG_LCR, lcr);
486 uart_barrier(bas);
487 break;
488 case UART_IOCTL_IFLOW:
489 lcr = uart_getreg(bas, REG_LCR);
490 uart_barrier(bas);
491 uart_setreg(bas, REG_LCR, 0xbf);
492 uart_barrier(bas);
493 efr = uart_getreg(bas, REG_EFR);
494 if (data)
495 efr |= EFR_RTS;
496 else
497 efr &= ~EFR_RTS;
498 uart_setreg(bas, REG_EFR, efr);
499 uart_barrier(bas);
500 uart_setreg(bas, REG_LCR, lcr);
501 uart_barrier(bas);
502 break;
503 case UART_IOCTL_OFLOW:
504 lcr = uart_getreg(bas, REG_LCR);
505 uart_barrier(bas);
506 uart_setreg(bas, REG_LCR, 0xbf);
507 uart_barrier(bas);
508 efr = uart_getreg(bas, REG_EFR);
509 if (data)
510 efr |= EFR_CTS;
511 else
512 efr &= ~EFR_CTS;
513 uart_setreg(bas, REG_EFR, efr);
514 uart_barrier(bas);
515 uart_setreg(bas, REG_LCR, lcr);
516 uart_barrier(bas);
517 break;
518 case UART_IOCTL_BAUD:
519 lcr = uart_getreg(bas, REG_LCR);
520 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
521 uart_barrier(bas);
522 divisor = uart_getdreg(bas, REG_DL);
523 uart_barrier(bas);
524 uart_setreg(bas, REG_LCR, lcr);
525 uart_barrier(bas);
526 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
527 if (baudrate > 0)
528 *(int*)data = baudrate;
529 else
530 error = ENXIO;
531 break;
532 default:
533 error = EINVAL;
534 break;
535 }
536 uart_unlock(sc->sc_hwmtx);
537 return (error);
538}
539
540static int
541ns8250_bus_ipend(struct uart_softc *sc)
542{
543 struct uart_bas *bas;
544 int ipend;
545 uint8_t iir, lsr;
546
547 bas = &sc->sc_bas;
548 uart_lock(sc->sc_hwmtx);
549 iir = uart_getreg(bas, REG_IIR);
550 if (iir & IIR_NOPEND) {
551 uart_unlock(sc->sc_hwmtx);
552 return (0);
553 }
554 ipend = 0;
555 if (iir & IIR_RXRDY) {
556 lsr = uart_getreg(bas, REG_LSR);
557 uart_unlock(sc->sc_hwmtx);
558 if (lsr & LSR_OE)
559 ipend |= SER_INT_OVERRUN;
560 if (lsr & LSR_BI)
561 ipend |= SER_INT_BREAK;
562 if (lsr & LSR_RXRDY)
563 ipend |= SER_INT_RXREADY;
564 } else {
565 uart_unlock(sc->sc_hwmtx);
566 if (iir & IIR_TXRDY)
567 ipend |= SER_INT_TXIDLE;
568 else
569 ipend |= SER_INT_SIGCHG;
570 }
571 return ((sc->sc_leaving) ? 0 : ipend);
572}
573
574static int
575ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
576 int stopbits, int parity)
577{
578 struct uart_bas *bas;
579 int error;
580
581 bas = &sc->sc_bas;
582 uart_lock(sc->sc_hwmtx);
583 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
584 uart_unlock(sc->sc_hwmtx);
585 return (error);
586}
587
588static int
589ns8250_bus_probe(struct uart_softc *sc)
590{
591 struct uart_bas *bas;
592 int count, delay, error, limit;
593 uint8_t lsr, mcr;
594
595 bas = &sc->sc_bas;
596
597 error = ns8250_probe(bas);
598 if (error)
599 return (error);
600
601 mcr = MCR_IE;
602 if (sc->sc_sysdev == NULL) {
603 /* By using ns8250_init() we also set DTR and RTS. */
604 ns8250_init(bas, 9600, 8, 1, UART_PARITY_NONE);
605 } else
606 mcr |= MCR_DTR | MCR_RTS;
607
608 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
609 if (error)
610 return (error);
611
612 /*
613 * Set loopback mode. This avoids having garbage on the wire and
614 * also allows us send and receive data. We set DTR and RTS to
615 * avoid the possibility that automatic flow-control prevents
616 * any data from being sent.
617 */
618 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
619 uart_barrier(bas);
620
621 /*
622 * Enable FIFOs. And check that the UART has them. If not, we're
623 * done. Since this is the first time we enable the FIFOs, we reset
624 * them.
625 */
626 uart_setreg(bas, REG_FCR, FCR_ENABLE);
627 uart_barrier(bas);
628 sc->sc_hasfifo = (uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK) ? 1 : 0;
629 if (!sc->sc_hasfifo) {
630 /*
631 * NS16450 or INS8250. We don't bother to differentiate
632 * between them. They're too old to be interesting.
633 */
634 uart_setreg(bas, REG_MCR, mcr);
635 uart_barrier(bas);
636 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
637 return (0);
638 }
639
640 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
641 uart_barrier(bas);
642
643 count = 0;
644 delay = ns8250_delay(bas);
645
646 /* We have FIFOs. Drain the transmitter and receiver. */
647 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
648 if (error) {
649 uart_setreg(bas, REG_MCR, mcr);
650 uart_setreg(bas, REG_FCR, 0);
651 uart_barrier(bas);
652 goto describe;
653 }
654
655 /*
656 * We should have a sufficiently clean "pipe" to determine the
657 * size of the FIFOs. We send as much characters as is reasonable
658 * and wait for the the overflow bit in the LSR register to be
659 * asserted, counting the characters as we send them. Based on
660 * that count we know the FIFO size.
661 */
662 do {
663 uart_setreg(bas, REG_DATA, 0);
664 uart_barrier(bas);
665 count++;
666
667 limit = 30;
668 lsr = 0;
669 /*
670 * LSR bits are cleared upon read, so we must accumulate
671 * them to be able to test LSR_OE below.
672 */
673 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
674 --limit)
675 DELAY(delay);
676 if (limit == 0) {
677 uart_setreg(bas, REG_IER, 0);
678 uart_setreg(bas, REG_MCR, mcr);
679 uart_setreg(bas, REG_FCR, 0);
680 uart_barrier(bas);
681 count = 0;
682 goto describe;
683 }
684 } while ((lsr & LSR_OE) == 0 && count < 130);
685 count--;
686
687 uart_setreg(bas, REG_MCR, mcr);
688
689 /* Reset FIFOs. */
690 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
691
692 describe:
693 if (count >= 14 && count <= 16) {
694 sc->sc_rxfifosz = 16;
695 device_set_desc(sc->sc_dev, "16550 or compatible");
696 } else if (count >= 28 && count <= 32) {
697 sc->sc_rxfifosz = 32;
698 device_set_desc(sc->sc_dev, "16650 or compatible");
699 } else if (count >= 56 && count <= 64) {
700 sc->sc_rxfifosz = 64;
701 device_set_desc(sc->sc_dev, "16750 or compatible");
702 } else if (count >= 112 && count <= 128) {
703 sc->sc_rxfifosz = 128;
704 device_set_desc(sc->sc_dev, "16950 or compatible");
705 } else {
706 sc->sc_rxfifosz = 16;
707 device_set_desc(sc->sc_dev,
708 "Non-standard ns8250 class UART with FIFOs");
709 }
710
711 /*
712 * Force the Tx FIFO size to 16 bytes for now. We don't program the
713 * Tx trigger. Also, we assume that all data has been sent when the
714 * interrupt happens.
715 */
716 sc->sc_txfifosz = 16;
717
718#if 0
719 /*
720 * XXX there are some issues related to hardware flow control and
721 * it's likely that uart(4) is the cause. This basicly needs more
722 * investigation, but we avoid using for hardware flow control
723 * until then.
724 */
725 /* 16650s or higher have automatic flow control. */
726 if (sc->sc_rxfifosz > 16) {
727 sc->sc_hwiflow = 1;
728 sc->sc_hwoflow = 1;
729 }
730#endif
731
732 return (0);
733}
734
735static int
736ns8250_bus_receive(struct uart_softc *sc)
737{
738 struct uart_bas *bas;
739 int xc;
740 uint8_t lsr;
741
742 bas = &sc->sc_bas;
743 uart_lock(sc->sc_hwmtx);
744 lsr = uart_getreg(bas, REG_LSR);
745 while (lsr & LSR_RXRDY) {
746 if (uart_rx_full(sc)) {
747 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
748 break;
749 }
750 xc = uart_getreg(bas, REG_DATA);
751 if (lsr & LSR_FE)
752 xc |= UART_STAT_FRAMERR;
753 if (lsr & LSR_PE)
754 xc |= UART_STAT_PARERR;
755 uart_rx_put(sc, xc);
756 lsr = uart_getreg(bas, REG_LSR);
757 }
758 /* Discard everything left in the Rx FIFO. */
759 while (lsr & LSR_RXRDY) {
760 (void)uart_getreg(bas, REG_DATA);
761 uart_barrier(bas);
762 lsr = uart_getreg(bas, REG_LSR);
763 }
764 uart_unlock(sc->sc_hwmtx);
765 return (0);
766}
767
768static int
769ns8250_bus_setsig(struct uart_softc *sc, int sig)
770{
771 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
772 struct uart_bas *bas;
773 uint32_t new, old;
774
775 bas = &sc->sc_bas;
776 do {
777 old = sc->sc_hwsig;
778 new = old;
779 if (sig & SER_DDTR) {
780 SIGCHG(sig & SER_DTR, new, SER_DTR,
781 SER_DDTR);
782 }
783 if (sig & SER_DRTS) {
784 SIGCHG(sig & SER_RTS, new, SER_RTS,
785 SER_DRTS);
786 }
787 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
788 uart_lock(sc->sc_hwmtx);
789 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
790 if (new & SER_DTR)
791 ns8250->mcr |= MCR_DTR;
792 if (new & SER_RTS)
793 ns8250->mcr |= MCR_RTS;
794 uart_setreg(bas, REG_MCR, ns8250->mcr);
795 uart_barrier(bas);
796 uart_unlock(sc->sc_hwmtx);
797 return (0);
798}
799
800static int
801ns8250_bus_transmit(struct uart_softc *sc)
802{
803 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
804 struct uart_bas *bas;
805 int i;
806
807 bas = &sc->sc_bas;
808 uart_lock(sc->sc_hwmtx);
809 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
810 ;
811 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
812 uart_barrier(bas);
813 for (i = 0; i < sc->sc_txdatasz; i++) {
814 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
815 uart_barrier(bas);
816 }
817 sc->sc_txbusy = 1;
818 uart_unlock(sc->sc_hwmtx);
819 return (0);
820}