| if_tireg.h (67405) | if_tireg.h (72200) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 67405 2000-10-21 00:13:35Z bmilekic $ | 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 72200 2001-02-09 06:11:45Z bmilekic $ |
| 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 1101 unchanged lines hidden (view full) --- 1142 u_int32_t ti_rx_max_coal_bds; 1143 u_int32_t ti_tx_max_coal_bds; 1144 u_int32_t ti_tx_buf_ratio; 1145 int ti_if_flags; 1146 int ti_txcnt; 1147 struct mtx ti_mtx; 1148}; 1149 | 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 1101 unchanged lines hidden (view full) --- 1142 u_int32_t ti_rx_max_coal_bds; 1143 u_int32_t ti_tx_max_coal_bds; 1144 u_int32_t ti_tx_buf_ratio; 1145 int ti_if_flags; 1146 int ti_txcnt; 1147 struct mtx ti_mtx; 1148}; 1149 |
| 1150#define TI_LOCK(_sc) mtx_enter(&(_sc)->ti_mtx, MTX_DEF) 1151#define TI_UNLOCK(_sc) mtx_exit(&(_sc)->ti_mtx, MTX_DEF) | 1150#define TI_LOCK(_sc) mtx_lock(&(_sc)->ti_mtx) 1151#define TI_UNLOCK(_sc) mtx_unlock(&(_sc)->ti_mtx) |
| 1152 1153/* 1154 * Microchip Technology 24Cxx EEPROM control bytes 1155 */ 1156#define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 1157#define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 1158 1159/* --- 27 unchanged lines hidden --- | 1152 1153/* 1154 * Microchip Technology 24Cxx EEPROM control bytes 1155 */ 1156#define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 1157#define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 1158 1159/* --- 27 unchanged lines hidden --- |