| if_tireg.h (64139) | if_tireg.h (64837) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 64139 2000-08-02 18:49:17Z wpaul $ | 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 64837 2000-08-19 08:32:59Z dwmalone $ |
| 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 1000 unchanged lines hidden (view full) --- 1041#define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \ 1042 (TI_JRAWLEN % sizeof(u_int64_t)))) 1043#define TI_JPAGESZ PAGE_SIZE 1044#define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ) 1045#define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID) 1046 1047struct ti_jslot { 1048 caddr_t ti_buf; | 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 1000 unchanged lines hidden (view full) --- 1041#define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \ 1042 (TI_JRAWLEN % sizeof(u_int64_t)))) 1043#define TI_JPAGESZ PAGE_SIZE 1044#define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ) 1045#define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID) 1046 1047struct ti_jslot { 1048 caddr_t ti_buf; |
| 1049 int ti_inuse; | |
| 1050}; 1051 1052/* 1053 * Ring structures. Most of these reside in host memory and we tell 1054 * the NIC where they are via the ring control blocks. The exceptions 1055 * are the tx and command rings, which live in NIC memory and which 1056 * we access via the shared memory window. 1057 */ --- 130 unchanged lines hidden --- | 1049}; 1050 1051/* 1052 * Ring structures. Most of these reside in host memory and we tell 1053 * the NIC where they are via the ring control blocks. The exceptions 1054 * are the tx and command rings, which live in NIC memory and which 1055 * we access via the shared memory window. 1056 */ --- 130 unchanged lines hidden --- |