| if_tireg.h (153982) | if_tireg.h (199559) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 153982 2006-01-03 06:14:07Z yongari $ | 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 199559 2009-11-19 22:06:40Z jhb $ |
| 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 992 unchanged lines hidden (view full) --- 1033 u_int32_t ti_rx_coal_ticks; 1034 u_int32_t ti_tx_coal_ticks; 1035 u_int32_t ti_rx_max_coal_bds; 1036 u_int32_t ti_tx_max_coal_bds; 1037 u_int32_t ti_tx_buf_ratio; 1038 int ti_if_flags; 1039 int ti_txcnt; 1040 struct mtx ti_mtx; | 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 992 unchanged lines hidden (view full) --- 1033 u_int32_t ti_rx_coal_ticks; 1034 u_int32_t ti_tx_coal_ticks; 1035 u_int32_t ti_rx_max_coal_bds; 1036 u_int32_t ti_tx_max_coal_bds; 1037 u_int32_t ti_tx_buf_ratio; 1038 int ti_if_flags; 1039 int ti_txcnt; 1040 struct mtx ti_mtx; |
| 1041 struct callout ti_watchdog; 1042 int ti_timer; |
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| 1041 ti_flag_vals ti_flags; 1042 struct cdev *dev; 1043}; 1044 1045#define TI_LOCK(_sc) mtx_lock(&(_sc)->ti_mtx) 1046#define TI_UNLOCK(_sc) mtx_unlock(&(_sc)->ti_mtx) 1047#define TI_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ti_mtx, MA_OWNED) 1048 --- 30 unchanged lines hidden --- | 1043 ti_flag_vals ti_flags; 1044 struct cdev *dev; 1045}; 1046 1047#define TI_LOCK(_sc) mtx_lock(&(_sc)->ti_mtx) 1048#define TI_UNLOCK(_sc) mtx_unlock(&(_sc)->ti_mtx) 1049#define TI_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ti_mtx, MA_OWNED) 1050 --- 30 unchanged lines hidden --- |