1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
37 *
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
41 */
42
43/*
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
50 * initialization.
51 *
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
55 *
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
60 * stellar example.
61 *
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
68 *
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
71 * for testing
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
77 */
78
79#include <sys/cdefs.h>
80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 195049 2009-06-26 11:45:06Z rwatson $");
81
82#include "opt_ti.h"
83
84#include <sys/param.h>
85#include <sys/systm.h>
86#include <sys/sockio.h>
87#include <sys/mbuf.h>
88#include <sys/malloc.h>
89#include <sys/kernel.h>
90#include <sys/module.h>
91#include <sys/socket.h>
92#include <sys/queue.h>
93#include <sys/conf.h>
94#include <sys/sf_buf.h>
95
96#include <net/if.h>
97#include <net/if_arp.h>
98#include <net/ethernet.h>
99#include <net/if_dl.h>
100#include <net/if_media.h>
101#include <net/if_types.h>
102#include <net/if_vlan_var.h>
103
104#include <net/bpf.h>
105
106#include <netinet/in_systm.h>
107#include <netinet/in.h>
108#include <netinet/ip.h>
109
110#include <machine/bus.h>
111#include <machine/resource.h>
112#include <sys/bus.h>
113#include <sys/rman.h>
114
115/* #define TI_PRIVATE_JUMBOS */
116#ifndef TI_PRIVATE_JUMBOS
117#include <vm/vm.h>
118#include <vm/vm_page.h>
119#endif
120
121#include <dev/pci/pcireg.h>
122#include <dev/pci/pcivar.h>
123
124#include <sys/tiio.h>
125#include <dev/ti/if_tireg.h>
126#include <dev/ti/ti_fw.h>
127#include <dev/ti/ti_fw2.h>
128
129#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
130/*
131 * We can only turn on header splitting if we're using extended receive
132 * BDs.
133 */
134#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
135#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
136#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
137
138typedef enum {
139 TI_SWAP_HTON,
140 TI_SWAP_NTOH
141} ti_swap_type;
142
143
144/*
145 * Various supported device vendors/types and their names.
146 */
147
148static struct ti_type ti_devs[] = {
149 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
152 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
153 { TC_VENDORID, TC_DEVICEID_3C985,
154 "3Com 3c985-SX Gigabit Ethernet" },
155 { NG_VENDORID, NG_DEVICEID_GA620,
156 "Netgear GA620 1000baseSX Gigabit Ethernet" },
157 { NG_VENDORID, NG_DEVICEID_GA620T,
158 "Netgear GA620 1000baseT Gigabit Ethernet" },
159 { SGI_VENDORID, SGI_DEVICEID_TIGON,
160 "Silicon Graphics Gigabit Ethernet" },
161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
162 "Farallon PN9000SX Gigabit Ethernet" },
163 { 0, 0, NULL }
164};
165
166
167static d_open_t ti_open;
168static d_close_t ti_close;
169static d_ioctl_t ti_ioctl2;
170
171static struct cdevsw ti_cdevsw = {
172 .d_version = D_VERSION,
173 .d_flags = 0,
174 .d_open = ti_open,
175 .d_close = ti_close,
176 .d_ioctl = ti_ioctl2,
177 .d_name = "ti",
178};
179
180static int ti_probe(device_t);
181static int ti_attach(device_t);
182static int ti_detach(device_t);
183static void ti_txeof(struct ti_softc *);
184static void ti_rxeof(struct ti_softc *);
185
186static void ti_stats_update(struct ti_softc *);
187static int ti_encap(struct ti_softc *, struct mbuf **);
188
189static void ti_intr(void *);
190static void ti_start(struct ifnet *);
191static void ti_start_locked(struct ifnet *);
192static int ti_ioctl(struct ifnet *, u_long, caddr_t);
193static void ti_init(void *);
194static void ti_init_locked(void *);
195static void ti_init2(struct ti_softc *);
196static void ti_stop(struct ti_softc *);
197static void ti_watchdog(struct ifnet *);
198static int ti_shutdown(device_t);
199static int ti_ifmedia_upd(struct ifnet *);
200static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
201
202static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int);
203static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *);
204static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
205
206static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
207static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
208static void ti_setmulti(struct ti_softc *);
209
210static void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *);
211static void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, void *);
212static void ti_mem_zero(struct ti_softc *, u_int32_t, u_int32_t);
213static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int);
214static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t,
215 int, int, int);
216static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
217static void ti_loadfw(struct ti_softc *);
218static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
219static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
220static void ti_handle_events(struct ti_softc *);
221static int ti_alloc_dmamaps(struct ti_softc *);
222static void ti_free_dmamaps(struct ti_softc *);
223static int ti_alloc_jumbo_mem(struct ti_softc *);
224#ifdef TI_PRIVATE_JUMBOS
225static void *ti_jalloc(struct ti_softc *);
226static void ti_jfree(void *, void *);
227#endif /* TI_PRIVATE_JUMBOS */
228static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
229static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
230static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
231static int ti_init_rx_ring_std(struct ti_softc *);
232static void ti_free_rx_ring_std(struct ti_softc *);
233static int ti_init_rx_ring_jumbo(struct ti_softc *);
234static void ti_free_rx_ring_jumbo(struct ti_softc *);
235static int ti_init_rx_ring_mini(struct ti_softc *);
236static void ti_free_rx_ring_mini(struct ti_softc *);
237static void ti_free_tx_ring(struct ti_softc *);
238static int ti_init_tx_ring(struct ti_softc *);
239
240static int ti_64bitslot_war(struct ti_softc *);
241static int ti_chipinit(struct ti_softc *);
242static int ti_gibinit(struct ti_softc *);
243
244#ifdef TI_JUMBO_HDRSPLIT
245static __inline void ti_hdr_split (struct mbuf *top, int hdr_len,
246 int pkt_len, int idx);
247#endif /* TI_JUMBO_HDRSPLIT */
248
249static device_method_t ti_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, ti_probe),
252 DEVMETHOD(device_attach, ti_attach),
253 DEVMETHOD(device_detach, ti_detach),
254 DEVMETHOD(device_shutdown, ti_shutdown),
255 { 0, 0 }
256};
257
258static driver_t ti_driver = {
259 "ti",
260 ti_methods,
261 sizeof(struct ti_softc)
262};
263
264static devclass_t ti_devclass;
265
266DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
267MODULE_DEPEND(ti, pci, 1, 1, 1);
268MODULE_DEPEND(ti, ether, 1, 1, 1);
269
270/*
271 * Send an instruction or address to the EEPROM, check for ACK.
272 */
273static u_int32_t ti_eeprom_putbyte(sc, byte)
274 struct ti_softc *sc;
275 int byte;
276{
277 int i, ack = 0;
278
279 /*
280 * Make sure we're in TX mode.
281 */
282 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
283
284 /*
285 * Feed in each bit and stobe the clock.
286 */
287 for (i = 0x80; i; i >>= 1) {
288 if (byte & i) {
289 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
290 } else {
291 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
292 }
293 DELAY(1);
294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
295 DELAY(1);
296 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
297 }
298
299 /*
300 * Turn off TX mode.
301 */
302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
303
304 /*
305 * Check for ack.
306 */
307 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
308 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
310
311 return (ack);
312}
313
314/*
315 * Read a byte of data stored in the EEPROM at address 'addr.'
316 * We have to send two address bytes since the EEPROM can hold
317 * more than 256 bytes of data.
318 */
319static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
320 struct ti_softc *sc;
321 int addr;
322 u_int8_t *dest;
323{
324 int i;
325 u_int8_t byte = 0;
326
327 EEPROM_START;
328
329 /*
330 * Send write control code to EEPROM.
331 */
332 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
333 device_printf(sc->ti_dev,
334 "failed to send write command, status: %x\n",
335 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
336 return (1);
337 }
338
339 /*
340 * Send first byte of address of byte we want to read.
341 */
342 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
343 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
344 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
345 return (1);
346 }
347 /*
348 * Send second byte address of byte we want to read.
349 */
350 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
351 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
352 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
353 return (1);
354 }
355
356 EEPROM_STOP;
357 EEPROM_START;
358 /*
359 * Send read control code to EEPROM.
360 */
361 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
362 device_printf(sc->ti_dev,
363 "failed to send read command, status: %x\n",
364 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
365 return (1);
366 }
367
368 /*
369 * Start reading bits from EEPROM.
370 */
371 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
372 for (i = 0x80; i; i >>= 1) {
373 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
374 DELAY(1);
375 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
376 byte |= i;
377 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
378 DELAY(1);
379 }
380
381 EEPROM_STOP;
382
383 /*
384 * No ACK generated for read, so just return byte.
385 */
386
387 *dest = byte;
388
389 return (0);
390}
391
392/*
393 * Read a sequence of bytes from the EEPROM.
394 */
395static int
396ti_read_eeprom(sc, dest, off, cnt)
397 struct ti_softc *sc;
398 caddr_t dest;
399 int off;
400 int cnt;
401{
402 int err = 0, i;
403 u_int8_t byte = 0;
404
405 for (i = 0; i < cnt; i++) {
406 err = ti_eeprom_getbyte(sc, off + i, &byte);
407 if (err)
408 break;
409 *(dest + i) = byte;
410 }
411
412 return (err ? 1 : 0);
413}
414
415/*
416 * NIC memory read function.
417 * Can be used to copy data from NIC local memory.
418 */
419static void
420ti_mem_read(sc, addr, len, buf)
421 struct ti_softc *sc;
422 u_int32_t addr, len;
423 void *buf;
424{
425 int segptr, segsize, cnt;
426 char *ptr;
427
428 segptr = addr;
429 cnt = len;
430 ptr = buf;
431
432 while (cnt) {
433 if (cnt < TI_WINLEN)
434 segsize = cnt;
435 else
436 segsize = TI_WINLEN - (segptr % TI_WINLEN);
437 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
438 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
439 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr,
440 segsize / 4);
441 ptr += segsize;
442 segptr += segsize;
443 cnt -= segsize;
444 }
445}
446
447
448/*
449 * NIC memory write function.
450 * Can be used to copy data into NIC local memory.
451 */
452static void
453ti_mem_write(sc, addr, len, buf)
454 struct ti_softc *sc;
455 u_int32_t addr, len;
456 void *buf;
457{
458 int segptr, segsize, cnt;
459 char *ptr;
460
461 segptr = addr;
462 cnt = len;
463 ptr = buf;
464
465 while (cnt) {
466 if (cnt < TI_WINLEN)
467 segsize = cnt;
468 else
469 segsize = TI_WINLEN - (segptr % TI_WINLEN);
470 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
471 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
472 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr,
473 segsize / 4);
474 ptr += segsize;
475 segptr += segsize;
476 cnt -= segsize;
477 }
478}
479
480/*
481 * NIC memory read function.
482 * Can be used to clear a section of NIC local memory.
483 */
484static void
485ti_mem_zero(sc, addr, len)
486 struct ti_softc *sc;
487 u_int32_t addr, len;
488{
489 int segptr, segsize, cnt;
490
491 segptr = addr;
492 cnt = len;
493
494 while (cnt) {
495 if (cnt < TI_WINLEN)
496 segsize = cnt;
497 else
498 segsize = TI_WINLEN - (segptr % TI_WINLEN);
499 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
500 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
501 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
502 segptr += segsize;
503 cnt -= segsize;
504 }
505}
506
507static int
508ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata)
509 struct ti_softc *sc;
510 u_int32_t tigon_addr, len;
511 caddr_t buf;
512 int useraddr, readdata;
513{
514 int segptr, segsize, cnt;
515 caddr_t ptr;
516 u_int32_t origwin;
517 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
518 int resid, segresid;
519 int first_pass;
520
521 TI_LOCK_ASSERT(sc);
522
523 /*
524 * At the moment, we don't handle non-aligned cases, we just bail.
525 * If this proves to be a problem, it will be fixed.
526 */
527 if ((readdata == 0)
528 && (tigon_addr & 0x3)) {
529 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
530 "word-aligned\n", __func__, tigon_addr);
531 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
532 "yet supported\n", __func__);
533 return (EINVAL);
534 }
535
536 segptr = tigon_addr & ~0x3;
537 segresid = tigon_addr - segptr;
538
539 /*
540 * This is the non-aligned amount left over that we'll need to
541 * copy.
542 */
543 resid = len & 0x3;
544
545 /* Add in the left over amount at the front of the buffer */
546 resid += segresid;
547
548 cnt = len & ~0x3;
549 /*
550 * If resid + segresid is >= 4, add multiples of 4 to the count and
551 * decrease the residual by that much.
552 */
553 cnt += resid & ~0x3;
554 resid -= resid & ~0x3;
555
556 ptr = buf;
557
558 first_pass = 1;
559
560 /*
561 * Save the old window base value.
562 */
563 origwin = CSR_READ_4(sc, TI_WINBASE);
564
565 while (cnt) {
566 bus_size_t ti_offset;
567
568 if (cnt < TI_WINLEN)
569 segsize = cnt;
570 else
571 segsize = TI_WINLEN - (segptr % TI_WINLEN);
572 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
573
574 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
575
576 if (readdata) {
577
578 bus_space_read_region_4(sc->ti_btag,
579 sc->ti_bhandle, ti_offset,
580 (u_int32_t *)tmparray,
581 segsize >> 2);
582 if (useraddr) {
583 /*
584 * Yeah, this is a little on the kludgy
585 * side, but at least this code is only
586 * used for debugging.
587 */
588 ti_bcopy_swap(tmparray, tmparray2, segsize,
589 TI_SWAP_NTOH);
590
591 TI_UNLOCK(sc);
592 if (first_pass) {
593 copyout(&tmparray2[segresid], ptr,
594 segsize - segresid);
595 first_pass = 0;
596 } else
597 copyout(tmparray2, ptr, segsize);
598 TI_LOCK(sc);
599 } else {
600 if (first_pass) {
601
602 ti_bcopy_swap(tmparray, tmparray2,
603 segsize, TI_SWAP_NTOH);
604 TI_UNLOCK(sc);
605 bcopy(&tmparray2[segresid], ptr,
606 segsize - segresid);
607 TI_LOCK(sc);
608 first_pass = 0;
609 } else
610 ti_bcopy_swap(tmparray, ptr, segsize,
611 TI_SWAP_NTOH);
612 }
613
614 } else {
615 if (useraddr) {
616 TI_UNLOCK(sc);
617 copyin(ptr, tmparray2, segsize);
618 TI_LOCK(sc);
619 ti_bcopy_swap(tmparray2, tmparray, segsize,
620 TI_SWAP_HTON);
621 } else
622 ti_bcopy_swap(ptr, tmparray, segsize,
623 TI_SWAP_HTON);
624
625 bus_space_write_region_4(sc->ti_btag,
626 sc->ti_bhandle, ti_offset,
627 (u_int32_t *)tmparray,
628 segsize >> 2);
629 }
630 segptr += segsize;
631 ptr += segsize;
632 cnt -= segsize;
633 }
634
635 /*
636 * Handle leftover, non-word-aligned bytes.
637 */
638 if (resid != 0) {
639 u_int32_t tmpval, tmpval2;
640 bus_size_t ti_offset;
641
642 /*
643 * Set the segment pointer.
644 */
645 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
646
647 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
648
649 /*
650 * First, grab whatever is in our source/destination.
651 * We'll obviously need this for reads, but also for
652 * writes, since we'll be doing read/modify/write.
653 */
654 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
655 ti_offset, &tmpval, 1);
656
657 /*
658 * Next, translate this from little-endian to big-endian
659 * (at least on i386 boxes).
660 */
661 tmpval2 = ntohl(tmpval);
662
663 if (readdata) {
664 /*
665 * If we're reading, just copy the leftover number
666 * of bytes from the host byte order buffer to
667 * the user's buffer.
668 */
669 if (useraddr) {
670 TI_UNLOCK(sc);
671 copyout(&tmpval2, ptr, resid);
672 TI_LOCK(sc);
673 } else
674 bcopy(&tmpval2, ptr, resid);
675 } else {
676 /*
677 * If we're writing, first copy the bytes to be
678 * written into the network byte order buffer,
679 * leaving the rest of the buffer with whatever was
680 * originally in there. Then, swap the bytes
681 * around into host order and write them out.
682 *
683 * XXX KDM the read side of this has been verified
684 * to work, but the write side of it has not been
685 * verified. So user beware.
686 */
687 if (useraddr) {
688 TI_UNLOCK(sc);
689 copyin(ptr, &tmpval2, resid);
690 TI_LOCK(sc);
691 } else
692 bcopy(ptr, &tmpval2, resid);
693
694 tmpval = htonl(tmpval2);
695
696 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
697 ti_offset, &tmpval, 1);
698 }
699 }
700
701 CSR_WRITE_4(sc, TI_WINBASE, origwin);
702
703 return (0);
704}
705
706static int
707ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu)
708 struct ti_softc *sc;
709 u_int32_t tigon_addr, len;
710 caddr_t buf;
711 int useraddr, readdata;
712 int cpu;
713{
714 u_int32_t segptr;
715 int cnt;
716 u_int32_t tmpval, tmpval2;
717 caddr_t ptr;
718
719 TI_LOCK_ASSERT(sc);
720
721 /*
722 * At the moment, we don't handle non-aligned cases, we just bail.
723 * If this proves to be a problem, it will be fixed.
724 */
725 if (tigon_addr & 0x3) {
726 device_printf(sc->ti_dev, "%s: tigon address %#x "
727 "isn't word-aligned\n", __func__, tigon_addr);
728 return (EINVAL);
729 }
730
731 if (len & 0x3) {
732 device_printf(sc->ti_dev, "%s: transfer length %d "
733 "isn't word-aligned\n", __func__, len);
734 return (EINVAL);
735 }
736
737 segptr = tigon_addr;
738 cnt = len;
739 ptr = buf;
740
741 while (cnt) {
742 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
743
744 if (readdata) {
745 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
746
747 tmpval = ntohl(tmpval2);
748
749 /*
750 * Note: I've used this debugging interface
751 * extensively with Alteon's 12.3.15 firmware,
752 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
753 *
754 * When you compile the firmware without
755 * optimization, which is necessary sometimes in
756 * order to properly step through it, you sometimes
757 * read out a bogus value of 0xc0017c instead of
758 * whatever was supposed to be in that scratchpad
759 * location. That value is on the stack somewhere,
760 * but I've never been able to figure out what was
761 * causing the problem.
762 *
763 * The address seems to pop up in random places,
764 * often not in the same place on two subsequent
765 * reads.
766 *
767 * In any case, the underlying data doesn't seem
768 * to be affected, just the value read out.
769 *
770 * KDM, 3/7/2000
771 */
772
773 if (tmpval2 == 0xc0017c)
774 device_printf(sc->ti_dev, "found 0xc0017c at "
775 "%#x (tmpval2)\n", segptr);
776
777 if (tmpval == 0xc0017c)
778 device_printf(sc->ti_dev, "found 0xc0017c at "
779 "%#x (tmpval)\n", segptr);
780
781 if (useraddr)
782 copyout(&tmpval, ptr, 4);
783 else
784 bcopy(&tmpval, ptr, 4);
785 } else {
786 if (useraddr)
787 copyin(ptr, &tmpval2, 4);
788 else
789 bcopy(ptr, &tmpval2, 4);
790
791 tmpval = htonl(tmpval2);
792
793 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
794 }
795
796 cnt -= 4;
797 segptr += 4;
798 ptr += 4;
799 }
800
801 return (0);
802}
803
804static int
805ti_bcopy_swap(src, dst, len, swap_type)
806 const void *src;
807 void *dst;
808 size_t len;
809 ti_swap_type swap_type;
810{
811 const u_int8_t *tmpsrc;
812 u_int8_t *tmpdst;
813 size_t tmplen;
814
815 if (len & 0x3) {
816 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
817 len);
818 return (-1);
819 }
820
821 tmpsrc = src;
822 tmpdst = dst;
823 tmplen = len;
824
825 while (tmplen) {
826 if (swap_type == TI_SWAP_NTOH)
827 *(u_int32_t *)tmpdst =
828 ntohl(*(const u_int32_t *)tmpsrc);
829 else
830 *(u_int32_t *)tmpdst =
831 htonl(*(const u_int32_t *)tmpsrc);
832
833 tmpsrc += 4;
834 tmpdst += 4;
835 tmplen -= 4;
836 }
837
838 return (0);
839}
840
841/*
842 * Load firmware image into the NIC. Check that the firmware revision
843 * is acceptable and see if we want the firmware for the Tigon 1 or
844 * Tigon 2.
845 */
846static void
847ti_loadfw(sc)
848 struct ti_softc *sc;
849{
850
851 TI_LOCK_ASSERT(sc);
852
853 switch (sc->ti_hwrev) {
854 case TI_HWREV_TIGON:
855 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
856 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
857 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
858 device_printf(sc->ti_dev, "firmware revision mismatch; "
859 "want %d.%d.%d, got %d.%d.%d\n",
860 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
861 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
862 tigonFwReleaseMinor, tigonFwReleaseFix);
863 return;
864 }
865 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
866 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
867 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
868 tigonFwRodata);
869 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
870 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
871 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
872 break;
873 case TI_HWREV_TIGON_II:
874 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
875 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
876 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
877 device_printf(sc->ti_dev, "firmware revision mismatch; "
878 "want %d.%d.%d, got %d.%d.%d\n",
879 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
880 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
881 tigon2FwReleaseMinor, tigon2FwReleaseFix);
882 return;
883 }
884 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
885 tigon2FwText);
886 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
887 tigon2FwData);
888 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
889 tigon2FwRodata);
890 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
891 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
892 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
893 break;
894 default:
895 device_printf(sc->ti_dev,
896 "can't load firmware: unknown hardware rev\n");
897 break;
898 }
899}
900
901/*
902 * Send the NIC a command via the command ring.
903 */
904static void
905ti_cmd(sc, cmd)
906 struct ti_softc *sc;
907 struct ti_cmd_desc *cmd;
908{
909 int index;
910
911 index = sc->ti_cmd_saved_prodidx;
912 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
913 TI_INC(index, TI_CMD_RING_CNT);
914 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
915 sc->ti_cmd_saved_prodidx = index;
916}
917
918/*
919 * Send the NIC an extended command. The 'len' parameter specifies the
920 * number of command slots to include after the initial command.
921 */
922static void
923ti_cmd_ext(sc, cmd, arg, len)
924 struct ti_softc *sc;
925 struct ti_cmd_desc *cmd;
926 caddr_t arg;
927 int len;
928{
929 int index;
930 int i;
931
932 index = sc->ti_cmd_saved_prodidx;
933 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
934 TI_INC(index, TI_CMD_RING_CNT);
935 for (i = 0; i < len; i++) {
936 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
937 *(u_int32_t *)(&arg[i * 4]));
938 TI_INC(index, TI_CMD_RING_CNT);
939 }
940 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
941 sc->ti_cmd_saved_prodidx = index;
942}
943
944/*
945 * Handle events that have triggered interrupts.
946 */
947static void
948ti_handle_events(sc)
949 struct ti_softc *sc;
950{
951 struct ti_event_desc *e;
952
953 if (sc->ti_rdata->ti_event_ring == NULL)
954 return;
955
956 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
957 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
958 switch (TI_EVENT_EVENT(e)) {
959 case TI_EV_LINKSTAT_CHANGED:
960 sc->ti_linkstat = TI_EVENT_CODE(e);
961 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP)
962 device_printf(sc->ti_dev, "10/100 link up\n");
963 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP)
964 device_printf(sc->ti_dev, "gigabit link up\n");
965 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
966 device_printf(sc->ti_dev, "link down\n");
967 break;
968 case TI_EV_ERROR:
969 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
970 device_printf(sc->ti_dev, "invalid command\n");
971 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
972 device_printf(sc->ti_dev, "unknown command\n");
973 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
974 device_printf(sc->ti_dev, "bad config data\n");
975 break;
976 case TI_EV_FIRMWARE_UP:
977 ti_init2(sc);
978 break;
979 case TI_EV_STATS_UPDATED:
980 ti_stats_update(sc);
981 break;
982 case TI_EV_RESET_JUMBO_RING:
983 case TI_EV_MCAST_UPDATED:
984 /* Who cares. */
985 break;
986 default:
987 device_printf(sc->ti_dev, "unknown event: %d\n",
988 TI_EVENT_EVENT(e));
989 break;
990 }
991 /* Advance the consumer index. */
992 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
993 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
994 }
995}
996
997static int
998ti_alloc_dmamaps(struct ti_softc *sc)
999{
1000 int i;
1001
1002 for (i = 0; i < TI_TX_RING_CNT; i++) {
1003 sc->ti_cdata.ti_txdesc[i].tx_m = NULL;
1004 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
1005 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0,
1006 &sc->ti_cdata.ti_txdesc[i].tx_dmamap))
1007 return (ENOBUFS);
1008 }
1009 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1010 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
1011 &sc->ti_cdata.ti_rx_std_maps[i]))
1012 return (ENOBUFS);
1013 }
1014
1015 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1016 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0,
1017 &sc->ti_cdata.ti_rx_jumbo_maps[i]))
1018 return (ENOBUFS);
1019 }
1020 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1021 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
1022 &sc->ti_cdata.ti_rx_mini_maps[i]))
1023 return (ENOBUFS);
1024 }
1025
1026 return (0);
1027}
1028
1029static void
1030ti_free_dmamaps(struct ti_softc *sc)
1031{
1032 int i;
1033
1034 if (sc->ti_mbuftx_dmat)
1035 for (i = 0; i < TI_TX_RING_CNT; i++)
1036 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1037 bus_dmamap_destroy(sc->ti_mbuftx_dmat,
1038 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1039 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
1040 }
1041
1042 if (sc->ti_mbufrx_dmat)
1043 for (i = 0; i < TI_STD_RX_RING_CNT; i++)
1044 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1045 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1046 sc->ti_cdata.ti_rx_std_maps[i]);
1047 sc->ti_cdata.ti_rx_std_maps[i] = 0;
1048 }
1049
1050 if (sc->ti_jumbo_dmat)
1051 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++)
1052 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1053 bus_dmamap_destroy(sc->ti_jumbo_dmat,
1054 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1055 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0;
1056 }
1057 if (sc->ti_mbufrx_dmat)
1058 for (i = 0; i < TI_MINI_RX_RING_CNT; i++)
1059 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1060 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1061 sc->ti_cdata.ti_rx_mini_maps[i]);
1062 sc->ti_cdata.ti_rx_mini_maps[i] = 0;
1063 }
1064}
1065
1066#ifdef TI_PRIVATE_JUMBOS
1067
1068/*
1069 * Memory management for the jumbo receive ring is a pain in the
1070 * butt. We need to allocate at least 9018 bytes of space per frame,
1071 * _and_ it has to be contiguous (unless you use the extended
1072 * jumbo descriptor format). Using malloc() all the time won't
1073 * work: malloc() allocates memory in powers of two, which means we
1074 * would end up wasting a considerable amount of space by allocating
1075 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
1076 * to do our own memory management.
1077 *
1078 * The driver needs to allocate a contiguous chunk of memory at boot
1079 * time. We then chop this up ourselves into 9K pieces and use them
1080 * as external mbuf storage.
1081 *
1082 * One issue here is how much memory to allocate. The jumbo ring has
1083 * 256 slots in it, but at 9K per slot than can consume over 2MB of
1084 * RAM. This is a bit much, especially considering we also need
1085 * RAM for the standard ring and mini ring (on the Tigon 2). To
1086 * save space, we only actually allocate enough memory for 64 slots
1087 * by default, which works out to between 500 and 600K. This can
1088 * be tuned by changing a #define in if_tireg.h.
1089 */
1090
1091static int
1092ti_alloc_jumbo_mem(sc)
1093 struct ti_softc *sc;
1094{
1095 caddr_t ptr;
1096 int i;
1097 struct ti_jpool_entry *entry;
1098
1099 /*
1100 * Grab a big chunk o' storage. Since we are chopping this pool up
1101 * into ~9k chunks, there doesn't appear to be a need to use page
1102 * alignment.
1103 */
1104 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1105 1, 0, /* algnmnt, boundary */
1106 BUS_SPACE_MAXADDR, /* lowaddr */
1107 BUS_SPACE_MAXADDR, /* highaddr */
1108 NULL, NULL, /* filter, filterarg */
1109 TI_JMEM, /* maxsize */
1110 1, /* nsegments */
1111 TI_JMEM, /* maxsegsize */
1112 0, /* flags */
1113 NULL, NULL, /* lockfunc, lockarg */
1114 &sc->ti_jumbo_dmat) != 0) {
1115 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1116 return (ENOBUFS);
1117 }
1118
1119 if (bus_dmamem_alloc(sc->ti_jumbo_dmat,
1120 (void**)&sc->ti_cdata.ti_jumbo_buf,
1121 BUS_DMA_NOWAIT, &sc->ti_jumbo_dmamap) != 0) {
1122 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n");
1123 return (ENOBUFS);
1124 }
1125
1126 SLIST_INIT(&sc->ti_jfree_listhead);
1127 SLIST_INIT(&sc->ti_jinuse_listhead);
1128
1129 /*
1130 * Now divide it up into 9K pieces and save the addresses
1131 * in an array.
1132 */
1133 ptr = sc->ti_cdata.ti_jumbo_buf;
1134 for (i = 0; i < TI_JSLOTS; i++) {
1135 sc->ti_cdata.ti_jslots[i] = ptr;
1136 ptr += TI_JLEN;
1137 entry = malloc(sizeof(struct ti_jpool_entry),
1138 M_DEVBUF, M_NOWAIT);
1139 if (entry == NULL) {
1140 device_printf(sc->ti_dev, "no memory for jumbo "
1141 "buffer queue!\n");
1142 return (ENOBUFS);
1143 }
1144 entry->slot = i;
1145 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1146 }
1147
1148 return (0);
1149}
1150
1151/*
1152 * Allocate a jumbo buffer.
1153 */
1154static void *ti_jalloc(sc)
1155 struct ti_softc *sc;
1156{
1157 struct ti_jpool_entry *entry;
1158
1159 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1160
1161 if (entry == NULL) {
1162 device_printf(sc->ti_dev, "no free jumbo buffers\n");
1163 return (NULL);
1164 }
1165
1166 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1167 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1168 return (sc->ti_cdata.ti_jslots[entry->slot]);
1169}
1170
1171/*
1172 * Release a jumbo buffer.
1173 */
1174static void
1175ti_jfree(buf, args)
1176 void *buf;
1177 void *args;
1178{
1179 struct ti_softc *sc;
1180 int i;
1181 struct ti_jpool_entry *entry;
1182
1183 /* Extract the softc struct pointer. */
1184 sc = (struct ti_softc *)args;
1185
1186 if (sc == NULL)
1187 panic("ti_jfree: didn't get softc pointer!");
1188
1189 /* calculate the slot this buffer belongs to */
1190 i = ((vm_offset_t)buf
1191 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1192
1193 if ((i < 0) || (i >= TI_JSLOTS))
1194 panic("ti_jfree: asked to free buffer that we don't manage!");
1195
1196 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1197 if (entry == NULL)
1198 panic("ti_jfree: buffer not in use!");
1199 entry->slot = i;
1200 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1201 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1202}
1203
1204#else
1205
1206static int
1207ti_alloc_jumbo_mem(sc)
1208 struct ti_softc *sc;
1209{
1210
1211 /*
1212 * The VM system will take care of providing aligned pages. Alignment
1213 * is set to 1 here so that busdma resources won't be wasted.
1214 */
1215 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1216 1, 0, /* algnmnt, boundary */
1217 BUS_SPACE_MAXADDR, /* lowaddr */
1218 BUS_SPACE_MAXADDR, /* highaddr */
1219 NULL, NULL, /* filter, filterarg */
1220 PAGE_SIZE * 4 /*XXX*/, /* maxsize */
1221 4, /* nsegments */
1222 PAGE_SIZE, /* maxsegsize */
1223 0, /* flags */
1224 NULL, NULL, /* lockfunc, lockarg */
1225 &sc->ti_jumbo_dmat) != 0) {
1226 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1227 return (ENOBUFS);
1228 }
1229
1230 return (0);
1231}
1232
1233#endif /* TI_PRIVATE_JUMBOS */
1234
1235/*
1236 * Intialize a standard receive ring descriptor.
1237 */
1238static int
1239ti_newbuf_std(sc, i, m)
1240 struct ti_softc *sc;
1241 int i;
1242 struct mbuf *m;
1243{
1244 bus_dmamap_t map;
1245 bus_dma_segment_t segs;
1246 struct mbuf *m_new = NULL;
1247 struct ti_rx_desc *r;
1248 int nsegs;
1249
1250 nsegs = 0;
1251 if (m == NULL) {
1252 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1253 if (m_new == NULL)
1254 return (ENOBUFS);
1255
1256 MCLGET(m_new, M_DONTWAIT);
1257 if (!(m_new->m_flags & M_EXT)) {
1258 m_freem(m_new);
1259 return (ENOBUFS);
1260 }
1261 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1262 } else {
1263 m_new = m;
1264 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1265 m_new->m_data = m_new->m_ext.ext_buf;
1266 }
1267
1268 m_adj(m_new, ETHER_ALIGN);
1269 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1270 r = &sc->ti_rdata->ti_rx_std_ring[i];
1271 map = sc->ti_cdata.ti_rx_std_maps[i];
1272 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1273 &nsegs, 0))
1274 return (ENOBUFS);
1275 if (nsegs != 1)
1276 return (ENOBUFS);
1277 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1278 r->ti_len = segs.ds_len;
1279 r->ti_type = TI_BDTYPE_RECV_BD;
1280 r->ti_flags = 0;
1281 if (sc->ti_ifp->if_hwassist)
1282 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1283 r->ti_idx = i;
1284
1285 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1286 return (0);
1287}
1288
1289/*
1290 * Intialize a mini receive ring descriptor. This only applies to
1291 * the Tigon 2.
1292 */
1293static int
1294ti_newbuf_mini(sc, i, m)
1295 struct ti_softc *sc;
1296 int i;
1297 struct mbuf *m;
1298{
1299 bus_dma_segment_t segs;
1300 bus_dmamap_t map;
1301 struct mbuf *m_new = NULL;
1302 struct ti_rx_desc *r;
1303 int nsegs;
1304
1305 nsegs = 0;
1306 if (m == NULL) {
1307 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1308 if (m_new == NULL) {
1309 return (ENOBUFS);
1310 }
1311 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1312 } else {
1313 m_new = m;
1314 m_new->m_data = m_new->m_pktdat;
1315 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1316 }
1317
1318 m_adj(m_new, ETHER_ALIGN);
1319 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1320 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1321 map = sc->ti_cdata.ti_rx_mini_maps[i];
1322 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1323 &nsegs, 0))
1324 return (ENOBUFS);
1325 if (nsegs != 1)
1326 return (ENOBUFS);
1327 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1328 r->ti_len = segs.ds_len;
1329 r->ti_type = TI_BDTYPE_RECV_BD;
1330 r->ti_flags = TI_BDFLAG_MINI_RING;
1331 if (sc->ti_ifp->if_hwassist)
1332 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1333 r->ti_idx = i;
1334
1335 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1336 return (0);
1337}
1338
1339#ifdef TI_PRIVATE_JUMBOS
1340
1341/*
1342 * Initialize a jumbo receive ring descriptor. This allocates
1343 * a jumbo buffer from the pool managed internally by the driver.
1344 */
1345static int
1346ti_newbuf_jumbo(sc, i, m)
1347 struct ti_softc *sc;
1348 int i;
1349 struct mbuf *m;
1350{
1351 bus_dmamap_t map;
1352 struct mbuf *m_new = NULL;
1353 struct ti_rx_desc *r;
1354 int nsegs;
1355 bus_dma_segment_t segs;
1356
1357 if (m == NULL) {
1358 caddr_t *buf = NULL;
1359
1360 /* Allocate the mbuf. */
1361 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1362 if (m_new == NULL) {
1363 return (ENOBUFS);
1364 }
1365
1366 /* Allocate the jumbo buffer */
1367 buf = ti_jalloc(sc);
1368 if (buf == NULL) {
1369 m_freem(m_new);
1370 device_printf(sc->ti_dev, "jumbo allocation failed "
1371 "-- packet dropped!\n");
1372 return (ENOBUFS);
1373 }
1374
1375 /* Attach the buffer to the mbuf. */
1376 m_new->m_data = (void *) buf;
1377 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1378 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
1379 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1380 } else {
1381 m_new = m;
1382 m_new->m_data = m_new->m_ext.ext_buf;
1383 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1384 }
1385
1386 m_adj(m_new, ETHER_ALIGN);
1387 /* Set up the descriptor. */
1388 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1389 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1390 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1391 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs,
1392 &nsegs, 0))
1393 return (ENOBUFS);
1394 if (nsegs != 1)
1395 return (ENOBUFS);
1396 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1397 r->ti_len = segs.ds_len;
1398 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1399 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1400 if (sc->ti_ifp->if_hwassist)
1401 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1402 r->ti_idx = i;
1403
1404 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1405 return (0);
1406}
1407
1408#else
1409
1410#if (PAGE_SIZE == 4096)
1411#define NPAYLOAD 2
1412#else
1413#define NPAYLOAD 1
1414#endif
1415
1416#define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1417#define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1418#define NFS_HDR_LEN (UDP_HDR_LEN)
1419static int HDR_LEN = TCP_HDR_LEN;
1420
1421
1422/*
1423 * Initialize a jumbo receive ring descriptor. This allocates
1424 * a jumbo buffer from the pool managed internally by the driver.
1425 */
1426static int
1427ti_newbuf_jumbo(sc, idx, m_old)
1428 struct ti_softc *sc;
1429 int idx;
1430 struct mbuf *m_old;
1431{
1432 bus_dmamap_t map;
1433 struct mbuf *cur, *m_new = NULL;
1434 struct mbuf *m[3] = {NULL, NULL, NULL};
1435 struct ti_rx_desc_ext *r;
1436 vm_page_t frame;
1437 static int color;
1438 /* 1 extra buf to make nobufs easy*/
1439 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1440 int i;
1441 bus_dma_segment_t segs[4];
1442 int nsegs;
1443
1444 if (m_old != NULL) {
1445 m_new = m_old;
1446 cur = m_old->m_next;
1447 for (i = 0; i <= NPAYLOAD; i++){
1448 m[i] = cur;
1449 cur = cur->m_next;
1450 }
1451 } else {
1452 /* Allocate the mbufs. */
1453 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1454 if (m_new == NULL) {
1455 device_printf(sc->ti_dev, "mbuf allocation failed "
1456 "-- packet dropped!\n");
1457 goto nobufs;
1458 }
1459 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1460 if (m[NPAYLOAD] == NULL) {
1461 device_printf(sc->ti_dev, "cluster mbuf allocation "
1462 "failed -- packet dropped!\n");
1463 goto nobufs;
1464 }
1465 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1466 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1467 device_printf(sc->ti_dev, "mbuf allocation failed "
1468 "-- packet dropped!\n");
1469 goto nobufs;
1470 }
1471 m[NPAYLOAD]->m_len = MCLBYTES;
1472
1473 for (i = 0; i < NPAYLOAD; i++){
1474 MGET(m[i], M_DONTWAIT, MT_DATA);
1475 if (m[i] == NULL) {
1476 device_printf(sc->ti_dev, "mbuf allocation "
1477 "failed -- packet dropped!\n");
1478 goto nobufs;
1479 }
1480 frame = vm_page_alloc(NULL, color++,
1481 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1482 VM_ALLOC_WIRED);
1483 if (frame == NULL) {
1484 device_printf(sc->ti_dev, "buffer allocation "
1485 "failed -- packet dropped!\n");
1486 printf(" index %d page %d\n", idx, i);
1487 goto nobufs;
1488 }
1489 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1490 if (sf[i] == NULL) {
1491 vm_page_lock_queues();
1492 vm_page_unwire(frame, 0);
1493 vm_page_free(frame);
1494 vm_page_unlock_queues();
1495 device_printf(sc->ti_dev, "buffer allocation "
1496 "failed -- packet dropped!\n");
1497 printf(" index %d page %d\n", idx, i);
1498 goto nobufs;
1499 }
1500 }
1501 for (i = 0; i < NPAYLOAD; i++){
1502 /* Attach the buffer to the mbuf. */
1503 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1504 m[i]->m_len = PAGE_SIZE;
1505 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1506 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1507 0, EXT_DISPOSABLE);
1508 m[i]->m_next = m[i+1];
1509 }
1510 /* link the buffers to the header */
1511 m_new->m_next = m[0];
1512 m_new->m_data += ETHER_ALIGN;
1513 if (sc->ti_hdrsplit)
1514 m_new->m_len = MHLEN - ETHER_ALIGN;
1515 else
1516 m_new->m_len = HDR_LEN;
1517 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1518 }
1519
1520 /* Set up the descriptor. */
1521 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1522 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1523 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1524 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs,
1525 &nsegs, 0))
1526 return (ENOBUFS);
1527 if ((nsegs < 1) || (nsegs > 4))
1528 return (ENOBUFS);
1529 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1530 r->ti_len0 = m_new->m_len;
1531
1532 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1533 r->ti_len1 = PAGE_SIZE;
1534
1535 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1536 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1537
1538 if (PAGE_SIZE == 4096) {
1539 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1540 r->ti_len3 = MCLBYTES;
1541 } else {
1542 r->ti_len3 = 0;
1543 }
1544 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1545
1546 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1547
1548 if (sc->ti_ifp->if_hwassist)
1549 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1550
1551 r->ti_idx = idx;
1552
1553 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1554 return (0);
1555
1556nobufs:
1557
1558 /*
1559 * Warning! :
1560 * This can only be called before the mbufs are strung together.
1561 * If the mbufs are strung together, m_freem() will free the chain,
1562 * so that the later mbufs will be freed multiple times.
1563 */
1564 if (m_new)
1565 m_freem(m_new);
1566
1567 for (i = 0; i < 3; i++) {
1568 if (m[i])
1569 m_freem(m[i]);
1570 if (sf[i])
1571 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1572 }
1573 return (ENOBUFS);
1574}
1575#endif
1576
1577
1578
1579/*
1580 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1581 * that's 1MB or memory, which is a lot. For now, we fill only the first
1582 * 256 ring entries and hope that our CPU is fast enough to keep up with
1583 * the NIC.
1584 */
1585static int
1586ti_init_rx_ring_std(sc)
1587 struct ti_softc *sc;
1588{
1589 int i;
1590 struct ti_cmd_desc cmd;
1591
1592 for (i = 0; i < TI_SSLOTS; i++) {
1593 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1594 return (ENOBUFS);
1595 };
1596
1597 TI_UPDATE_STDPROD(sc, i - 1);
1598 sc->ti_std = i - 1;
1599
1600 return (0);
1601}
1602
1603static void
1604ti_free_rx_ring_std(sc)
1605 struct ti_softc *sc;
1606{
1607 bus_dmamap_t map;
1608 int i;
1609
1610 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1611 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1612 map = sc->ti_cdata.ti_rx_std_maps[i];
1613 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1614 BUS_DMASYNC_POSTREAD);
1615 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1616 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1617 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1618 }
1619 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1620 sizeof(struct ti_rx_desc));
1621 }
1622}
1623
1624static int
1625ti_init_rx_ring_jumbo(sc)
1626 struct ti_softc *sc;
1627{
1628 int i;
1629 struct ti_cmd_desc cmd;
1630
1631 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1632 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1633 return (ENOBUFS);
1634 };
1635
1636 TI_UPDATE_JUMBOPROD(sc, i - 1);
1637 sc->ti_jumbo = i - 1;
1638
1639 return (0);
1640}
1641
1642static void
1643ti_free_rx_ring_jumbo(sc)
1644 struct ti_softc *sc;
1645{
1646 bus_dmamap_t map;
1647 int i;
1648
1649 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1650 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1651 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1652 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
1653 BUS_DMASYNC_POSTREAD);
1654 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
1655 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1656 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1657 }
1658 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1659 sizeof(struct ti_rx_desc));
1660 }
1661}
1662
1663static int
1664ti_init_rx_ring_mini(sc)
1665 struct ti_softc *sc;
1666{
1667 int i;
1668
1669 for (i = 0; i < TI_MSLOTS; i++) {
1670 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1671 return (ENOBUFS);
1672 };
1673
1674 TI_UPDATE_MINIPROD(sc, i - 1);
1675 sc->ti_mini = i - 1;
1676
1677 return (0);
1678}
1679
1680static void
1681ti_free_rx_ring_mini(sc)
1682 struct ti_softc *sc;
1683{
1684 bus_dmamap_t map;
1685 int i;
1686
1687 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1688 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1689 map = sc->ti_cdata.ti_rx_mini_maps[i];
1690 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1691 BUS_DMASYNC_POSTREAD);
1692 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1693 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1694 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1695 }
1696 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1697 sizeof(struct ti_rx_desc));
1698 }
1699}
1700
1701static void
1702ti_free_tx_ring(sc)
1703 struct ti_softc *sc;
1704{
1705 struct ti_txdesc *txd;
1706 int i;
1707
1708 if (sc->ti_rdata->ti_tx_ring == NULL)
1709 return;
1710
1711 for (i = 0; i < TI_TX_RING_CNT; i++) {
1712 txd = &sc->ti_cdata.ti_txdesc[i];
1713 if (txd->tx_m != NULL) {
1714 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
1715 BUS_DMASYNC_POSTWRITE);
1716 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
1717 m_freem(txd->tx_m);
1718 txd->tx_m = NULL;
1719 }
1720 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1721 sizeof(struct ti_tx_desc));
1722 }
1723}
1724
1725static int
1726ti_init_tx_ring(sc)
1727 struct ti_softc *sc;
1728{
1729 struct ti_txdesc *txd;
1730 int i;
1731
1732 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1733 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1734 for (i = 0; i < TI_TX_RING_CNT; i++) {
1735 txd = &sc->ti_cdata.ti_txdesc[i];
1736 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1737 }
1738 sc->ti_txcnt = 0;
1739 sc->ti_tx_saved_considx = 0;
1740 sc->ti_tx_saved_prodidx = 0;
1741 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1742 return (0);
1743}
1744
1745/*
1746 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1747 * but we have to support the old way too so that Tigon 1 cards will
1748 * work.
1749 */
1750static void
1751ti_add_mcast(sc, addr)
1752 struct ti_softc *sc;
1753 struct ether_addr *addr;
1754{
1755 struct ti_cmd_desc cmd;
1756 u_int16_t *m;
1757 u_int32_t ext[2] = {0, 0};
1758
1759 m = (u_int16_t *)&addr->octet[0];
1760
1761 switch (sc->ti_hwrev) {
1762 case TI_HWREV_TIGON:
1763 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1764 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1765 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1766 break;
1767 case TI_HWREV_TIGON_II:
1768 ext[0] = htons(m[0]);
1769 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1770 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1771 break;
1772 default:
1773 device_printf(sc->ti_dev, "unknown hwrev\n");
1774 break;
1775 }
1776}
1777
1778static void
1779ti_del_mcast(sc, addr)
1780 struct ti_softc *sc;
1781 struct ether_addr *addr;
1782{
1783 struct ti_cmd_desc cmd;
1784 u_int16_t *m;
1785 u_int32_t ext[2] = {0, 0};
1786
1787 m = (u_int16_t *)&addr->octet[0];
1788
1789 switch (sc->ti_hwrev) {
1790 case TI_HWREV_TIGON:
1791 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1792 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1793 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1794 break;
1795 case TI_HWREV_TIGON_II:
1796 ext[0] = htons(m[0]);
1797 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1798 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1799 break;
1800 default:
1801 device_printf(sc->ti_dev, "unknown hwrev\n");
1802 break;
1803 }
1804}
1805
1806/*
1807 * Configure the Tigon's multicast address filter.
1808 *
1809 * The actual multicast table management is a bit of a pain, thanks to
1810 * slight brain damage on the part of both Alteon and us. With our
1811 * multicast code, we are only alerted when the multicast address table
1812 * changes and at that point we only have the current list of addresses:
1813 * we only know the current state, not the previous state, so we don't
1814 * actually know what addresses were removed or added. The firmware has
1815 * state, but we can't get our grubby mits on it, and there is no 'delete
1816 * all multicast addresses' command. Hence, we have to maintain our own
1817 * state so we know what addresses have been programmed into the NIC at
1818 * any given time.
1819 */
1820static void
1821ti_setmulti(sc)
1822 struct ti_softc *sc;
1823{
1824 struct ifnet *ifp;
1825 struct ifmultiaddr *ifma;
1826 struct ti_cmd_desc cmd;
1827 struct ti_mc_entry *mc;
1828 u_int32_t intrs;
1829
1830 TI_LOCK_ASSERT(sc);
1831
1832 ifp = sc->ti_ifp;
1833
1834 if (ifp->if_flags & IFF_ALLMULTI) {
1835 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1836 return;
1837 } else {
1838 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1839 }
1840
1841 /* Disable interrupts. */
1842 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1843 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1844
1845 /* First, zot all the existing filters. */
1846 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1847 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1848 ti_del_mcast(sc, &mc->mc_addr);
1849 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1850 free(mc, M_DEVBUF);
1851 }
1852
1853 /* Now program new ones. */
1854 if_maddr_rlock(ifp);
1855 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1856 if (ifma->ifma_addr->sa_family != AF_LINK)
1857 continue;
1858 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1859 if (mc == NULL) {
1860 device_printf(sc->ti_dev,
1861 "no memory for mcast filter entry\n");
1862 continue;
1863 }
1864 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1865 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1866 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1867 ti_add_mcast(sc, &mc->mc_addr);
1868 }
1869 if_maddr_runlock(ifp);
1870
1871 /* Re-enable interrupts. */
1872 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1873}
1874
1875/*
1876 * Check to see if the BIOS has configured us for a 64 bit slot when
1877 * we aren't actually in one. If we detect this condition, we can work
1878 * around it on the Tigon 2 by setting a bit in the PCI state register,
1879 * but for the Tigon 1 we must give up and abort the interface attach.
1880 */
1881static int ti_64bitslot_war(sc)
1882 struct ti_softc *sc;
1883{
1884 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1885 CSR_WRITE_4(sc, 0x600, 0);
1886 CSR_WRITE_4(sc, 0x604, 0);
1887 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1888 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1889 if (sc->ti_hwrev == TI_HWREV_TIGON)
1890 return (EINVAL);
1891 else {
1892 TI_SETBIT(sc, TI_PCI_STATE,
1893 TI_PCISTATE_32BIT_BUS);
1894 return (0);
1895 }
1896 }
1897 }
1898
1899 return (0);
1900}
1901
1902/*
1903 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1904 * self-test results.
1905 */
1906static int
1907ti_chipinit(sc)
1908 struct ti_softc *sc;
1909{
1910 u_int32_t cacheline;
1911 u_int32_t pci_writemax = 0;
1912 u_int32_t hdrsplit;
1913
1914 /* Initialize link to down state. */
1915 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1916
1917 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM)
1918 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
1919 else
1920 sc->ti_ifp->if_hwassist = 0;
1921
1922 /* Set endianness before we access any non-PCI registers. */
1923#if 0 && BYTE_ORDER == BIG_ENDIAN
1924 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1925 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1926#else
1927 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1928 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1929#endif
1930
1931 /* Check the ROM failed bit to see if self-tests passed. */
1932 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1933 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
1934 return (ENODEV);
1935 }
1936
1937 /* Halt the CPU. */
1938 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1939
1940 /* Figure out the hardware revision. */
1941 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1942 case TI_REV_TIGON_I:
1943 sc->ti_hwrev = TI_HWREV_TIGON;
1944 break;
1945 case TI_REV_TIGON_II:
1946 sc->ti_hwrev = TI_HWREV_TIGON_II;
1947 break;
1948 default:
1949 device_printf(sc->ti_dev, "unsupported chip revision\n");
1950 return (ENODEV);
1951 }
1952
1953 /* Do special setup for Tigon 2. */
1954 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1955 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1956 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1957 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1958 }
1959
1960 /*
1961 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1962 * can't do header splitting.
1963 */
1964#ifdef TI_JUMBO_HDRSPLIT
1965 if (sc->ti_hwrev != TI_HWREV_TIGON)
1966 sc->ti_hdrsplit = 1;
1967 else
1968 device_printf(sc->ti_dev,
1969 "can't do header splitting on a Tigon I board\n");
1970#endif /* TI_JUMBO_HDRSPLIT */
1971
1972 /* Set up the PCI state register. */
1973 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1974 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1975 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1976 }
1977
1978 /* Clear the read/write max DMA parameters. */
1979 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1980 TI_PCISTATE_READ_MAXDMA));
1981
1982 /* Get cache line size. */
1983 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1984
1985 /*
1986 * If the system has set enabled the PCI memory write
1987 * and invalidate command in the command register, set
1988 * the write max parameter accordingly. This is necessary
1989 * to use MWI with the Tigon 2.
1990 */
1991 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1992 switch (cacheline) {
1993 case 1:
1994 case 4:
1995 case 8:
1996 case 16:
1997 case 32:
1998 case 64:
1999 break;
2000 default:
2001 /* Disable PCI memory write and invalidate. */
2002 if (bootverbose)
2003 device_printf(sc->ti_dev, "cache line size %d"
2004 " not supported; disabling PCI MWI\n",
2005 cacheline);
2006 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
2007 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
2008 break;
2009 }
2010 }
2011
2012 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
2013
2014 /* This sets the min dma param all the way up (0xff). */
2015 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
2016
2017 if (sc->ti_hdrsplit)
2018 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
2019 else
2020 hdrsplit = 0;
2021
2022 /* Configure DMA variables. */
2023#if BYTE_ORDER == BIG_ENDIAN
2024 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
2025 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
2026 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
2027 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
2028#else /* BYTE_ORDER */
2029 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
2030 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
2031 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
2032#endif /* BYTE_ORDER */
2033
2034 /*
2035 * Only allow 1 DMA channel to be active at a time.
2036 * I don't think this is a good idea, but without it
2037 * the firmware racks up lots of nicDmaReadRingFull
2038 * errors. This is not compatible with hardware checksums.
2039 */
2040 if (sc->ti_ifp->if_hwassist == 0)
2041 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
2042
2043 /* Recommended settings from Tigon manual. */
2044 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
2045 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
2046
2047 if (ti_64bitslot_war(sc)) {
2048 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
2049 "but we aren't");
2050 return (EINVAL);
2051 }
2052
2053 return (0);
2054}
2055
2056/*
2057 * Initialize the general information block and firmware, and
2058 * start the CPU(s) running.
2059 */
2060static int
2061ti_gibinit(sc)
2062 struct ti_softc *sc;
2063{
2064 struct ti_rcb *rcb;
2065 int i;
2066 struct ifnet *ifp;
2067 uint32_t rdphys;
2068
2069 TI_LOCK_ASSERT(sc);
2070
2071 ifp = sc->ti_ifp;
2072 rdphys = sc->ti_rdata_phys;
2073
2074 /* Disable interrupts for now. */
2075 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2076
2077 /*
2078 * Tell the chip where to find the general information block.
2079 * While this struct could go into >4GB memory, we allocate it in a
2080 * single slab with the other descriptors, and those don't seem to
2081 * support being located in a 64-bit region.
2082 */
2083 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
2084 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
2085
2086 /* Load the firmware into SRAM. */
2087 ti_loadfw(sc);
2088
2089 /* Set up the contents of the general info and ring control blocks. */
2090
2091 /* Set up the event ring and producer pointer. */
2092 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
2093
2094 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
2095 rcb->ti_flags = 0;
2096 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
2097 rdphys + TI_RD_OFF(ti_ev_prodidx_r);
2098 sc->ti_ev_prodidx.ti_idx = 0;
2099 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2100 sc->ti_ev_saved_considx = 0;
2101
2102 /* Set up the command ring and producer mailbox. */
2103 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
2104
2105 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
2106 rcb->ti_flags = 0;
2107 rcb->ti_max_len = 0;
2108 for (i = 0; i < TI_CMD_RING_CNT; i++) {
2109 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2110 }
2111 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2112 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2113 sc->ti_cmd_saved_prodidx = 0;
2114
2115 /*
2116 * Assign the address of the stats refresh buffer.
2117 * We re-use the current stats buffer for this to
2118 * conserve memory.
2119 */
2120 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
2121 rdphys + TI_RD_OFF(ti_info.ti_stats);
2122
2123 /* Set up the standard receive ring. */
2124 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
2125 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
2126 rcb->ti_max_len = TI_FRAMELEN;
2127 rcb->ti_flags = 0;
2128 if (sc->ti_ifp->if_hwassist)
2129 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2130 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2131 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2132
2133 /* Set up the jumbo receive ring. */
2134 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
2135 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
2136
2137#ifdef TI_PRIVATE_JUMBOS
2138 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
2139 rcb->ti_flags = 0;
2140#else
2141 rcb->ti_max_len = PAGE_SIZE;
2142 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2143#endif
2144 if (sc->ti_ifp->if_hwassist)
2145 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2146 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2147 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2148
2149 /*
2150 * Set up the mini ring. Only activated on the
2151 * Tigon 2 but the slot in the config block is
2152 * still there on the Tigon 1.
2153 */
2154 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
2155 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
2156 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2157 if (sc->ti_hwrev == TI_HWREV_TIGON)
2158 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2159 else
2160 rcb->ti_flags = 0;
2161 if (sc->ti_ifp->if_hwassist)
2162 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2163 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2164 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2165
2166 /*
2167 * Set up the receive return ring.
2168 */
2169 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
2170 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
2171 rcb->ti_flags = 0;
2172 rcb->ti_max_len = TI_RETURN_RING_CNT;
2173 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
2174 rdphys + TI_RD_OFF(ti_return_prodidx_r);
2175
2176 /*
2177 * Set up the tx ring. Note: for the Tigon 2, we have the option
2178 * of putting the transmit ring in the host's address space and
2179 * letting the chip DMA it instead of leaving the ring in the NIC's
2180 * memory and accessing it through the shared memory region. We
2181 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2182 * so we have to revert to the shared memory scheme if we detect
2183 * a Tigon 1 chip.
2184 */
2185 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2186 bzero((char *)sc->ti_rdata->ti_tx_ring,
2187 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
2188 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
2189 if (sc->ti_hwrev == TI_HWREV_TIGON)
2190 rcb->ti_flags = 0;
2191 else
2192 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2193 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2194 if (sc->ti_ifp->if_hwassist)
2195 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2196 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2197 rcb->ti_max_len = TI_TX_RING_CNT;
2198 if (sc->ti_hwrev == TI_HWREV_TIGON)
2199 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
2200 else
2201 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
2202 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
2203 rdphys + TI_RD_OFF(ti_tx_considx_r);
2204
2205 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2206 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2207
2208 /* Set up tuneables */
2209#if 0
2210 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2211 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2212 (sc->ti_rx_coal_ticks / 10));
2213 else
2214#endif
2215 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2216 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2217 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2218 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2219 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2220 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2221
2222 /* Turn interrupts on. */
2223 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2224 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2225
2226 /* Start CPU. */
2227 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2228
2229 return (0);
2230}
2231
2232static void
2233ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2234{
2235 struct ti_softc *sc;
2236
2237 sc = arg;
2238 if (error || nseg != 1)
2239 return;
2240
2241 /*
2242 * All of the Tigon data structures need to live at <4GB. This
2243 * cast is fine since busdma was told about this constraint.
2244 */
2245 sc->ti_rdata_phys = segs[0].ds_addr;
2246 return;
2247}
2248
2249/*
2250 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2251 * against our list and return its name if we find a match.
2252 */
2253static int
2254ti_probe(dev)
2255 device_t dev;
2256{
2257 struct ti_type *t;
2258
2259 t = ti_devs;
2260
2261 while (t->ti_name != NULL) {
2262 if ((pci_get_vendor(dev) == t->ti_vid) &&
2263 (pci_get_device(dev) == t->ti_did)) {
2264 device_set_desc(dev, t->ti_name);
2265 return (BUS_PROBE_DEFAULT);
2266 }
2267 t++;
2268 }
2269
2270 return (ENXIO);
2271}
2272
2273static int
2274ti_attach(dev)
2275 device_t dev;
2276{
2277 struct ifnet *ifp;
2278 struct ti_softc *sc;
2279 int error = 0, rid;
2280 u_char eaddr[6];
2281
2282 sc = device_get_softc(dev);
2283 sc->ti_unit = device_get_unit(dev);
2284 sc->ti_dev = dev;
2285
2286 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2287 MTX_DEF);
2288 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2289 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2290 if (ifp == NULL) {
2291 device_printf(dev, "can not if_alloc()\n");
2292 error = ENOSPC;
2293 goto fail;
2294 }
2295 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM |
2296 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2297 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2298
2299 /*
2300 * Map control/status registers.
2301 */
2302 pci_enable_busmaster(dev);
2303
2304 rid = TI_PCI_LOMEM;
2305 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2306 RF_ACTIVE);
2307
2308 if (sc->ti_res == NULL) {
2309 device_printf(dev, "couldn't map memory\n");
2310 error = ENXIO;
2311 goto fail;
2312 }
2313
2314 sc->ti_btag = rman_get_bustag(sc->ti_res);
2315 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2316
2317 /* Allocate interrupt */
2318 rid = 0;
2319
2320 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2321 RF_SHAREABLE | RF_ACTIVE);
2322
2323 if (sc->ti_irq == NULL) {
2324 device_printf(dev, "couldn't map interrupt\n");
2325 error = ENXIO;
2326 goto fail;
2327 }
2328
2329 if (ti_chipinit(sc)) {
2330 device_printf(dev, "chip initialization failed\n");
2331 error = ENXIO;
2332 goto fail;
2333 }
2334
2335 /* Zero out the NIC's on-board SRAM. */
2336 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2337
2338 /* Init again -- zeroing memory may have clobbered some registers. */
2339 if (ti_chipinit(sc)) {
2340 device_printf(dev, "chip initialization failed\n");
2341 error = ENXIO;
2342 goto fail;
2343 }
2344
2345 /*
2346 * Get station address from the EEPROM. Note: the manual states
2347 * that the MAC address is at offset 0x8c, however the data is
2348 * stored as two longwords (since that's how it's loaded into
2349 * the NIC). This means the MAC address is actually preceded
2350 * by two zero bytes. We need to skip over those.
2351 */
2352 if (ti_read_eeprom(sc, eaddr,
2353 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2354 device_printf(dev, "failed to read station address\n");
2355 error = ENXIO;
2356 goto fail;
2357 }
2358
2359 /* Allocate the general information block and ring buffers. */
2360 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
2361 1, 0, /* algnmnt, boundary */
2362 BUS_SPACE_MAXADDR, /* lowaddr */
2363 BUS_SPACE_MAXADDR, /* highaddr */
2364 NULL, NULL, /* filter, filterarg */
2365 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2366 0, /* nsegments */
2367 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2368 0, /* flags */
2369 NULL, NULL, /* lockfunc, lockarg */
2370 &sc->ti_parent_dmat) != 0) {
2371 device_printf(dev, "Failed to allocate parent dmat\n");
2372 error = ENOMEM;
2373 goto fail;
2374 }
2375
2376 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2377 PAGE_SIZE, 0, /* algnmnt, boundary */
2378 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2379 BUS_SPACE_MAXADDR, /* highaddr */
2380 NULL, NULL, /* filter, filterarg */
2381 sizeof(struct ti_ring_data), /* maxsize */
2382 1, /* nsegments */
2383 sizeof(struct ti_ring_data), /* maxsegsize */
2384 0, /* flags */
2385 NULL, NULL, /* lockfunc, lockarg */
2386 &sc->ti_rdata_dmat) != 0) {
2387 device_printf(dev, "Failed to allocate rdata dmat\n");
2388 error = ENOMEM;
2389 goto fail;
2390 }
2391
2392 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
2393 BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) {
2394 device_printf(dev, "Failed to allocate rdata memory\n");
2395 error = ENOMEM;
2396 goto fail;
2397 }
2398
2399 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2400 sc->ti_rdata, sizeof(struct ti_ring_data),
2401 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
2402 device_printf(dev, "Failed to load rdata segments\n");
2403 error = ENOMEM;
2404 goto fail;
2405 }
2406
2407 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2408
2409 /* Try to allocate memory for jumbo buffers. */
2410 if (ti_alloc_jumbo_mem(sc)) {
2411 device_printf(dev, "jumbo buffer allocation failed\n");
2412 error = ENXIO;
2413 goto fail;
2414 }
2415
2416 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2417 1, 0, /* algnmnt, boundary */
2418 BUS_SPACE_MAXADDR, /* lowaddr */
2419 BUS_SPACE_MAXADDR, /* highaddr */
2420 NULL, NULL, /* filter, filterarg */
2421 MCLBYTES * TI_MAXTXSEGS,/* maxsize */
2422 TI_MAXTXSEGS, /* nsegments */
2423 MCLBYTES, /* maxsegsize */
2424 0, /* flags */
2425 NULL, NULL, /* lockfunc, lockarg */
2426 &sc->ti_mbuftx_dmat) != 0) {
2427 device_printf(dev, "Failed to allocate rdata dmat\n");
2428 error = ENOMEM;
2429 goto fail;
2430 }
2431
2432 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2433 1, 0, /* algnmnt, boundary */
2434 BUS_SPACE_MAXADDR, /* lowaddr */
2435 BUS_SPACE_MAXADDR, /* highaddr */
2436 NULL, NULL, /* filter, filterarg */
2437 MCLBYTES, /* maxsize */
2438 1, /* nsegments */
2439 MCLBYTES, /* maxsegsize */
2440 0, /* flags */
2441 NULL, NULL, /* lockfunc, lockarg */
2442 &sc->ti_mbufrx_dmat) != 0) {
2443 device_printf(dev, "Failed to allocate rdata dmat\n");
2444 error = ENOMEM;
2445 goto fail;
2446 }
2447
2448 if (ti_alloc_dmamaps(sc)) {
2449 device_printf(dev, "dma map creation failed\n");
2450 error = ENXIO;
2451 goto fail;
2452 }
2453
2454 /*
2455 * We really need a better way to tell a 1000baseTX card
2456 * from a 1000baseSX one, since in theory there could be
2457 * OEMed 1000baseTX cards from lame vendors who aren't
2458 * clever enough to change the PCI ID. For the moment
2459 * though, the AceNIC is the only copper card available.
2460 */
2461 if (pci_get_vendor(dev) == ALT_VENDORID &&
2462 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2463 sc->ti_copper = 1;
2464 /* Ok, it's not the only copper card available. */
2465 if (pci_get_vendor(dev) == NG_VENDORID &&
2466 pci_get_device(dev) == NG_DEVICEID_GA620T)
2467 sc->ti_copper = 1;
2468
2469 /* Set default tuneable values. */
2470 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
2471#if 0
2472 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
2473#endif
2474 sc->ti_rx_coal_ticks = 170;
2475 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
2476 sc->ti_rx_max_coal_bds = 64;
2477#if 0
2478 sc->ti_tx_max_coal_bds = 128;
2479#endif
2480 sc->ti_tx_max_coal_bds = 32;
2481 sc->ti_tx_buf_ratio = 21;
2482
2483 /* Set up ifnet structure */
2484 ifp->if_softc = sc;
2485 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2486 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2487 ifp->if_ioctl = ti_ioctl;
2488 ifp->if_start = ti_start;
2489 ifp->if_watchdog = ti_watchdog;
2490 ifp->if_init = ti_init;
2491 ifp->if_baudrate = 1000000000;
2492 ifp->if_mtu = ETHERMTU;
2493 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
2494
2495 /* Set up ifmedia support. */
2496 if (sc->ti_copper) {
2497 /*
2498 * Copper cards allow manual 10/100 mode selection,
2499 * but not manual 1000baseTX mode selection. Why?
2500 * Becuase currently there's no way to specify the
2501 * master/slave setting through the firmware interface,
2502 * so Alteon decided to just bag it and handle it
2503 * via autonegotiation.
2504 */
2505 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2506 ifmedia_add(&sc->ifmedia,
2507 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2508 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2509 ifmedia_add(&sc->ifmedia,
2510 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2511 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2512 ifmedia_add(&sc->ifmedia,
2513 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2514 } else {
2515 /* Fiber cards don't support 10/100 modes. */
2516 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2517 ifmedia_add(&sc->ifmedia,
2518 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2519 }
2520 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2521 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2522
2523 /*
2524 * We're assuming here that card initialization is a sequential
2525 * thing. If it isn't, multiple cards probing at the same time
2526 * could stomp on the list of softcs here.
2527 */
2528
2529 /* Register the device */
2530 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
2531 0600, "ti%d", sc->ti_unit);
2532 sc->dev->si_drv1 = sc;
2533
2534 /*
2535 * Call MI attach routine.
2536 */
2537 ether_ifattach(ifp, eaddr);
2538
2539 /* Hook interrupt last to avoid having to lock softc */
2540 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2541 NULL, ti_intr, sc, &sc->ti_intrhand);
2542
2543 if (error) {
2544 device_printf(dev, "couldn't set up irq\n");
2545 goto fail;
2546 }
2547
2548fail:
2549 if (error)
2550 ti_detach(dev);
2551
2552 return (error);
2553}
2554
2555/*
2556 * Shutdown hardware and free up resources. This can be called any
2557 * time after the mutex has been initialized. It is called in both
2558 * the error case in attach and the normal detach case so it needs
2559 * to be careful about only freeing resources that have actually been
2560 * allocated.
2561 */
2562static int
2563ti_detach(dev)
2564 device_t dev;
2565{
2566 struct ti_softc *sc;
2567 struct ifnet *ifp;
2568 int attached;
2569
2570 sc = device_get_softc(dev);
2571 if (sc->dev)
2572 destroy_dev(sc->dev);
2573 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2574 attached = device_is_attached(dev);
2575 TI_LOCK(sc);
2576 ifp = sc->ti_ifp;
2577 if (attached)
2578 ti_stop(sc);
2579 TI_UNLOCK(sc);
2580 if (attached)
2581 ether_ifdetach(ifp);
2582
2583 /* These should only be active if attach succeeded */
2584 if (attached)
2585 bus_generic_detach(dev);
2586 ti_free_dmamaps(sc);
2587 ifmedia_removeall(&sc->ifmedia);
2588
2589#ifdef TI_PRIVATE_JUMBOS
2590 if (sc->ti_cdata.ti_jumbo_buf)
2591 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf,
2592 sc->ti_jumbo_dmamap);
2593#endif
2594 if (sc->ti_jumbo_dmat)
2595 bus_dma_tag_destroy(sc->ti_jumbo_dmat);
2596 if (sc->ti_mbuftx_dmat)
2597 bus_dma_tag_destroy(sc->ti_mbuftx_dmat);
2598 if (sc->ti_mbufrx_dmat)
2599 bus_dma_tag_destroy(sc->ti_mbufrx_dmat);
2600 if (sc->ti_rdata)
2601 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
2602 sc->ti_rdata_dmamap);
2603 if (sc->ti_rdata_dmat)
2604 bus_dma_tag_destroy(sc->ti_rdata_dmat);
2605 if (sc->ti_parent_dmat)
2606 bus_dma_tag_destroy(sc->ti_parent_dmat);
2607 if (sc->ti_intrhand)
2608 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2609 if (sc->ti_irq)
2610 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2611 if (sc->ti_res) {
2612 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2613 sc->ti_res);
2614 }
2615 if (ifp)
2616 if_free(ifp);
2617
2618 mtx_destroy(&sc->ti_mtx);
2619
2620 return (0);
2621}
2622
2623#ifdef TI_JUMBO_HDRSPLIT
2624/*
2625 * If hdr_len is 0, that means that header splitting wasn't done on
2626 * this packet for some reason. The two most likely reasons are that
2627 * the protocol isn't a supported protocol for splitting, or this
2628 * packet had a fragment offset that wasn't 0.
2629 *
2630 * The header length, if it is non-zero, will always be the length of
2631 * the headers on the packet, but that length could be longer than the
2632 * first mbuf. So we take the minimum of the two as the actual
2633 * length.
2634 */
2635static __inline void
2636ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2637{
2638 int i = 0;
2639 int lengths[4] = {0, 0, 0, 0};
2640 struct mbuf *m, *mp;
2641
2642 if (hdr_len != 0)
2643 top->m_len = min(hdr_len, top->m_len);
2644 pkt_len -= top->m_len;
2645 lengths[i++] = top->m_len;
2646
2647 mp = top;
2648 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2649 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2650 pkt_len -= m->m_len;
2651 lengths[i++] = m->m_len;
2652 mp = m;
2653 }
2654
2655#if 0
2656 if (hdr_len != 0)
2657 printf("got split packet: ");
2658 else
2659 printf("got non-split packet: ");
2660
2661 printf("%d,%d,%d,%d = %d\n", lengths[0],
2662 lengths[1], lengths[2], lengths[3],
2663 lengths[0] + lengths[1] + lengths[2] +
2664 lengths[3]);
2665#endif
2666
2667 if (pkt_len)
2668 panic("header splitting didn't");
2669
2670 if (m) {
2671 m_freem(m);
2672 mp->m_next = NULL;
2673
2674 }
2675 if (mp->m_next != NULL)
2676 panic("ti_hdr_split: last mbuf in chain should be null");
2677}
2678#endif /* TI_JUMBO_HDRSPLIT */
2679
2680/*
2681 * Frame reception handling. This is called if there's a frame
2682 * on the receive return list.
2683 *
2684 * Note: we have to be able to handle three possibilities here:
2685 * 1) the frame is from the mini receive ring (can only happen)
2686 * on Tigon 2 boards)
2687 * 2) the frame is from the jumbo recieve ring
2688 * 3) the frame is from the standard receive ring
2689 */
2690
2691static void
2692ti_rxeof(sc)
2693 struct ti_softc *sc;
2694{
2695 bus_dmamap_t map;
2696 struct ifnet *ifp;
2697 struct ti_cmd_desc cmd;
2698
2699 TI_LOCK_ASSERT(sc);
2700
2701 ifp = sc->ti_ifp;
2702
2703 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2704 struct ti_rx_desc *cur_rx;
2705 u_int32_t rxidx;
2706 struct mbuf *m = NULL;
2707 u_int16_t vlan_tag = 0;
2708 int have_tag = 0;
2709
2710 cur_rx =
2711 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2712 rxidx = cur_rx->ti_idx;
2713 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2714
2715 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2716 have_tag = 1;
2717 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
2718 }
2719
2720 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2721
2722 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2723 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2724 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2725 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2726 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
2727 BUS_DMASYNC_POSTREAD);
2728 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
2729 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2730 ifp->if_ierrors++;
2731 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2732 continue;
2733 }
2734 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2735 ifp->if_ierrors++;
2736 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2737 continue;
2738 }
2739#ifdef TI_PRIVATE_JUMBOS
2740 m->m_len = cur_rx->ti_len;
2741#else /* TI_PRIVATE_JUMBOS */
2742#ifdef TI_JUMBO_HDRSPLIT
2743 if (sc->ti_hdrsplit)
2744 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2745 cur_rx->ti_len, rxidx);
2746 else
2747#endif /* TI_JUMBO_HDRSPLIT */
2748 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2749#endif /* TI_PRIVATE_JUMBOS */
2750 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2751 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2752 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2753 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2754 map = sc->ti_cdata.ti_rx_mini_maps[rxidx];
2755 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2756 BUS_DMASYNC_POSTREAD);
2757 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2758 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2759 ifp->if_ierrors++;
2760 ti_newbuf_mini(sc, sc->ti_mini, m);
2761 continue;
2762 }
2763 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2764 ifp->if_ierrors++;
2765 ti_newbuf_mini(sc, sc->ti_mini, m);
2766 continue;
2767 }
2768 m->m_len = cur_rx->ti_len;
2769 } else {
2770 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2771 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2772 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2773 map = sc->ti_cdata.ti_rx_std_maps[rxidx];
2774 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2775 BUS_DMASYNC_POSTREAD);
2776 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2777 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2778 ifp->if_ierrors++;
2779 ti_newbuf_std(sc, sc->ti_std, m);
2780 continue;
2781 }
2782 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2783 ifp->if_ierrors++;
2784 ti_newbuf_std(sc, sc->ti_std, m);
2785 continue;
2786 }
2787 m->m_len = cur_rx->ti_len;
2788 }
2789
2790 m->m_pkthdr.len = cur_rx->ti_len;
2791 ifp->if_ipackets++;
2792 m->m_pkthdr.rcvif = ifp;
2793
2794 if (ifp->if_hwassist) {
2795 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
2796 CSUM_DATA_VALID;
2797 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2798 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2799 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
2800 }
2801
2802 /*
2803 * If we received a packet with a vlan tag,
2804 * tag it before passing the packet upward.
2805 */
2806 if (have_tag) {
2807 m->m_pkthdr.ether_vtag = vlan_tag;
2808 m->m_flags |= M_VLANTAG;
2809 }
2810 TI_UNLOCK(sc);
2811 (*ifp->if_input)(ifp, m);
2812 TI_LOCK(sc);
2813 }
2814
2815 /* Only necessary on the Tigon 1. */
2816 if (sc->ti_hwrev == TI_HWREV_TIGON)
2817 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2818 sc->ti_rx_saved_considx);
2819
2820 TI_UPDATE_STDPROD(sc, sc->ti_std);
2821 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2822 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2823}
2824
2825static void
2826ti_txeof(sc)
2827 struct ti_softc *sc;
2828{
2829 struct ti_txdesc *txd;
2830 struct ti_tx_desc txdesc;
2831 struct ti_tx_desc *cur_tx = NULL;
2832 struct ifnet *ifp;
2833 int idx;
2834
2835 ifp = sc->ti_ifp;
2836
2837 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2838 if (txd == NULL)
2839 return;
2840 /*
2841 * Go through our tx ring and free mbufs for those
2842 * frames that have been sent.
2843 */
2844 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2845 TI_INC(idx, TI_TX_RING_CNT)) {
2846 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2847 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2848 sizeof(txdesc), &txdesc);
2849 cur_tx = &txdesc;
2850 } else
2851 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2852 sc->ti_txcnt--;
2853 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2854 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2855 continue;
2856 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2857 BUS_DMASYNC_POSTWRITE);
2858 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2859
2860 ifp->if_opackets++;
2861 m_freem(txd->tx_m);
2862 txd->tx_m = NULL;
2863 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2864 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2865 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2866 }
2867 sc->ti_tx_saved_considx = idx;
2868
2869 ifp->if_timer = sc->ti_txcnt > 0 ? 5 : 0;
2870}
2871
2872static void
2873ti_intr(xsc)
2874 void *xsc;
2875{
2876 struct ti_softc *sc;
2877 struct ifnet *ifp;
2878
2879 sc = xsc;
2880 TI_LOCK(sc);
2881 ifp = sc->ti_ifp;
2882
2883/*#ifdef notdef*/
2884 /* Avoid this for now -- checking this register is expensive. */
2885 /* Make sure this is really our interrupt. */
2886 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2887 TI_UNLOCK(sc);
2888 return;
2889 }
2890/*#endif*/
2891
2892 /* Ack interrupt and stop others from occuring. */
2893 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2894
2895 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2896 /* Check RX return ring producer/consumer */
2897 ti_rxeof(sc);
2898
2899 /* Check TX ring producer/consumer */
2900 ti_txeof(sc);
2901 }
2902
2903 ti_handle_events(sc);
2904
2905 /* Re-enable interrupts. */
2906 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2907
2908 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2909 ifp->if_snd.ifq_head != NULL)
2910 ti_start_locked(ifp);
2911
2912 TI_UNLOCK(sc);
2913}
2914
2915static void
2916ti_stats_update(sc)
2917 struct ti_softc *sc;
2918{
2919 struct ifnet *ifp;
2920
2921 ifp = sc->ti_ifp;
2922
2923 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2924 BUS_DMASYNC_POSTREAD);
2925
2926 ifp->if_collisions +=
2927 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2928 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2929 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2930 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2931 ifp->if_collisions;
2932
2933 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2934 BUS_DMASYNC_PREREAD);
2935}
2936
2937/*
2938 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2939 * pointers to descriptors.
2940 */
2941static int
2942ti_encap(sc, m_head)
2943 struct ti_softc *sc;
2944 struct mbuf **m_head;
2945{
2946 struct ti_txdesc *txd;
2947 struct ti_tx_desc *f;
2948 struct ti_tx_desc txdesc;
2949 struct mbuf *m;
2950 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
2951 u_int16_t csum_flags;
2952 int error, frag, i, nseg;
2953
2954 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
2955 return (ENOBUFS);
2956
2957 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2958 *m_head, txsegs, &nseg, 0);
2959 if (error == EFBIG) {
2960 m = m_defrag(*m_head, M_DONTWAIT);
2961 if (m == NULL) {
2962 m_freem(*m_head);
2963 *m_head = NULL;
2964 return (ENOMEM);
2965 }
2966 *m_head = m;
2967 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat,
2968 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2969 if (error) {
2970 m_freem(*m_head);
2971 *m_head = NULL;
2972 return (error);
2973 }
2974 } else if (error != 0)
2975 return (error);
2976 if (nseg == 0) {
2977 m_freem(*m_head);
2978 *m_head = NULL;
2979 return (EIO);
2980 }
2981
2982 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
2983 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2984 return (ENOBUFS);
2985 }
2986
2987 m = *m_head;
2988 csum_flags = 0;
2989 if (m->m_pkthdr.csum_flags) {
2990 if (m->m_pkthdr.csum_flags & CSUM_IP)
2991 csum_flags |= TI_BDFLAG_IP_CKSUM;
2992 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2993 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2994 if (m->m_flags & M_LASTFRAG)
2995 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2996 else if (m->m_flags & M_FRAG)
2997 csum_flags |= TI_BDFLAG_IP_FRAG;
2998 }
2999
3000 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
3001 BUS_DMASYNC_PREWRITE);
3002 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
3003 BUS_DMASYNC_PREWRITE);
3004
3005 frag = sc->ti_tx_saved_prodidx;
3006 for (i = 0; i < nseg; i++) {
3007 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3008 bzero(&txdesc, sizeof(txdesc));
3009 f = &txdesc;
3010 } else
3011 f = &sc->ti_rdata->ti_tx_ring[frag];
3012 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
3013 f->ti_len = txsegs[i].ds_len;
3014 f->ti_flags = csum_flags;
3015 if (m->m_flags & M_VLANTAG) {
3016 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
3017 f->ti_vlan_tag = m->m_pkthdr.ether_vtag & 0xfff;
3018 } else {
3019 f->ti_vlan_tag = 0;
3020 }
3021
3022 if (sc->ti_hwrev == TI_HWREV_TIGON)
3023 ti_mem_write(sc, TI_TX_RING_BASE + frag *
3024 sizeof(txdesc), sizeof(txdesc), &txdesc);
3025 TI_INC(frag, TI_TX_RING_CNT);
3026 }
3027
3028 sc->ti_tx_saved_prodidx = frag;
3029 /* set TI_BDFLAG_END on the last descriptor */
3030 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
3031 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3032 txdesc.ti_flags |= TI_BDFLAG_END;
3033 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
3034 sizeof(txdesc), &txdesc);
3035 } else
3036 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
3037
3038 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
3039 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
3040 txd->tx_m = m;
3041 sc->ti_txcnt += nseg;
3042
3043 return (0);
3044}
3045
3046static void
3047ti_start(ifp)
3048 struct ifnet *ifp;
3049{
3050 struct ti_softc *sc;
3051
3052 sc = ifp->if_softc;
3053 TI_LOCK(sc);
3054 ti_start_locked(ifp);
3055 TI_UNLOCK(sc);
3056}
3057
3058/*
3059 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3060 * to the mbuf data regions directly in the transmit descriptors.
3061 */
3062static void
3063ti_start_locked(ifp)
3064 struct ifnet *ifp;
3065{
3066 struct ti_softc *sc;
3067 struct mbuf *m_head = NULL;
3068 int enq = 0;
3069
3070 sc = ifp->if_softc;
3071
3072 for (; ifp->if_snd.ifq_head != NULL &&
3073 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3074 IF_DEQUEUE(&ifp->if_snd, m_head);
3075 if (m_head == NULL)
3076 break;
3077
3078 /*
3079 * XXX
3080 * safety overkill. If this is a fragmented packet chain
3081 * with delayed TCP/UDP checksums, then only encapsulate
3082 * it if we have enough descriptors to handle the entire
3083 * chain at once.
3084 * (paranoia -- may not actually be needed)
3085 */
3086 if (m_head->m_flags & M_FIRSTFRAG &&
3087 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3088 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
3089 m_head->m_pkthdr.csum_data + 16) {
3090 IF_PREPEND(&ifp->if_snd, m_head);
3091 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3092 break;
3093 }
3094 }
3095
3096 /*
3097 * Pack the data into the transmit ring. If we
3098 * don't have room, set the OACTIVE flag and wait
3099 * for the NIC to drain the ring.
3100 */
3101 if (ti_encap(sc, &m_head)) {
3102 if (m_head == NULL)
3103 break;
3104 IF_PREPEND(&ifp->if_snd, m_head);
3105 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3106 break;
3107 }
3108
3109 enq++;
3110 /*
3111 * If there's a BPF listener, bounce a copy of this frame
3112 * to him.
3113 */
3114 ETHER_BPF_MTAP(ifp, m_head);
3115 }
3116
3117 if (enq > 0) {
3118 /* Transmit */
3119 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3120
3121 /*
3122 * Set a timeout in case the chip goes out to lunch.
3123 */
3124 ifp->if_timer = 5;
3125 }
3126}
3127
3128static void
3129ti_init(xsc)
3130 void *xsc;
3131{
3132 struct ti_softc *sc;
3133
3134 sc = xsc;
3135 TI_LOCK(sc);
3136 ti_init_locked(sc);
3137 TI_UNLOCK(sc);
3138}
3139
3140static void
3141ti_init_locked(xsc)
3142 void *xsc;
3143{
3144 struct ti_softc *sc = xsc;
3145
3146 /* Cancel pending I/O and flush buffers. */
3147 ti_stop(sc);
3148
3149 /* Init the gen info block, ring control blocks and firmware. */
3150 if (ti_gibinit(sc)) {
3151 device_printf(sc->ti_dev, "initialization failure\n");
3152 return;
3153 }
3154}
3155
3156static void ti_init2(sc)
3157 struct ti_softc *sc;
3158{
3159 struct ti_cmd_desc cmd;
3160 struct ifnet *ifp;
3161 u_int8_t *ea;
3162 struct ifmedia *ifm;
3163 int tmp;
3164
3165 TI_LOCK_ASSERT(sc);
3166
3167 ifp = sc->ti_ifp;
3168
3169 /* Specify MTU and interface index. */
3170 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
3171 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3172 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3173 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3174
3175 /* Load our MAC address. */
3176 ea = IF_LLADDR(sc->ti_ifp);
3177 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3178 CSR_WRITE_4(sc, TI_GCR_PAR1,
3179 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3180 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3181
3182 /* Enable or disable promiscuous mode as needed. */
3183 if (ifp->if_flags & IFF_PROMISC) {
3184 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3185 } else {
3186 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3187 }
3188
3189 /* Program multicast filter. */
3190 ti_setmulti(sc);
3191
3192 /*
3193 * If this is a Tigon 1, we should tell the
3194 * firmware to use software packet filtering.
3195 */
3196 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3197 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3198 }
3199
3200 /* Init RX ring. */
3201 ti_init_rx_ring_std(sc);
3202
3203 /* Init jumbo RX ring. */
3204 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3205 ti_init_rx_ring_jumbo(sc);
3206
3207 /*
3208 * If this is a Tigon 2, we can also configure the
3209 * mini ring.
3210 */
3211 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
3212 ti_init_rx_ring_mini(sc);
3213
3214 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3215 sc->ti_rx_saved_considx = 0;
3216
3217 /* Init TX ring. */
3218 ti_init_tx_ring(sc);
3219
3220 /* Tell firmware we're alive. */
3221 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3222
3223 /* Enable host interrupts. */
3224 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3225
3226 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3227 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3228
3229 /*
3230 * Make sure to set media properly. We have to do this
3231 * here since we have to issue commands in order to set
3232 * the link negotiation and we can't issue commands until
3233 * the firmware is running.
3234 */
3235 ifm = &sc->ifmedia;
3236 tmp = ifm->ifm_media;
3237 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3238 ti_ifmedia_upd(ifp);
3239 ifm->ifm_media = tmp;
3240}
3241
3242/*
3243 * Set media options.
3244 */
3245static int
3246ti_ifmedia_upd(ifp)
3247 struct ifnet *ifp;
3248{
3249 struct ti_softc *sc;
3250 struct ifmedia *ifm;
3251 struct ti_cmd_desc cmd;
3252 u_int32_t flowctl;
3253
3254 sc = ifp->if_softc;
3255 ifm = &sc->ifmedia;
3256
3257 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3258 return (EINVAL);
3259
3260 flowctl = 0;
3261
3262 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3263 case IFM_AUTO:
3264 /*
3265 * Transmit flow control doesn't work on the Tigon 1.
3266 */
3267 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3268
3269 /*
3270 * Transmit flow control can also cause problems on the
3271 * Tigon 2, apparantly with both the copper and fiber
3272 * boards. The symptom is that the interface will just
3273 * hang. This was reproduced with Alteon 180 switches.
3274 */
3275#if 0
3276 if (sc->ti_hwrev != TI_HWREV_TIGON)
3277 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3278#endif
3279
3280 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3281 TI_GLNK_FULL_DUPLEX| flowctl |
3282 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3283
3284 flowctl = TI_LNK_RX_FLOWCTL_Y;
3285#if 0
3286 if (sc->ti_hwrev != TI_HWREV_TIGON)
3287 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3288#endif
3289
3290 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3291 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3292 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3293 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3294 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3295 break;
3296 case IFM_1000_SX:
3297 case IFM_1000_T:
3298 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3299#if 0
3300 if (sc->ti_hwrev != TI_HWREV_TIGON)
3301 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3302#endif
3303
3304 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3305 flowctl |TI_GLNK_ENB);
3306 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3307 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3308 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3309 }
3310 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3311 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3312 break;
3313 case IFM_100_FX:
3314 case IFM_10_FL:
3315 case IFM_100_TX:
3316 case IFM_10_T:
3317 flowctl = TI_LNK_RX_FLOWCTL_Y;
3318#if 0
3319 if (sc->ti_hwrev != TI_HWREV_TIGON)
3320 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3321#endif
3322
3323 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3324 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3325 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3326 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3327 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3328 } else {
3329 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3330 }
3331 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3332 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3333 } else {
3334 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3335 }
3336 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3337 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3338 break;
3339 }
3340
3341 return (0);
3342}
3343
3344/*
3345 * Report current media status.
3346 */
3347static void
3348ti_ifmedia_sts(ifp, ifmr)
3349 struct ifnet *ifp;
3350 struct ifmediareq *ifmr;
3351{
3352 struct ti_softc *sc;
3353 u_int32_t media = 0;
3354
3355 sc = ifp->if_softc;
3356
3357 ifmr->ifm_status = IFM_AVALID;
3358 ifmr->ifm_active = IFM_ETHER;
3359
3360 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
3361 return;
3362
3363 ifmr->ifm_status |= IFM_ACTIVE;
3364
3365 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3366 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3367 if (sc->ti_copper)
3368 ifmr->ifm_active |= IFM_1000_T;
3369 else
3370 ifmr->ifm_active |= IFM_1000_SX;
3371 if (media & TI_GLNK_FULL_DUPLEX)
3372 ifmr->ifm_active |= IFM_FDX;
3373 else
3374 ifmr->ifm_active |= IFM_HDX;
3375 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3376 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3377 if (sc->ti_copper) {
3378 if (media & TI_LNK_100MB)
3379 ifmr->ifm_active |= IFM_100_TX;
3380 if (media & TI_LNK_10MB)
3381 ifmr->ifm_active |= IFM_10_T;
3382 } else {
3383 if (media & TI_LNK_100MB)
3384 ifmr->ifm_active |= IFM_100_FX;
3385 if (media & TI_LNK_10MB)
3386 ifmr->ifm_active |= IFM_10_FL;
3387 }
3388 if (media & TI_LNK_FULL_DUPLEX)
3389 ifmr->ifm_active |= IFM_FDX;
3390 if (media & TI_LNK_HALF_DUPLEX)
3391 ifmr->ifm_active |= IFM_HDX;
3392 }
3393}
3394
3395static int
3396ti_ioctl(ifp, command, data)
3397 struct ifnet *ifp;
3398 u_long command;
3399 caddr_t data;
3400{
3401 struct ti_softc *sc = ifp->if_softc;
3402 struct ifreq *ifr = (struct ifreq *) data;
3403 int mask, error = 0;
3404 struct ti_cmd_desc cmd;
3405
3406 switch (command) {
3407 case SIOCSIFMTU:
3408 TI_LOCK(sc);
3409 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3410 error = EINVAL;
3411 else {
3412 ifp->if_mtu = ifr->ifr_mtu;
3413 ti_init_locked(sc);
3414 }
3415 TI_UNLOCK(sc);
3416 break;
3417 case SIOCSIFFLAGS:
3418 TI_LOCK(sc);
3419 if (ifp->if_flags & IFF_UP) {
3420 /*
3421 * If only the state of the PROMISC flag changed,
3422 * then just use the 'set promisc mode' command
3423 * instead of reinitializing the entire NIC. Doing
3424 * a full re-init means reloading the firmware and
3425 * waiting for it to start up, which may take a
3426 * second or two.
3427 */
3428 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3429 ifp->if_flags & IFF_PROMISC &&
3430 !(sc->ti_if_flags & IFF_PROMISC)) {
3431 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3432 TI_CMD_CODE_PROMISC_ENB, 0);
3433 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3434 !(ifp->if_flags & IFF_PROMISC) &&
3435 sc->ti_if_flags & IFF_PROMISC) {
3436 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3437 TI_CMD_CODE_PROMISC_DIS, 0);
3438 } else
3439 ti_init_locked(sc);
3440 } else {
3441 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3442 ti_stop(sc);
3443 }
3444 }
3445 sc->ti_if_flags = ifp->if_flags;
3446 TI_UNLOCK(sc);
3447 break;
3448 case SIOCADDMULTI:
3449 case SIOCDELMULTI:
3450 TI_LOCK(sc);
3451 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3452 ti_setmulti(sc);
3453 TI_UNLOCK(sc);
3454 break;
3455 case SIOCSIFMEDIA:
3456 case SIOCGIFMEDIA:
3457 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3458 break;
3459 case SIOCSIFCAP:
3460 TI_LOCK(sc);
3461 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3462 if (mask & IFCAP_HWCSUM) {
3463 if (IFCAP_HWCSUM & ifp->if_capenable)
3464 ifp->if_capenable &= ~IFCAP_HWCSUM;
3465 else
3466 ifp->if_capenable |= IFCAP_HWCSUM;
3467 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3468 ti_init_locked(sc);
3469 }
3470 TI_UNLOCK(sc);
3471 break;
3472 default:
3473 error = ether_ioctl(ifp, command, data);
3474 break;
3475 }
3476
3477 return (error);
3478}
3479
3480static int
3481ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3482{
3483 struct ti_softc *sc;
3484
3485 sc = dev->si_drv1;
3486 if (sc == NULL)
3487 return (ENODEV);
3488
3489 TI_LOCK(sc);
3490 sc->ti_flags |= TI_FLAG_DEBUGING;
3491 TI_UNLOCK(sc);
3492
3493 return (0);
3494}
3495
3496static int
3497ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3498{
3499 struct ti_softc *sc;
3500
3501 sc = dev->si_drv1;
3502 if (sc == NULL)
3503 return (ENODEV);
3504
3505 TI_LOCK(sc);
3506 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3507 TI_UNLOCK(sc);
3508
3509 return (0);
3510}
3511
3512/*
3513 * This ioctl routine goes along with the Tigon character device.
3514 */
3515static int
3516ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3517 struct thread *td)
3518{
3519 int error;
3520 struct ti_softc *sc;
3521
3522 sc = dev->si_drv1;
3523 if (sc == NULL)
3524 return (ENODEV);
3525
3526 error = 0;
3527
3528 switch (cmd) {
3529 case TIIOCGETSTATS:
3530 {
3531 struct ti_stats *outstats;
3532
3533 outstats = (struct ti_stats *)addr;
3534
3535 TI_LOCK(sc);
3536 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3537 sizeof(struct ti_stats));
3538 TI_UNLOCK(sc);
3539 break;
3540 }
3541 case TIIOCGETPARAMS:
3542 {
3543 struct ti_params *params;
3544
3545 params = (struct ti_params *)addr;
3546
3547 TI_LOCK(sc);
3548 params->ti_stat_ticks = sc->ti_stat_ticks;
3549 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3550 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3551 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3552 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3553 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3554 params->param_mask = TI_PARAM_ALL;
3555 TI_UNLOCK(sc);
3556
3557 error = 0;
3558
3559 break;
3560 }
3561 case TIIOCSETPARAMS:
3562 {
3563 struct ti_params *params;
3564
3565 params = (struct ti_params *)addr;
3566
3567 TI_LOCK(sc);
3568 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3569 sc->ti_stat_ticks = params->ti_stat_ticks;
3570 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3571 }
3572
3573 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3574 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3575 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3576 sc->ti_rx_coal_ticks);
3577 }
3578
3579 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3580 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3581 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3582 sc->ti_tx_coal_ticks);
3583 }
3584
3585 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3586 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3587 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3588 sc->ti_rx_max_coal_bds);
3589 }
3590
3591 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3592 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3593 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3594 sc->ti_tx_max_coal_bds);
3595 }
3596
3597 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3598 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3599 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3600 sc->ti_tx_buf_ratio);
3601 }
3602 TI_UNLOCK(sc);
3603
3604 error = 0;
3605
3606 break;
3607 }
3608 case TIIOCSETTRACE: {
3609 ti_trace_type trace_type;
3610
3611 trace_type = *(ti_trace_type *)addr;
3612
3613 /*
3614 * Set tracing to whatever the user asked for. Setting
3615 * this register to 0 should have the effect of disabling
3616 * tracing.
3617 */
3618 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3619
3620 error = 0;
3621
3622 break;
3623 }
3624 case TIIOCGETTRACE: {
3625 struct ti_trace_buf *trace_buf;
3626 u_int32_t trace_start, cur_trace_ptr, trace_len;
3627
3628 trace_buf = (struct ti_trace_buf *)addr;
3629
3630 TI_LOCK(sc);
3631 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3632 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3633 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3634
3635#if 0
3636 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3637 "trace_len = %d\n", trace_start,
3638 cur_trace_ptr, trace_len);
3639 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3640 trace_buf->buf_len);
3641#endif
3642
3643 error = ti_copy_mem(sc, trace_start, min(trace_len,
3644 trace_buf->buf_len),
3645 (caddr_t)trace_buf->buf, 1, 1);
3646
3647 if (error == 0) {
3648 trace_buf->fill_len = min(trace_len,
3649 trace_buf->buf_len);
3650 if (cur_trace_ptr < trace_start)
3651 trace_buf->cur_trace_ptr =
3652 trace_start - cur_trace_ptr;
3653 else
3654 trace_buf->cur_trace_ptr =
3655 cur_trace_ptr - trace_start;
3656 } else
3657 trace_buf->fill_len = 0;
3658 TI_UNLOCK(sc);
3659
3660 break;
3661 }
3662
3663 /*
3664 * For debugging, five ioctls are needed:
3665 * ALT_ATTACH
3666 * ALT_READ_TG_REG
3667 * ALT_WRITE_TG_REG
3668 * ALT_READ_TG_MEM
3669 * ALT_WRITE_TG_MEM
3670 */
3671 case ALT_ATTACH:
3672 /*
3673 * From what I can tell, Alteon's Solaris Tigon driver
3674 * only has one character device, so you have to attach
3675 * to the Tigon board you're interested in. This seems
3676 * like a not-so-good way to do things, since unless you
3677 * subsequently specify the unit number of the device
3678 * you're interested in every ioctl, you'll only be
3679 * able to debug one board at a time.
3680 */
3681 error = 0;
3682 break;
3683 case ALT_READ_TG_MEM:
3684 case ALT_WRITE_TG_MEM:
3685 {
3686 struct tg_mem *mem_param;
3687 u_int32_t sram_end, scratch_end;
3688
3689 mem_param = (struct tg_mem *)addr;
3690
3691 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3692 sram_end = TI_END_SRAM_I;
3693 scratch_end = TI_END_SCRATCH_I;
3694 } else {
3695 sram_end = TI_END_SRAM_II;
3696 scratch_end = TI_END_SCRATCH_II;
3697 }
3698
3699 /*
3700 * For now, we'll only handle accessing regular SRAM,
3701 * nothing else.
3702 */
3703 TI_LOCK(sc);
3704 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3705 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3706 /*
3707 * In this instance, we always copy to/from user
3708 * space, so the user space argument is set to 1.
3709 */
3710 error = ti_copy_mem(sc, mem_param->tgAddr,
3711 mem_param->len,
3712 mem_param->userAddr, 1,
3713 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3714 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3715 && (mem_param->tgAddr <= scratch_end)) {
3716 error = ti_copy_scratch(sc, mem_param->tgAddr,
3717 mem_param->len,
3718 mem_param->userAddr, 1,
3719 (cmd == ALT_READ_TG_MEM) ?
3720 1 : 0, TI_PROCESSOR_A);
3721 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3722 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3723 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3724 if_printf(sc->ti_ifp,
3725 "invalid memory range for Tigon I\n");
3726 error = EINVAL;
3727 break;
3728 }
3729 error = ti_copy_scratch(sc, mem_param->tgAddr -
3730 TI_SCRATCH_DEBUG_OFF,
3731 mem_param->len,
3732 mem_param->userAddr, 1,
3733 (cmd == ALT_READ_TG_MEM) ?
3734 1 : 0, TI_PROCESSOR_B);
3735 } else {
3736 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3737 "out of supported range\n",
3738 mem_param->tgAddr, mem_param->len);
3739 error = EINVAL;
3740 }
3741 TI_UNLOCK(sc);
3742
3743 break;
3744 }
3745 case ALT_READ_TG_REG:
3746 case ALT_WRITE_TG_REG:
3747 {
3748 struct tg_reg *regs;
3749 u_int32_t tmpval;
3750
3751 regs = (struct tg_reg *)addr;
3752
3753 /*
3754 * Make sure the address in question isn't out of range.
3755 */
3756 if (regs->addr > TI_REG_MAX) {
3757 error = EINVAL;
3758 break;
3759 }
3760 TI_LOCK(sc);
3761 if (cmd == ALT_READ_TG_REG) {
3762 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3763 regs->addr, &tmpval, 1);
3764 regs->data = ntohl(tmpval);
3765#if 0
3766 if ((regs->addr == TI_CPU_STATE)
3767 || (regs->addr == TI_CPU_CTL_B)) {
3768 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3769 regs->addr, tmpval);
3770 }
3771#endif
3772 } else {
3773 tmpval = htonl(regs->data);
3774 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3775 regs->addr, &tmpval, 1);
3776 }
3777 TI_UNLOCK(sc);
3778
3779 break;
3780 }
3781 default:
3782 error = ENOTTY;
3783 break;
3784 }
3785 return (error);
3786}
3787
3788static void
3789ti_watchdog(ifp)
3790 struct ifnet *ifp;
3791{
3792 struct ti_softc *sc;
3793
3794 sc = ifp->if_softc;
3795 TI_LOCK(sc);
3796
3797 /*
3798 * When we're debugging, the chip is often stopped for long periods
3799 * of time, and that would normally cause the watchdog timer to fire.
3800 * Since that impedes debugging, we don't want to do that.
3801 */
3802 if (sc->ti_flags & TI_FLAG_DEBUGING) {
3803 TI_UNLOCK(sc);
3804 return;
3805 }
3806
3807 if_printf(ifp, "watchdog timeout -- resetting\n");
3808 ti_stop(sc);
3809 ti_init_locked(sc);
3810
3811 ifp->if_oerrors++;
3812 TI_UNLOCK(sc);
3813}
3814
3815/*
3816 * Stop the adapter and free any mbufs allocated to the
3817 * RX and TX lists.
3818 */
3819static void
3820ti_stop(sc)
3821 struct ti_softc *sc;
3822{
3823 struct ifnet *ifp;
3824 struct ti_cmd_desc cmd;
3825
3826 TI_LOCK_ASSERT(sc);
3827
3828 ifp = sc->ti_ifp;
3829
3830 /* Disable host interrupts. */
3831 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3832 /*
3833 * Tell firmware we're shutting down.
3834 */
3835 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3836
3837 /* Halt and reinitialize. */
3838 if (ti_chipinit(sc) != 0)
3839 return;
3840 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3841 if (ti_chipinit(sc) != 0)
3842 return;
3843
3844 /* Free the RX lists. */
3845 ti_free_rx_ring_std(sc);
3846
3847 /* Free jumbo RX list. */
3848 ti_free_rx_ring_jumbo(sc);
3849
3850 /* Free mini RX list. */
3851 ti_free_rx_ring_mini(sc);
3852
3853 /* Free TX buffers. */
3854 ti_free_tx_ring(sc);
3855
3856 sc->ti_ev_prodidx.ti_idx = 0;
3857 sc->ti_return_prodidx.ti_idx = 0;
3858 sc->ti_tx_considx.ti_idx = 0;
3859 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3860
3861 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3862}
3863
3864/*
3865 * Stop all chip I/O so that the kernel's probe routines don't
3866 * get confused by errant DMAs when rebooting.
3867 */
3868static int
3869ti_shutdown(dev)
3870 device_t dev;
3871{
3872 struct ti_softc *sc;
3873
3874 sc = device_get_softc(dev);
3875 TI_LOCK(sc);
3876 ti_chipinit(sc);
3877 TI_UNLOCK(sc);
3878
3879 return (0);
3880}