1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200910 2009-12-23 19:18:07Z yongari $");
35
36#ifdef HAVE_KERNEL_OPTION_HEADERS
37#include "opt_device_polling.h"
38#endif
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/bus.h>
43#include <sys/endian.h>
44#include <sys/kernel.h>
45#include <sys/lock.h>
46#include <sys/malloc.h>
47#include <sys/mbuf.h>
48#include <sys/module.h>
49#include <sys/rman.h>
50#include <sys/socket.h>
51#include <sys/sockio.h>
52#include <sys/sysctl.h>
53
54#include <net/bpf.h>
55#include <net/if.h>
56#include <net/if_arp.h>
57#include <net/ethernet.h>
58#include <net/if_dl.h>
59#include <net/if_media.h>
60#include <net/if_types.h>
61#include <net/if_vlan_var.h>
62
63#include <machine/bus.h>
64#include <machine/resource.h>
65
66#include <dev/mii/mii.h>
67#include <dev/mii/miivar.h>
68
69#include <dev/pci/pcireg.h>
70#include <dev/pci/pcivar.h>
71
72#include <dev/ste/if_stereg.h>
73
74/* "device miibus" required. See GENERIC if you get errors here. */
75#include "miibus_if.h"
76
77MODULE_DEPEND(ste, pci, 1, 1, 1);
78MODULE_DEPEND(ste, ether, 1, 1, 1);
79MODULE_DEPEND(ste, miibus, 1, 1, 1);
80
81/* Define to show Tx error status. */
82#define STE_SHOW_TXERRORS
83
84/*
85 * Various supported device vendors/types and their names.
86 */
87static struct ste_type ste_devs[] = {
88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" },
89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" },
90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
91 { 0, 0, NULL }
92};
93
94static int ste_attach(device_t);
95static int ste_detach(device_t);
96static int ste_probe(device_t);
97static int ste_shutdown(device_t);
98
99static int ste_dma_alloc(struct ste_softc *);
100static void ste_dma_free(struct ste_softc *);
101static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int);
102static int ste_eeprom_wait(struct ste_softc *);
103static int ste_encap(struct ste_softc *, struct mbuf **,
104 struct ste_chain *);
105static int ste_ifmedia_upd(struct ifnet *);
106static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
107static void ste_init(void *);
108static void ste_init_locked(struct ste_softc *);
109static int ste_init_rx_list(struct ste_softc *);
110static void ste_init_tx_list(struct ste_softc *);
111static void ste_intr(void *);
112static int ste_ioctl(struct ifnet *, u_long, caddr_t);
113static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *);
114static void ste_mii_send(struct ste_softc *, uint32_t, int);
115static void ste_mii_sync(struct ste_softc *);
116static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *);
117static int ste_miibus_readreg(device_t, int, int);
118static void ste_miibus_statchg(device_t);
119static int ste_miibus_writereg(device_t, int, int, int);
120static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *);
121static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int);
122static void ste_reset(struct ste_softc *);
123static void ste_restart_tx(struct ste_softc *);
124static int ste_rxeof(struct ste_softc *, int);
125static void ste_rxfilter(struct ste_softc *);
126static void ste_start(struct ifnet *);
127static void ste_start_locked(struct ifnet *);
128static void ste_stats_clear(struct ste_softc *);
129static void ste_stats_update(struct ste_softc *);
130static void ste_stop(struct ste_softc *);
131static void ste_sysctl_node(struct ste_softc *);
132static void ste_tick(void *);
133static void ste_txeoc(struct ste_softc *);
134static void ste_txeof(struct ste_softc *);
135static void ste_wait(struct ste_softc *);
136static void ste_watchdog(struct ste_softc *);
137
138static device_method_t ste_methods[] = {
139 /* Device interface */
140 DEVMETHOD(device_probe, ste_probe),
141 DEVMETHOD(device_attach, ste_attach),
142 DEVMETHOD(device_detach, ste_detach),
143 DEVMETHOD(device_shutdown, ste_shutdown),
144
145 /* bus interface */
146 DEVMETHOD(bus_print_child, bus_generic_print_child),
147 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
148
149 /* MII interface */
150 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
151 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
152 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
153
154 { 0, 0 }
155};
156
157static driver_t ste_driver = {
158 "ste",
159 ste_methods,
160 sizeof(struct ste_softc)
161};
162
163static devclass_t ste_devclass;
164
165DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
166DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
167
168#define STE_SETBIT4(sc, reg, x) \
169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
170
171#define STE_CLRBIT4(sc, reg, x) \
172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
173
174#define STE_SETBIT2(sc, reg, x) \
175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
176
177#define STE_CLRBIT2(sc, reg, x) \
178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
179
180#define STE_SETBIT1(sc, reg, x) \
181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
182
183#define STE_CLRBIT1(sc, reg, x) \
184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
185
186
187#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
188#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
189
190/*
191 * Sync the PHYs by setting data bit and strobing the clock 32 times.
192 */
193static void
194ste_mii_sync(struct ste_softc *sc)
195{
196 int i;
197
198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
199
200 for (i = 0; i < 32; i++) {
201 MII_SET(STE_PHYCTL_MCLK);
202 DELAY(1);
203 MII_CLR(STE_PHYCTL_MCLK);
204 DELAY(1);
205 }
206}
207
208/*
209 * Clock a series of bits through the MII.
210 */
211static void
212ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt)
213{
214 int i;
215
216 MII_CLR(STE_PHYCTL_MCLK);
217
218 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
219 if (bits & i) {
220 MII_SET(STE_PHYCTL_MDATA);
221 } else {
222 MII_CLR(STE_PHYCTL_MDATA);
223 }
224 DELAY(1);
225 MII_CLR(STE_PHYCTL_MCLK);
226 DELAY(1);
227 MII_SET(STE_PHYCTL_MCLK);
228 }
229}
230
231/*
232 * Read an PHY register through the MII.
233 */
234static int
235ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame)
236{
237 int i, ack;
238
239 /*
240 * Set up frame for RX.
241 */
242 frame->mii_stdelim = STE_MII_STARTDELIM;
243 frame->mii_opcode = STE_MII_READOP;
244 frame->mii_turnaround = 0;
245 frame->mii_data = 0;
246
247 CSR_WRITE_2(sc, STE_PHYCTL, 0);
248 /*
249 * Turn on data xmit.
250 */
251 MII_SET(STE_PHYCTL_MDIR);
252
253 ste_mii_sync(sc);
254
255 /*
256 * Send command/address info.
257 */
258 ste_mii_send(sc, frame->mii_stdelim, 2);
259 ste_mii_send(sc, frame->mii_opcode, 2);
260 ste_mii_send(sc, frame->mii_phyaddr, 5);
261 ste_mii_send(sc, frame->mii_regaddr, 5);
262
263 /* Turn off xmit. */
264 MII_CLR(STE_PHYCTL_MDIR);
265
266 /* Idle bit */
267 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
268 DELAY(1);
269 MII_SET(STE_PHYCTL_MCLK);
270 DELAY(1);
271
272 /* Check for ack */
273 MII_CLR(STE_PHYCTL_MCLK);
274 DELAY(1);
275 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
276 MII_SET(STE_PHYCTL_MCLK);
277 DELAY(1);
278
279 /*
280 * Now try reading data bits. If the ack failed, we still
281 * need to clock through 16 cycles to keep the PHY(s) in sync.
282 */
283 if (ack) {
284 for (i = 0; i < 16; i++) {
285 MII_CLR(STE_PHYCTL_MCLK);
286 DELAY(1);
287 MII_SET(STE_PHYCTL_MCLK);
288 DELAY(1);
289 }
290 goto fail;
291 }
292
293 for (i = 0x8000; i; i >>= 1) {
294 MII_CLR(STE_PHYCTL_MCLK);
295 DELAY(1);
296 if (!ack) {
297 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
298 frame->mii_data |= i;
299 DELAY(1);
300 }
301 MII_SET(STE_PHYCTL_MCLK);
302 DELAY(1);
303 }
304
305fail:
306
307 MII_CLR(STE_PHYCTL_MCLK);
308 DELAY(1);
309 MII_SET(STE_PHYCTL_MCLK);
310 DELAY(1);
311
312 if (ack)
313 return (1);
314 return (0);
315}
316
317/*
318 * Write to a PHY register through the MII.
319 */
320static int
321ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame)
322{
323
324 /*
325 * Set up frame for TX.
326 */
327
328 frame->mii_stdelim = STE_MII_STARTDELIM;
329 frame->mii_opcode = STE_MII_WRITEOP;
330 frame->mii_turnaround = STE_MII_TURNAROUND;
331
332 /*
333 * Turn on data output.
334 */
335 MII_SET(STE_PHYCTL_MDIR);
336
337 ste_mii_sync(sc);
338
339 ste_mii_send(sc, frame->mii_stdelim, 2);
340 ste_mii_send(sc, frame->mii_opcode, 2);
341 ste_mii_send(sc, frame->mii_phyaddr, 5);
342 ste_mii_send(sc, frame->mii_regaddr, 5);
343 ste_mii_send(sc, frame->mii_turnaround, 2);
344 ste_mii_send(sc, frame->mii_data, 16);
345
346 /* Idle bit. */
347 MII_SET(STE_PHYCTL_MCLK);
348 DELAY(1);
349 MII_CLR(STE_PHYCTL_MCLK);
350 DELAY(1);
351
352 /*
353 * Turn off xmit.
354 */
355 MII_CLR(STE_PHYCTL_MDIR);
356
357 return (0);
358}
359
360static int
361ste_miibus_readreg(device_t dev, int phy, int reg)
362{
363 struct ste_softc *sc;
364 struct ste_mii_frame frame;
365
366 sc = device_get_softc(dev);
367
368 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0)
369 return (0);
370
371 bzero((char *)&frame, sizeof(frame));
372
373 frame.mii_phyaddr = phy;
374 frame.mii_regaddr = reg;
375 ste_mii_readreg(sc, &frame);
376
377 return (frame.mii_data);
378}
379
380static int
381ste_miibus_writereg(device_t dev, int phy, int reg, int data)
382{
383 struct ste_softc *sc;
384 struct ste_mii_frame frame;
385
386 sc = device_get_softc(dev);
387 bzero((char *)&frame, sizeof(frame));
388
389 frame.mii_phyaddr = phy;
390 frame.mii_regaddr = reg;
391 frame.mii_data = data;
392
393 ste_mii_writereg(sc, &frame);
394
395 return (0);
396}
397
398static void
399ste_miibus_statchg(device_t dev)
400{
401 struct ste_softc *sc;
402 struct mii_data *mii;
403 struct ifnet *ifp;
404 uint16_t cfg;
405
406 sc = device_get_softc(dev);
407
408 mii = device_get_softc(sc->ste_miibus);
409 ifp = sc->ste_ifp;
410 if (mii == NULL || ifp == NULL ||
411 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
412 return;
413
414 sc->ste_flags &= ~STE_FLAG_LINK;
415 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
416 (IFM_ACTIVE | IFM_AVALID)) {
417 switch (IFM_SUBTYPE(mii->mii_media_active)) {
418 case IFM_10_T:
419 case IFM_100_TX:
420 case IFM_100_FX:
421 case IFM_100_T4:
422 sc->ste_flags |= STE_FLAG_LINK;
423 default:
424 break;
425 }
426 }
427
428 /* Program MACs with resolved speed/duplex/flow-control. */
429 if ((sc->ste_flags & STE_FLAG_LINK) != 0) {
430 cfg = CSR_READ_2(sc, STE_MACCTL0);
431 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX);
432 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
433 /*
434 * ST201 data sheet says driver should enable receiving
435 * MAC control frames bit of receive mode register to
436 * receive flow-control frames but the register has no
437 * such bits. In addition the controller has no ability
438 * to send pause frames so it should be handled in
439 * driver. Implementing pause timer handling in driver
440 * layer is not trivial, so don't enable flow-control
441 * here.
442 */
443 cfg |= STE_MACCTL0_FULLDUPLEX;
444 }
445 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
446 }
447}
448
449static int
450ste_ifmedia_upd(struct ifnet *ifp)
451{
452 struct ste_softc *sc;
453 struct mii_data *mii;
454 struct mii_softc *miisc;
455 int error;
456
457 sc = ifp->if_softc;
458 STE_LOCK(sc);
459 mii = device_get_softc(sc->ste_miibus);
460 if (mii->mii_instance) {
461 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
462 mii_phy_reset(miisc);
463 }
464 error = mii_mediachg(mii);
465 STE_UNLOCK(sc);
466
467 return (error);
468}
469
470static void
471ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
472{
473 struct ste_softc *sc;
474 struct mii_data *mii;
475
476 sc = ifp->if_softc;
477 mii = device_get_softc(sc->ste_miibus);
478
479 STE_LOCK(sc);
480 if ((ifp->if_flags & IFF_UP) == 0) {
481 STE_UNLOCK(sc);
482 return;
483 }
484 mii_pollstat(mii);
485 ifmr->ifm_active = mii->mii_media_active;
486 ifmr->ifm_status = mii->mii_media_status;
487 STE_UNLOCK(sc);
488}
489
490static void
491ste_wait(struct ste_softc *sc)
492{
493 int i;
494
495 for (i = 0; i < STE_TIMEOUT; i++) {
496 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
497 break;
498 DELAY(1);
499 }
500
501 if (i == STE_TIMEOUT)
502 device_printf(sc->ste_dev, "command never completed!\n");
503}
504
505/*
506 * The EEPROM is slow: give it time to come ready after issuing
507 * it a command.
508 */
509static int
510ste_eeprom_wait(struct ste_softc *sc)
511{
512 int i;
513
514 DELAY(1000);
515
516 for (i = 0; i < 100; i++) {
517 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
518 DELAY(1000);
519 else
520 break;
521 }
522
523 if (i == 100) {
524 device_printf(sc->ste_dev, "eeprom failed to come ready\n");
525 return (1);
526 }
527
528 return (0);
529}
530
531/*
532 * Read a sequence of words from the EEPROM. Note that ethernet address
533 * data is stored in the EEPROM in network byte order.
534 */
535static int
536ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap)
537{
538 uint16_t word, *ptr;
539 int err = 0, i;
540
541 if (ste_eeprom_wait(sc))
542 return (1);
543
544 for (i = 0; i < cnt; i++) {
545 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
546 err = ste_eeprom_wait(sc);
547 if (err)
548 break;
549 word = CSR_READ_2(sc, STE_EEPROM_DATA);
550 ptr = (uint16_t *)(dest + (i * 2));
551 if (swap)
552 *ptr = ntohs(word);
553 else
554 *ptr = word;
555 }
556
557 return (err ? 1 : 0);
558}
559
560static void
561ste_rxfilter(struct ste_softc *sc)
562{
563 struct ifnet *ifp;
564 struct ifmultiaddr *ifma;
565 uint32_t hashes[2] = { 0, 0 };
566 uint8_t rxcfg;
567 int h;
568
569 STE_LOCK_ASSERT(sc);
570
571 ifp = sc->ste_ifp;
572 rxcfg = CSR_READ_1(sc, STE_RX_MODE);
573 rxcfg |= STE_RXMODE_UNICAST;
574 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH |
575 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC);
576 if (ifp->if_flags & IFF_BROADCAST)
577 rxcfg |= STE_RXMODE_BROADCAST;
578 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
579 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
580 rxcfg |= STE_RXMODE_ALLMULTI;
581 if ((ifp->if_flags & IFF_PROMISC) != 0)
582 rxcfg |= STE_RXMODE_PROMISC;
583 goto chipit;
584 }
585
586 rxcfg |= STE_RXMODE_MULTIHASH;
587 /* Now program new ones. */
588 if_maddr_rlock(ifp);
589 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
590 if (ifma->ifma_addr->sa_family != AF_LINK)
591 continue;
592 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
593 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F;
594 if (h < 32)
595 hashes[0] |= (1 << h);
596 else
597 hashes[1] |= (1 << (h - 32));
598 }
599 if_maddr_runlock(ifp);
600
601chipit:
602 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
603 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
604 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
605 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
606 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
607 CSR_READ_1(sc, STE_RX_MODE);
608}
609
610#ifdef DEVICE_POLLING
611static poll_handler_t ste_poll, ste_poll_locked;
612
613static int
614ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
615{
616 struct ste_softc *sc = ifp->if_softc;
617 int rx_npkts = 0;
618
619 STE_LOCK(sc);
620 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
621 rx_npkts = ste_poll_locked(ifp, cmd, count);
622 STE_UNLOCK(sc);
623 return (rx_npkts);
624}
625
626static int
627ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
628{
629 struct ste_softc *sc = ifp->if_softc;
630 int rx_npkts;
631
632 STE_LOCK_ASSERT(sc);
633
634 rx_npkts = ste_rxeof(sc, count);
635 ste_txeof(sc);
636 ste_txeoc(sc);
637 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
638 ste_start_locked(ifp);
639
640 if (cmd == POLL_AND_CHECK_STATUS) {
641 uint16_t status;
642
643 status = CSR_READ_2(sc, STE_ISR_ACK);
644
645 if (status & STE_ISR_STATS_OFLOW)
646 ste_stats_update(sc);
647
648 if (status & STE_ISR_HOSTERR) {
649 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
650 ste_init_locked(sc);
651 }
652 }
653 return (rx_npkts);
654}
655#endif /* DEVICE_POLLING */
656
657static void
658ste_intr(void *xsc)
659{
660 struct ste_softc *sc;
661 struct ifnet *ifp;
662 uint16_t status;
663
664 sc = xsc;
665 STE_LOCK(sc);
666 ifp = sc->ste_ifp;
667
668#ifdef DEVICE_POLLING
669 if (ifp->if_capenable & IFCAP_POLLING) {
670 STE_UNLOCK(sc);
671 return;
672 }
673#endif
674
675 /* See if this is really our interrupt. */
676 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) {
677 STE_UNLOCK(sc);
678 return;
679 }
680
681 for (;;) {
682 status = CSR_READ_2(sc, STE_ISR_ACK);
683
684 if (!(status & STE_INTRS))
685 break;
686
687 if (status & STE_ISR_RX_DMADONE)
688 ste_rxeof(sc, -1);
689
690 if (status & STE_ISR_TX_DMADONE)
691 ste_txeof(sc);
692
693 if (status & STE_ISR_TX_DONE)
694 ste_txeoc(sc);
695
696 if (status & STE_ISR_STATS_OFLOW)
697 ste_stats_update(sc);
698
699 if (status & STE_ISR_HOSTERR) {
700 ste_init_locked(sc);
701 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
702 }
703 }
704
705 /* Re-enable interrupts */
706 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
707
708 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
709 ste_start_locked(ifp);
710
711 STE_UNLOCK(sc);
712}
713
714/*
715 * A frame has been uploaded: pass the resulting mbuf chain up to
716 * the higher level protocols.
717 */
718static int
719ste_rxeof(struct ste_softc *sc, int count)
720{
721 struct mbuf *m;
722 struct ifnet *ifp;
723 struct ste_chain_onefrag *cur_rx;
724 uint32_t rxstat;
725 int total_len, rx_npkts;
726
727 ifp = sc->ste_ifp;
728
729 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
730 sc->ste_cdata.ste_rx_list_map,
731 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
732
733 cur_rx = sc->ste_cdata.ste_rx_head;
734 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++,
735 cur_rx = cur_rx->ste_next) {
736 rxstat = le32toh(cur_rx->ste_ptr->ste_status);
737 if ((rxstat & STE_RXSTAT_DMADONE) == 0)
738 break;
739#ifdef DEVICE_POLLING
740 if (ifp->if_capenable & IFCAP_POLLING) {
741 if (count == 0)
742 break;
743 count--;
744 }
745#endif
746 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
747 break;
748 /*
749 * If an error occurs, update stats, clear the
750 * status word and leave the mbuf cluster in place:
751 * it should simply get re-used next time this descriptor
752 * comes up in the ring.
753 */
754 if (rxstat & STE_RXSTAT_FRAME_ERR) {
755 ifp->if_ierrors++;
756 cur_rx->ste_ptr->ste_status = 0;
757 continue;
758 }
759
760 /* No errors; receive the packet. */
761 m = cur_rx->ste_mbuf;
762 total_len = STE_RX_BYTES(rxstat);
763
764 /*
765 * Try to conjure up a new mbuf cluster. If that
766 * fails, it means we have an out of memory condition and
767 * should leave the buffer in place and continue. This will
768 * result in a lost packet, but there's little else we
769 * can do in this situation.
770 */
771 if (ste_newbuf(sc, cur_rx) != 0) {
772 ifp->if_ierrors++;
773 cur_rx->ste_ptr->ste_status = 0;
774 continue;
775 }
776
777 m->m_pkthdr.rcvif = ifp;
778 m->m_pkthdr.len = m->m_len = total_len;
779
780 ifp->if_ipackets++;
781 STE_UNLOCK(sc);
782 (*ifp->if_input)(ifp, m);
783 STE_LOCK(sc);
784 }
785
786 if (rx_npkts > 0) {
787 sc->ste_cdata.ste_rx_head = cur_rx;
788 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
789 sc->ste_cdata.ste_rx_list_map,
790 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
791 }
792
793 return (rx_npkts);
794}
795
796static void
797ste_txeoc(struct ste_softc *sc)
798{
799 uint16_t txstat;
800 struct ifnet *ifp;
801
802 STE_LOCK_ASSERT(sc);
803
804 ifp = sc->ste_ifp;
805
806 /*
807 * STE_TX_STATUS register implements a queue of up to 31
808 * transmit status byte. Writing an arbitrary value to the
809 * register will advance the queue to the next transmit
810 * status byte. This means if driver does not read
811 * STE_TX_STATUS register after completing sending more
812 * than 31 frames the controller would be stalled so driver
813 * should re-wake the Tx MAC. This is the most severe
814 * limitation of ST201 based controller.
815 */
816 for (;;) {
817 txstat = CSR_READ_2(sc, STE_TX_STATUS);
818 if ((txstat & STE_TXSTATUS_TXDONE) == 0)
819 break;
820 if ((txstat & (STE_TXSTATUS_UNDERRUN |
821 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR |
822 STE_TXSTATUS_STATSOFLOW)) != 0) {
823 ifp->if_oerrors++;
824#ifdef STE_SHOW_TXERRORS
825 device_printf(sc->ste_dev, "TX error : 0x%b\n",
826 txstat & 0xFF, STE_ERR_BITS);
827#endif
828 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 &&
829 sc->ste_tx_thresh < STE_PACKET_SIZE) {
830 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
831 if (sc->ste_tx_thresh > STE_PACKET_SIZE)
832 sc->ste_tx_thresh = STE_PACKET_SIZE;
833 device_printf(sc->ste_dev,
834 "TX underrun, increasing TX"
835 " start threshold to %d bytes\n",
836 sc->ste_tx_thresh);
837 /* Make sure to disable active DMA cycles. */
838 STE_SETBIT4(sc, STE_DMACTL,
839 STE_DMACTL_TXDMA_STALL);
840 ste_wait(sc);
841 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
842 ste_init_locked(sc);
843 break;
844 }
845 /* Restart Tx. */
846 ste_restart_tx(sc);
847 }
848 /*
849 * Advance to next status and ACK TxComplete
850 * interrupt. ST201 data sheet was wrong here, to
851 * get next Tx status, we have to write both
852 * STE_TX_STATUS and STE_TX_FRAMEID register.
853 * Otherwise controller returns the same status
854 * as well as not acknowledge Tx completion
855 * interrupt.
856 */
857 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
858 }
859}
860
861static void
862ste_tick(void *arg)
863{
864 struct ste_softc *sc;
865 struct mii_data *mii;
866
867 sc = (struct ste_softc *)arg;
868
869 STE_LOCK_ASSERT(sc);
870
871 mii = device_get_softc(sc->ste_miibus);
872 mii_tick(mii);
873 /*
874 * ukphy(4) does not seem to generate CB that reports
875 * resolved link state so if we know we lost a link,
876 * explicitly check the link state.
877 */
878 if ((sc->ste_flags & STE_FLAG_LINK) == 0)
879 ste_miibus_statchg(sc->ste_dev);
880 ste_stats_update(sc);
881 ste_watchdog(sc);
882 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
883}
884
885static void
886ste_txeof(struct ste_softc *sc)
887{
888 struct ifnet *ifp;
889 struct ste_chain *cur_tx;
890 uint32_t txstat;
891 int idx;
892
893 STE_LOCK_ASSERT(sc);
894
895 ifp = sc->ste_ifp;
896 idx = sc->ste_cdata.ste_tx_cons;
897 if (idx == sc->ste_cdata.ste_tx_prod)
898 return;
899
900 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
901 sc->ste_cdata.ste_tx_list_map,
902 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
903
904 while (idx != sc->ste_cdata.ste_tx_prod) {
905 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
906 txstat = le32toh(cur_tx->ste_ptr->ste_ctl);
907 if ((txstat & STE_TXCTL_DMADONE) == 0)
908 break;
909 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map,
910 BUS_DMASYNC_POSTWRITE);
911 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map);
912 KASSERT(cur_tx->ste_mbuf != NULL,
913 ("%s: freeing NULL mbuf!\n", __func__));
914 m_freem(cur_tx->ste_mbuf);
915 cur_tx->ste_mbuf = NULL;
916 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
917 ifp->if_opackets++;
918 sc->ste_cdata.ste_tx_cnt--;
919 STE_INC(idx, STE_TX_LIST_CNT);
920 }
921
922 sc->ste_cdata.ste_tx_cons = idx;
923 if (sc->ste_cdata.ste_tx_cnt == 0)
924 sc->ste_timer = 0;
925}
926
927static void
928ste_stats_clear(struct ste_softc *sc)
929{
930
931 STE_LOCK_ASSERT(sc);
932
933 /* Rx stats. */
934 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO);
935 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI);
936 CSR_READ_2(sc, STE_STAT_RX_FRAMES);
937 CSR_READ_1(sc, STE_STAT_RX_BCAST);
938 CSR_READ_1(sc, STE_STAT_RX_MCAST);
939 CSR_READ_1(sc, STE_STAT_RX_LOST);
940 /* Tx stats. */
941 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO);
942 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI);
943 CSR_READ_2(sc, STE_STAT_TX_FRAMES);
944 CSR_READ_1(sc, STE_STAT_TX_BCAST);
945 CSR_READ_1(sc, STE_STAT_TX_MCAST);
946 CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
947 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
948 CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
949 CSR_READ_1(sc, STE_STAT_LATE_COLLS);
950 CSR_READ_1(sc, STE_STAT_TX_DEFER);
951 CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
952 CSR_READ_1(sc, STE_STAT_TX_ABORT);
953}
954
955static void
956ste_stats_update(struct ste_softc *sc)
957{
958 struct ifnet *ifp;
959 struct ste_hw_stats *stats;
960 uint32_t val;
961
962 STE_LOCK_ASSERT(sc);
963
964 ifp = sc->ste_ifp;
965 stats = &sc->ste_stats;
966 /* Rx stats. */
967 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) |
968 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16;
969 val &= 0x000FFFFF;
970 stats->rx_bytes += val;
971 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES);
972 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST);
973 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST);
974 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST);
975 /* Tx stats. */
976 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) |
977 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16;
978 val &= 0x000FFFFF;
979 stats->tx_bytes += val;
980 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES);
981 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST);
982 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST);
983 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
984 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
985 stats->tx_single_colls += val;
986 ifp->if_collisions += val;
987 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
988 stats->tx_multi_colls += val;
989 ifp->if_collisions += val;
990 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS);
991 stats->tx_late_colls += val;
992 ifp->if_collisions += val;
993 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER);
994 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
995 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT);
996}
997
998/*
999 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
1000 * IDs against our list and return a device name if we find a match.
1001 */
1002static int
1003ste_probe(device_t dev)
1004{
1005 struct ste_type *t;
1006
1007 t = ste_devs;
1008
1009 while (t->ste_name != NULL) {
1010 if ((pci_get_vendor(dev) == t->ste_vid) &&
1011 (pci_get_device(dev) == t->ste_did)) {
1012 device_set_desc(dev, t->ste_name);
1013 return (BUS_PROBE_DEFAULT);
1014 }
1015 t++;
1016 }
1017
1018 return (ENXIO);
1019}
1020
1021/*
1022 * Attach the interface. Allocate softc structures, do ifmedia
1023 * setup and ethernet/BPF attach.
1024 */
1025static int
1026ste_attach(device_t dev)
1027{
1028 struct ste_softc *sc;
1029 struct ifnet *ifp;
1030 u_char eaddr[6];
1031 int error = 0, rid;
1032
1033 sc = device_get_softc(dev);
1034 sc->ste_dev = dev;
1035
1036 /*
1037 * Only use one PHY since this chip reports multiple
1038 * Note on the DFE-550 the PHY is at 1 on the DFE-580
1039 * it is at 0 & 1. It is rev 0x12.
1040 */
1041 if (pci_get_vendor(dev) == DL_VENDORID &&
1042 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
1043 pci_get_revid(dev) == 0x12 )
1044 sc->ste_flags |= STE_FLAG_ONE_PHY;
1045
1046 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1047 MTX_DEF);
1048 /*
1049 * Map control/status registers.
1050 */
1051 pci_enable_busmaster(dev);
1052
1053 /* Prefer memory space register mapping over IO space. */
1054 sc->ste_res_id = PCIR_BAR(1);
1055 sc->ste_res_type = SYS_RES_MEMORY;
1056 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
1057 &sc->ste_res_id, RF_ACTIVE);
1058 if (sc->ste_res == NULL) {
1059 sc->ste_res_id = PCIR_BAR(0);
1060 sc->ste_res_type = SYS_RES_IOPORT;
1061 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
1062 &sc->ste_res_id, RF_ACTIVE);
1063 }
1064 if (sc->ste_res == NULL) {
1065 device_printf(dev, "couldn't map ports/memory\n");
1066 error = ENXIO;
1067 goto fail;
1068 }
1069
1070 /* Allocate interrupt */
1071 rid = 0;
1072 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1073 RF_SHAREABLE | RF_ACTIVE);
1074
1075 if (sc->ste_irq == NULL) {
1076 device_printf(dev, "couldn't map interrupt\n");
1077 error = ENXIO;
1078 goto fail;
1079 }
1080
1081 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0);
1082
1083 /* Reset the adapter. */
1084 ste_reset(sc);
1085
1086 /*
1087 * Get station address from the EEPROM.
1088 */
1089 if (ste_read_eeprom(sc, eaddr,
1090 STE_EEADDR_NODE0, 3, 0)) {
1091 device_printf(dev, "failed to read station address\n");
1092 error = ENXIO;;
1093 goto fail;
1094 }
1095 ste_sysctl_node(sc);
1096
1097 if ((error = ste_dma_alloc(sc)) != 0)
1098 goto fail;
1099
1100 ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
1101 if (ifp == NULL) {
1102 device_printf(dev, "can not if_alloc()\n");
1103 error = ENOSPC;
1104 goto fail;
1105 }
1106
1107 /* Do MII setup. */
1108 if (mii_phy_probe(dev, &sc->ste_miibus,
1109 ste_ifmedia_upd, ste_ifmedia_sts)) {
1110 device_printf(dev, "MII without any phy!\n");
1111 error = ENXIO;
1112 goto fail;
1113 }
1114
1115 ifp->if_softc = sc;
1116 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1117 ifp->if_mtu = ETHERMTU;
1118 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1119 ifp->if_ioctl = ste_ioctl;
1120 ifp->if_start = ste_start;
1121 ifp->if_init = ste_init;
1122 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1123 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
1124 IFQ_SET_READY(&ifp->if_snd);
1125
1126 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1127
1128 /*
1129 * Call MI attach routine.
1130 */
1131 ether_ifattach(ifp, eaddr);
1132
1133 /*
1134 * Tell the upper layer(s) we support long frames.
1135 */
1136 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1137 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1138 ifp->if_capenable = ifp->if_capabilities;
1139#ifdef DEVICE_POLLING
1140 ifp->if_capabilities |= IFCAP_POLLING;
1141#endif
1142
1143 /* Hook interrupt last to avoid having to lock softc */
1144 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
1145 NULL, ste_intr, sc, &sc->ste_intrhand);
1146
1147 if (error) {
1148 device_printf(dev, "couldn't set up irq\n");
1149 ether_ifdetach(ifp);
1150 goto fail;
1151 }
1152
1153fail:
1154 if (error)
1155 ste_detach(dev);
1156
1157 return (error);
1158}
1159
1160/*
1161 * Shutdown hardware and free up resources. This can be called any
1162 * time after the mutex has been initialized. It is called in both
1163 * the error case in attach and the normal detach case so it needs
1164 * to be careful about only freeing resources that have actually been
1165 * allocated.
1166 */
1167static int
1168ste_detach(device_t dev)
1169{
1170 struct ste_softc *sc;
1171 struct ifnet *ifp;
1172
1173 sc = device_get_softc(dev);
1174 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1175 ifp = sc->ste_ifp;
1176
1177#ifdef DEVICE_POLLING
1178 if (ifp->if_capenable & IFCAP_POLLING)
1179 ether_poll_deregister(ifp);
1180#endif
1181
1182 /* These should only be active if attach succeeded */
1183 if (device_is_attached(dev)) {
1184 ether_ifdetach(ifp);
1185 STE_LOCK(sc);
1186 ste_stop(sc);
1187 STE_UNLOCK(sc);
1188 callout_drain(&sc->ste_callout);
1189 }
1190 if (sc->ste_miibus)
1191 device_delete_child(dev, sc->ste_miibus);
1192 bus_generic_detach(dev);
1193
1194 if (sc->ste_intrhand)
1195 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1196 if (sc->ste_irq)
1197 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1198 if (sc->ste_res)
1199 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id,
1200 sc->ste_res);
1201
1202 if (ifp)
1203 if_free(ifp);
1204
1205 ste_dma_free(sc);
1206 mtx_destroy(&sc->ste_mtx);
1207
1208 return (0);
1209}
1210
1211struct ste_dmamap_arg {
1212 bus_addr_t ste_busaddr;
1213};
1214
1215static void
1216ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1217{
1218 struct ste_dmamap_arg *ctx;
1219
1220 if (error != 0)
1221 return;
1222
1223 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1224
1225 ctx = (struct ste_dmamap_arg *)arg;
1226 ctx->ste_busaddr = segs[0].ds_addr;
1227}
1228
1229static int
1230ste_dma_alloc(struct ste_softc *sc)
1231{
1232 struct ste_chain *txc;
1233 struct ste_chain_onefrag *rxc;
1234 struct ste_dmamap_arg ctx;
1235 int error, i;
1236
1237 /* Create parent DMA tag. */
1238 error = bus_dma_tag_create(
1239 bus_get_dma_tag(sc->ste_dev), /* parent */
1240 1, 0, /* alignment, boundary */
1241 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1242 BUS_SPACE_MAXADDR, /* highaddr */
1243 NULL, NULL, /* filter, filterarg */
1244 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1245 0, /* nsegments */
1246 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1247 0, /* flags */
1248 NULL, NULL, /* lockfunc, lockarg */
1249 &sc->ste_cdata.ste_parent_tag);
1250 if (error != 0) {
1251 device_printf(sc->ste_dev,
1252 "could not create parent DMA tag.\n");
1253 goto fail;
1254 }
1255
1256 /* Create DMA tag for Tx descriptor list. */
1257 error = bus_dma_tag_create(
1258 sc->ste_cdata.ste_parent_tag, /* parent */
1259 STE_DESC_ALIGN, 0, /* alignment, boundary */
1260 BUS_SPACE_MAXADDR, /* lowaddr */
1261 BUS_SPACE_MAXADDR, /* highaddr */
1262 NULL, NULL, /* filter, filterarg */
1263 STE_TX_LIST_SZ, /* maxsize */
1264 1, /* nsegments */
1265 STE_TX_LIST_SZ, /* maxsegsize */
1266 0, /* flags */
1267 NULL, NULL, /* lockfunc, lockarg */
1268 &sc->ste_cdata.ste_tx_list_tag);
1269 if (error != 0) {
1270 device_printf(sc->ste_dev,
1271 "could not create Tx list DMA tag.\n");
1272 goto fail;
1273 }
1274
1275 /* Create DMA tag for Rx descriptor list. */
1276 error = bus_dma_tag_create(
1277 sc->ste_cdata.ste_parent_tag, /* parent */
1278 STE_DESC_ALIGN, 0, /* alignment, boundary */
1279 BUS_SPACE_MAXADDR, /* lowaddr */
1280 BUS_SPACE_MAXADDR, /* highaddr */
1281 NULL, NULL, /* filter, filterarg */
1282 STE_RX_LIST_SZ, /* maxsize */
1283 1, /* nsegments */
1284 STE_RX_LIST_SZ, /* maxsegsize */
1285 0, /* flags */
1286 NULL, NULL, /* lockfunc, lockarg */
1287 &sc->ste_cdata.ste_rx_list_tag);
1288 if (error != 0) {
1289 device_printf(sc->ste_dev,
1290 "could not create Rx list DMA tag.\n");
1291 goto fail;
1292 }
1293
1294 /* Create DMA tag for Tx buffers. */
1295 error = bus_dma_tag_create(
1296 sc->ste_cdata.ste_parent_tag, /* parent */
1297 1, 0, /* alignment, boundary */
1298 BUS_SPACE_MAXADDR, /* lowaddr */
1299 BUS_SPACE_MAXADDR, /* highaddr */
1300 NULL, NULL, /* filter, filterarg */
1301 MCLBYTES * STE_MAXFRAGS, /* maxsize */
1302 STE_MAXFRAGS, /* nsegments */
1303 MCLBYTES, /* maxsegsize */
1304 0, /* flags */
1305 NULL, NULL, /* lockfunc, lockarg */
1306 &sc->ste_cdata.ste_tx_tag);
1307 if (error != 0) {
1308 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n");
1309 goto fail;
1310 }
1311
1312 /* Create DMA tag for Rx buffers. */
1313 error = bus_dma_tag_create(
1314 sc->ste_cdata.ste_parent_tag, /* parent */
1315 1, 0, /* alignment, boundary */
1316 BUS_SPACE_MAXADDR, /* lowaddr */
1317 BUS_SPACE_MAXADDR, /* highaddr */
1318 NULL, NULL, /* filter, filterarg */
1319 MCLBYTES, /* maxsize */
1320 1, /* nsegments */
1321 MCLBYTES, /* maxsegsize */
1322 0, /* flags */
1323 NULL, NULL, /* lockfunc, lockarg */
1324 &sc->ste_cdata.ste_rx_tag);
1325 if (error != 0) {
1326 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n");
1327 goto fail;
1328 }
1329
1330 /* Allocate DMA'able memory and load the DMA map for Tx list. */
1331 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag,
1332 (void **)&sc->ste_ldata.ste_tx_list,
1333 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1334 &sc->ste_cdata.ste_tx_list_map);
1335 if (error != 0) {
1336 device_printf(sc->ste_dev,
1337 "could not allocate DMA'able memory for Tx list.\n");
1338 goto fail;
1339 }
1340 ctx.ste_busaddr = 0;
1341 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag,
1342 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list,
1343 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1344 if (error != 0 || ctx.ste_busaddr == 0) {
1345 device_printf(sc->ste_dev,
1346 "could not load DMA'able memory for Tx list.\n");
1347 goto fail;
1348 }
1349 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr;
1350
1351 /* Allocate DMA'able memory and load the DMA map for Rx list. */
1352 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag,
1353 (void **)&sc->ste_ldata.ste_rx_list,
1354 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1355 &sc->ste_cdata.ste_rx_list_map);
1356 if (error != 0) {
1357 device_printf(sc->ste_dev,
1358 "could not allocate DMA'able memory for Rx list.\n");
1359 goto fail;
1360 }
1361 ctx.ste_busaddr = 0;
1362 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag,
1363 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list,
1364 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1365 if (error != 0 || ctx.ste_busaddr == 0) {
1366 device_printf(sc->ste_dev,
1367 "could not load DMA'able memory for Rx list.\n");
1368 goto fail;
1369 }
1370 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr;
1371
1372 /* Create DMA maps for Tx buffers. */
1373 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1374 txc = &sc->ste_cdata.ste_tx_chain[i];
1375 txc->ste_ptr = NULL;
1376 txc->ste_mbuf = NULL;
1377 txc->ste_next = NULL;
1378 txc->ste_phys = 0;
1379 txc->ste_map = NULL;
1380 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0,
1381 &txc->ste_map);
1382 if (error != 0) {
1383 device_printf(sc->ste_dev,
1384 "could not create Tx dmamap.\n");
1385 goto fail;
1386 }
1387 }
1388 /* Create DMA maps for Rx buffers. */
1389 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1390 &sc->ste_cdata.ste_rx_sparemap)) != 0) {
1391 device_printf(sc->ste_dev,
1392 "could not create spare Rx dmamap.\n");
1393 goto fail;
1394 }
1395 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1396 rxc = &sc->ste_cdata.ste_rx_chain[i];
1397 rxc->ste_ptr = NULL;
1398 rxc->ste_mbuf = NULL;
1399 rxc->ste_next = NULL;
1400 rxc->ste_map = NULL;
1401 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1402 &rxc->ste_map);
1403 if (error != 0) {
1404 device_printf(sc->ste_dev,
1405 "could not create Rx dmamap.\n");
1406 goto fail;
1407 }
1408 }
1409
1410fail:
1411 return (error);
1412}
1413
1414static void
1415ste_dma_free(struct ste_softc *sc)
1416{
1417 struct ste_chain *txc;
1418 struct ste_chain_onefrag *rxc;
1419 int i;
1420
1421 /* Tx buffers. */
1422 if (sc->ste_cdata.ste_tx_tag != NULL) {
1423 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1424 txc = &sc->ste_cdata.ste_tx_chain[i];
1425 if (txc->ste_map != NULL) {
1426 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag,
1427 txc->ste_map);
1428 txc->ste_map = NULL;
1429 }
1430 }
1431 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag);
1432 sc->ste_cdata.ste_tx_tag = NULL;
1433 }
1434 /* Rx buffers. */
1435 if (sc->ste_cdata.ste_rx_tag != NULL) {
1436 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1437 rxc = &sc->ste_cdata.ste_rx_chain[i];
1438 if (rxc->ste_map != NULL) {
1439 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1440 rxc->ste_map);
1441 rxc->ste_map = NULL;
1442 }
1443 }
1444 if (sc->ste_cdata.ste_rx_sparemap != NULL) {
1445 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1446 sc->ste_cdata.ste_rx_sparemap);
1447 sc->ste_cdata.ste_rx_sparemap = NULL;
1448 }
1449 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag);
1450 sc->ste_cdata.ste_rx_tag = NULL;
1451 }
1452 /* Tx descriptor list. */
1453 if (sc->ste_cdata.ste_tx_list_tag != NULL) {
1454 if (sc->ste_cdata.ste_tx_list_map != NULL)
1455 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag,
1456 sc->ste_cdata.ste_tx_list_map);
1457 if (sc->ste_cdata.ste_tx_list_map != NULL &&
1458 sc->ste_ldata.ste_tx_list != NULL)
1459 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag,
1460 sc->ste_ldata.ste_tx_list,
1461 sc->ste_cdata.ste_tx_list_map);
1462 sc->ste_ldata.ste_tx_list = NULL;
1463 sc->ste_cdata.ste_tx_list_map = NULL;
1464 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag);
1465 sc->ste_cdata.ste_tx_list_tag = NULL;
1466 }
1467 /* Rx descriptor list. */
1468 if (sc->ste_cdata.ste_rx_list_tag != NULL) {
1469 if (sc->ste_cdata.ste_rx_list_map != NULL)
1470 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag,
1471 sc->ste_cdata.ste_rx_list_map);
1472 if (sc->ste_cdata.ste_rx_list_map != NULL &&
1473 sc->ste_ldata.ste_rx_list != NULL)
1474 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag,
1475 sc->ste_ldata.ste_rx_list,
1476 sc->ste_cdata.ste_rx_list_map);
1477 sc->ste_ldata.ste_rx_list = NULL;
1478 sc->ste_cdata.ste_rx_list_map = NULL;
1479 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag);
1480 sc->ste_cdata.ste_rx_list_tag = NULL;
1481 }
1482 if (sc->ste_cdata.ste_parent_tag != NULL) {
1483 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag);
1484 sc->ste_cdata.ste_parent_tag = NULL;
1485 }
1486}
1487
1488static int
1489ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc)
1490{
1491 struct mbuf *m;
1492 bus_dma_segment_t segs[1];
1493 bus_dmamap_t map;
1494 int error, nsegs;
1495
1496 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1497 if (m == NULL)
1498 return (ENOBUFS);
1499 m->m_len = m->m_pkthdr.len = MCLBYTES;
1500 m_adj(m, ETHER_ALIGN);
1501
1502 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag,
1503 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) {
1504 m_freem(m);
1505 return (error);
1506 }
1507 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1508
1509 if (rxc->ste_mbuf != NULL) {
1510 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1511 BUS_DMASYNC_POSTREAD);
1512 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map);
1513 }
1514 map = rxc->ste_map;
1515 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap;
1516 sc->ste_cdata.ste_rx_sparemap = map;
1517 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1518 BUS_DMASYNC_PREREAD);
1519 rxc->ste_mbuf = m;
1520 rxc->ste_ptr->ste_status = 0;
1521 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr);
1522 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len |
1523 STE_FRAG_LAST);
1524 return (0);
1525}
1526
1527static int
1528ste_init_rx_list(struct ste_softc *sc)
1529{
1530 struct ste_chain_data *cd;
1531 struct ste_list_data *ld;
1532 int error, i;
1533
1534 cd = &sc->ste_cdata;
1535 ld = &sc->ste_ldata;
1536 bzero(ld->ste_rx_list, STE_RX_LIST_SZ);
1537 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1538 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1539 error = ste_newbuf(sc, &cd->ste_rx_chain[i]);
1540 if (error != 0)
1541 return (error);
1542 if (i == (STE_RX_LIST_CNT - 1)) {
1543 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0];
1544 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr +
1545 (sizeof(struct ste_desc_onefrag) * 0);
1546 } else {
1547 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1];
1548 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr +
1549 (sizeof(struct ste_desc_onefrag) * (i + 1));
1550 }
1551 }
1552
1553 cd->ste_rx_head = &cd->ste_rx_chain[0];
1554 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
1555 sc->ste_cdata.ste_rx_list_map,
1556 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1557
1558 return (0);
1559}
1560
1561static void
1562ste_init_tx_list(struct ste_softc *sc)
1563{
1564 struct ste_chain_data *cd;
1565 struct ste_list_data *ld;
1566 int i;
1567
1568 cd = &sc->ste_cdata;
1569 ld = &sc->ste_ldata;
1570 bzero(ld->ste_tx_list, STE_TX_LIST_SZ);
1571 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1572 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1573 cd->ste_tx_chain[i].ste_mbuf = NULL;
1574 if (i == (STE_TX_LIST_CNT - 1)) {
1575 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0];
1576 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1577 ld->ste_tx_list_paddr +
1578 (sizeof(struct ste_desc) * 0)));
1579 } else {
1580 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1];
1581 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1582 ld->ste_tx_list_paddr +
1583 (sizeof(struct ste_desc) * (i + 1))));
1584 }
1585 }
1586
1587 cd->ste_last_tx = NULL;
1588 cd->ste_tx_prod = 0;
1589 cd->ste_tx_cons = 0;
1590 cd->ste_tx_cnt = 0;
1591
1592 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1593 sc->ste_cdata.ste_tx_list_map,
1594 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1595}
1596
1597static void
1598ste_init(void *xsc)
1599{
1600 struct ste_softc *sc;
1601
1602 sc = xsc;
1603 STE_LOCK(sc);
1604 ste_init_locked(sc);
1605 STE_UNLOCK(sc);
1606}
1607
1608static void
1609ste_init_locked(struct ste_softc *sc)
1610{
1611 struct ifnet *ifp;
1612 struct mii_data *mii;
1613 int i;
1614
1615 STE_LOCK_ASSERT(sc);
1616 ifp = sc->ste_ifp;
1617 mii = device_get_softc(sc->ste_miibus);
1618
1619 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1620 return;
1621
1622 ste_stop(sc);
1623 /* Reset the chip to a known state. */
1624 ste_reset(sc);
1625
1626 /* Init our MAC address */
1627 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1628 CSR_WRITE_2(sc, STE_PAR0 + i,
1629 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) |
1630 IF_LLADDR(sc->ste_ifp)[i + 1] << 8));
1631 }
1632
1633 /* Init RX list */
1634 if (ste_init_rx_list(sc) != 0) {
1635 device_printf(sc->ste_dev,
1636 "initialization failed: no memory for RX buffers\n");
1637 ste_stop(sc);
1638 return;
1639 }
1640
1641 /* Set RX polling interval */
1642 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1643
1644 /* Init TX descriptors */
1645 ste_init_tx_list(sc);
1646
1647 /* Set the TX freethresh value */
1648 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1649
1650 /* Set the TX start threshold for best performance. */
1651 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1652
1653 /* Set the TX reclaim threshold. */
1654 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1655
1656 /* Accept VLAN length packets */
1657 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1658
1659 /* Set up the RX filter. */
1660 ste_rxfilter(sc);
1661
1662 /* Load the address of the RX list. */
1663 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1664 ste_wait(sc);
1665 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1666 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr));
1667 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1668 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1669
1670 /* Set TX polling interval(defer until we TX first packet). */
1671 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1672
1673 /* Load address of the TX list */
1674 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1675 ste_wait(sc);
1676 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1677 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1678 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1679 ste_wait(sc);
1680
1681 /* Enable receiver and transmitter */
1682 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1683 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1684 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1685 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1686
1687 /* Enable stats counters. */
1688 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1689 /* Clear stats counters. */
1690 ste_stats_clear(sc);
1691
1692 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1693#ifdef DEVICE_POLLING
1694 /* Disable interrupts if we are polling. */
1695 if (ifp->if_capenable & IFCAP_POLLING)
1696 CSR_WRITE_2(sc, STE_IMR, 0);
1697 else
1698#endif
1699 /* Enable interrupts. */
1700 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1701
1702 sc->ste_flags &= ~STE_FLAG_LINK;
1703 /* Switch to the current media. */
1704 mii_mediachg(mii);
1705
1706 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1707 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1708
1709 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
1710}
1711
1712static void
1713ste_stop(struct ste_softc *sc)
1714{
1715 struct ifnet *ifp;
1716 struct ste_chain_onefrag *cur_rx;
1717 struct ste_chain *cur_tx;
1718 uint32_t val;
1719 int i;
1720
1721 STE_LOCK_ASSERT(sc);
1722 ifp = sc->ste_ifp;
1723
1724 callout_stop(&sc->ste_callout);
1725 sc->ste_timer = 0;
1726 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1727
1728 CSR_WRITE_2(sc, STE_IMR, 0);
1729 /* Stop pending DMA. */
1730 val = CSR_READ_4(sc, STE_DMACTL);
1731 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL;
1732 CSR_WRITE_4(sc, STE_DMACTL, val);
1733 ste_wait(sc);
1734 /* Disable auto-polling. */
1735 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0);
1736 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1737 /* Nullify DMA address to stop any further DMA. */
1738 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0);
1739 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1740 /* Stop TX/RX MAC. */
1741 val = CSR_READ_2(sc, STE_MACCTL1);
1742 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE |
1743 STE_MACCTL1_STATS_DISABLE;
1744 CSR_WRITE_2(sc, STE_MACCTL1, val);
1745 for (i = 0; i < STE_TIMEOUT; i++) {
1746 DELAY(10);
1747 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE |
1748 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0)
1749 break;
1750 }
1751 if (i == STE_TIMEOUT)
1752 device_printf(sc->ste_dev, "Stopping MAC timed out\n");
1753 /* Acknowledge any pending interrupts. */
1754 CSR_READ_2(sc, STE_ISR_ACK);
1755 ste_stats_update(sc);
1756
1757 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1758 cur_rx = &sc->ste_cdata.ste_rx_chain[i];
1759 if (cur_rx->ste_mbuf != NULL) {
1760 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag,
1761 cur_rx->ste_map, BUS_DMASYNC_POSTREAD);
1762 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag,
1763 cur_rx->ste_map);
1764 m_freem(cur_rx->ste_mbuf);
1765 cur_rx->ste_mbuf = NULL;
1766 }
1767 }
1768
1769 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1770 cur_tx = &sc->ste_cdata.ste_tx_chain[i];
1771 if (cur_tx->ste_mbuf != NULL) {
1772 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag,
1773 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE);
1774 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag,
1775 cur_tx->ste_map);
1776 m_freem(cur_tx->ste_mbuf);
1777 cur_tx->ste_mbuf = NULL;
1778 }
1779 }
1780}
1781
1782static void
1783ste_reset(struct ste_softc *sc)
1784{
1785 uint32_t ctl;
1786 int i;
1787
1788 ctl = CSR_READ_4(sc, STE_ASICCTL);
1789 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET |
1790 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET |
1791 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET |
1792 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET |
1793 STE_ASICCTL_EXTRESET_RESET;
1794 CSR_WRITE_4(sc, STE_ASICCTL, ctl);
1795 CSR_READ_4(sc, STE_ASICCTL);
1796 /*
1797 * Due to the need of accessing EEPROM controller can take
1798 * up to 1ms to complete the global reset.
1799 */
1800 DELAY(1000);
1801
1802 for (i = 0; i < STE_TIMEOUT; i++) {
1803 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1804 break;
1805 DELAY(10);
1806 }
1807
1808 if (i == STE_TIMEOUT)
1809 device_printf(sc->ste_dev, "global reset never completed\n");
1810}
1811
1812static void
1813ste_restart_tx(struct ste_softc *sc)
1814{
1815 uint16_t mac;
1816 int i;
1817
1818 for (i = 0; i < STE_TIMEOUT; i++) {
1819 mac = CSR_READ_2(sc, STE_MACCTL1);
1820 mac |= STE_MACCTL1_TX_ENABLE;
1821 CSR_WRITE_2(sc, STE_MACCTL1, mac);
1822 mac = CSR_READ_2(sc, STE_MACCTL1);
1823 if ((mac & STE_MACCTL1_TX_ENABLED) != 0)
1824 break;
1825 DELAY(10);
1826 }
1827
1828 if (i == STE_TIMEOUT)
1829 device_printf(sc->ste_dev, "starting Tx failed");
1830}
1831
1832static int
1833ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1834{
1835 struct ste_softc *sc;
1836 struct ifreq *ifr;
1837 struct mii_data *mii;
1838 int error = 0;
1839
1840 sc = ifp->if_softc;
1841 ifr = (struct ifreq *)data;
1842
1843 switch (command) {
1844 case SIOCSIFFLAGS:
1845 STE_LOCK(sc);
1846 if ((ifp->if_flags & IFF_UP) != 0) {
1847 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1848 ((ifp->if_flags ^ sc->ste_if_flags) &
1849 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1850 ste_rxfilter(sc);
1851 else
1852 ste_init_locked(sc);
1853 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1854 ste_stop(sc);
1855 sc->ste_if_flags = ifp->if_flags;
1856 STE_UNLOCK(sc);
1857 break;
1858 case SIOCADDMULTI:
1859 case SIOCDELMULTI:
1860 STE_LOCK(sc);
1861 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1862 ste_rxfilter(sc);
1863 STE_UNLOCK(sc);
1864 break;
1865 case SIOCGIFMEDIA:
1866 case SIOCSIFMEDIA:
1867 mii = device_get_softc(sc->ste_miibus);
1868 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1869 break;
1870 case SIOCSIFCAP:
1871#ifdef DEVICE_POLLING
1872 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1873 !(ifp->if_capenable & IFCAP_POLLING)) {
1874 error = ether_poll_register(ste_poll, ifp);
1875 if (error)
1876 return (error);
1877 STE_LOCK(sc);
1878 /* Disable interrupts */
1879 CSR_WRITE_2(sc, STE_IMR, 0);
1880 ifp->if_capenable |= IFCAP_POLLING;
1881 STE_UNLOCK(sc);
1882 return (error);
1883
1884 }
1885 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1886 ifp->if_capenable & IFCAP_POLLING) {
1887 error = ether_poll_deregister(ifp);
1888 /* Enable interrupts. */
1889 STE_LOCK(sc);
1890 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1891 ifp->if_capenable &= ~IFCAP_POLLING;
1892 STE_UNLOCK(sc);
1893 return (error);
1894 }
1895#endif /* DEVICE_POLLING */
1896 break;
1897 default:
1898 error = ether_ioctl(ifp, command, data);
1899 break;
1900 }
1901
1902 return (error);
1903}
1904
1905static int
1906ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc)
1907{
1908 struct ste_frag *frag;
1909 struct mbuf *m;
1910 struct ste_desc *desc;
1911 bus_dma_segment_t txsegs[STE_MAXFRAGS];
1912 int error, i, nsegs;
1913
1914 STE_LOCK_ASSERT(sc);
1915 M_ASSERTPKTHDR((*m_head));
1916
1917 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1918 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1919 if (error == EFBIG) {
1920 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS);
1921 if (m == NULL) {
1922 m_freem(*m_head);
1923 *m_head = NULL;
1924 return (ENOMEM);
1925 }
1926 *m_head = m;
1927 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1928 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1929 if (error != 0) {
1930 m_freem(*m_head);
1931 *m_head = NULL;
1932 return (error);
1933 }
1934 } else if (error != 0)
1935 return (error);
1936 if (nsegs == 0) {
1937 m_freem(*m_head);
1938 *m_head = NULL;
1939 return (EIO);
1940 }
1941 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map,
1942 BUS_DMASYNC_PREWRITE);
1943
1944 desc = txc->ste_ptr;
1945 for (i = 0; i < nsegs; i++) {
1946 frag = &desc->ste_frags[i];
1947 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr));
1948 frag->ste_len = htole32(txsegs[i].ds_len);
1949 }
1950 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST);
1951 /*
1952 * Because we use Tx polling we can't chain multiple
1953 * Tx descriptors here. Otherwise we race with controller.
1954 */
1955 desc->ste_next = 0;
1956 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | STE_TXCTL_DMAINTR);
1957 txc->ste_mbuf = *m_head;
1958 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT);
1959 sc->ste_cdata.ste_tx_cnt++;
1960
1961 return (0);
1962}
1963
1964static void
1965ste_start(struct ifnet *ifp)
1966{
1967 struct ste_softc *sc;
1968
1969 sc = ifp->if_softc;
1970 STE_LOCK(sc);
1971 ste_start_locked(ifp);
1972 STE_UNLOCK(sc);
1973}
1974
1975static void
1976ste_start_locked(struct ifnet *ifp)
1977{
1978 struct ste_softc *sc;
1979 struct ste_chain *cur_tx;
1980 struct mbuf *m_head = NULL;
1981 int enq;
1982
1983 sc = ifp->if_softc;
1984 STE_LOCK_ASSERT(sc);
1985
1986 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1987 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0)
1988 return;
1989
1990 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
1991 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) {
1992 /*
1993 * Controller may have cached copy of the last used
1994 * next ptr so we have to reserve one TFD to avoid
1995 * TFD overruns.
1996 */
1997 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1998 break;
1999 }
2000 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2001 if (m_head == NULL)
2002 break;
2003 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod];
2004 if (ste_encap(sc, &m_head, cur_tx) != 0) {
2005 if (m_head == NULL)
2006 break;
2007 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2008 break;
2009 }
2010 if (sc->ste_cdata.ste_last_tx == NULL) {
2011 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
2012 sc->ste_cdata.ste_tx_list_map,
2013 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2014 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
2015 ste_wait(sc);
2016 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
2017 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr));
2018 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
2019 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
2020 ste_wait(sc);
2021 } else {
2022 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next =
2023 sc->ste_cdata.ste_last_tx->ste_phys;
2024 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
2025 sc->ste_cdata.ste_tx_list_map,
2026 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2027 }
2028 sc->ste_cdata.ste_last_tx = cur_tx;
2029
2030 enq++;
2031 /*
2032 * If there's a BPF listener, bounce a copy of this frame
2033 * to him.
2034 */
2035 BPF_MTAP(ifp, m_head);
2036 }
2037
2038 if (enq > 0)
2039 sc->ste_timer = STE_TX_TIMEOUT;
2040}
2041
2042static void
2043ste_watchdog(struct ste_softc *sc)
2044{
2045 struct ifnet *ifp;
2046
2047 ifp = sc->ste_ifp;
2048 STE_LOCK_ASSERT(sc);
2049
2050 if (sc->ste_timer == 0 || --sc->ste_timer)
2051 return;
2052
2053 ifp->if_oerrors++;
2054 if_printf(ifp, "watchdog timeout\n");
2055
2056 ste_txeof(sc);
2057 ste_txeoc(sc);
2058 ste_rxeof(sc, -1);
2059 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2060 ste_init_locked(sc);
2061
2062 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2063 ste_start_locked(ifp);
2064}
2065
2066static int
2067ste_shutdown(device_t dev)
2068{
2069 struct ste_softc *sc;
2070
2071 sc = device_get_softc(dev);
2072
2073 STE_LOCK(sc);
2074 ste_stop(sc);
2075 STE_UNLOCK(sc);
2076
2077 return (0);
2078}
2079
2080#define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
2081 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
2082#define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
2083 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
2084
2085static void
2086ste_sysctl_node(struct ste_softc *sc)
2087{
2088 struct sysctl_ctx_list *ctx;
2089 struct sysctl_oid_list *child, *parent;
2090 struct sysctl_oid *tree;
2091 struct ste_hw_stats *stats;
2092
2093 stats = &sc->ste_stats;
2094 ctx = device_get_sysctl_ctx(sc->ste_dev);
2095 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev));
2096
2097 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
2098 NULL, "STE statistics");
2099 parent = SYSCTL_CHILDREN(tree);
2100
2101 /* Rx statistics. */
2102 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
2103 NULL, "Rx MAC statistics");
2104 child = SYSCTL_CHILDREN(tree);
2105 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2106 &stats->rx_bytes, "Good octets");
2107 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2108 &stats->rx_frames, "Good frames");
2109 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2110 &stats->rx_bcast_frames, "Good broadcast frames");
2111 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2112 &stats->rx_mcast_frames, "Good multicast frames");
2113 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames",
2114 &stats->rx_lost_frames, "Lost frames");
2115
2116 /* Tx statistics. */
2117 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
2118 NULL, "Tx MAC statistics");
2119 child = SYSCTL_CHILDREN(tree);
2120 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2121 &stats->tx_bytes, "Good octets");
2122 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2123 &stats->tx_frames, "Good frames");
2124 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2125 &stats->tx_bcast_frames, "Good broadcast frames");
2126 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2127 &stats->tx_mcast_frames, "Good multicast frames");
2128 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs",
2129 &stats->tx_carrsense_errs, "Carrier sense errors");
2130 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
2131 &stats->tx_single_colls, "Single collisions");
2132 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
2133 &stats->tx_multi_colls, "Multiple collisions");
2134 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
2135 &stats->tx_late_colls, "Late collisions");
2136 STE_SYSCTL_STAT_ADD32(ctx, child, "defers",
2137 &stats->tx_frames_defered, "Frames with deferrals");
2138 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
2139 &stats->tx_excess_defers, "Frames with excessive derferrals");
2140 STE_SYSCTL_STAT_ADD32(ctx, child, "abort",
2141 &stats->tx_abort, "Aborted frames due to Excessive collisions");
2142}
2143
2144#undef STE_SYSCTL_STAT_ADD32
2145#undef STE_SYSCTL_STAT_ADD64
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200910 2009-12-23 19:18:07Z yongari $");
35
36#ifdef HAVE_KERNEL_OPTION_HEADERS
37#include "opt_device_polling.h"
38#endif
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/bus.h>
43#include <sys/endian.h>
44#include <sys/kernel.h>
45#include <sys/lock.h>
46#include <sys/malloc.h>
47#include <sys/mbuf.h>
48#include <sys/module.h>
49#include <sys/rman.h>
50#include <sys/socket.h>
51#include <sys/sockio.h>
52#include <sys/sysctl.h>
53
54#include <net/bpf.h>
55#include <net/if.h>
56#include <net/if_arp.h>
57#include <net/ethernet.h>
58#include <net/if_dl.h>
59#include <net/if_media.h>
60#include <net/if_types.h>
61#include <net/if_vlan_var.h>
62
63#include <machine/bus.h>
64#include <machine/resource.h>
65
66#include <dev/mii/mii.h>
67#include <dev/mii/miivar.h>
68
69#include <dev/pci/pcireg.h>
70#include <dev/pci/pcivar.h>
71
72#include <dev/ste/if_stereg.h>
73
74/* "device miibus" required. See GENERIC if you get errors here. */
75#include "miibus_if.h"
76
77MODULE_DEPEND(ste, pci, 1, 1, 1);
78MODULE_DEPEND(ste, ether, 1, 1, 1);
79MODULE_DEPEND(ste, miibus, 1, 1, 1);
80
81/* Define to show Tx error status. */
82#define STE_SHOW_TXERRORS
83
84/*
85 * Various supported device vendors/types and their names.
86 */
87static struct ste_type ste_devs[] = {
88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" },
89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" },
90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
91 { 0, 0, NULL }
92};
93
94static int ste_attach(device_t);
95static int ste_detach(device_t);
96static int ste_probe(device_t);
97static int ste_shutdown(device_t);
98
99static int ste_dma_alloc(struct ste_softc *);
100static void ste_dma_free(struct ste_softc *);
101static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int);
102static int ste_eeprom_wait(struct ste_softc *);
103static int ste_encap(struct ste_softc *, struct mbuf **,
104 struct ste_chain *);
105static int ste_ifmedia_upd(struct ifnet *);
106static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
107static void ste_init(void *);
108static void ste_init_locked(struct ste_softc *);
109static int ste_init_rx_list(struct ste_softc *);
110static void ste_init_tx_list(struct ste_softc *);
111static void ste_intr(void *);
112static int ste_ioctl(struct ifnet *, u_long, caddr_t);
113static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *);
114static void ste_mii_send(struct ste_softc *, uint32_t, int);
115static void ste_mii_sync(struct ste_softc *);
116static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *);
117static int ste_miibus_readreg(device_t, int, int);
118static void ste_miibus_statchg(device_t);
119static int ste_miibus_writereg(device_t, int, int, int);
120static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *);
121static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int);
122static void ste_reset(struct ste_softc *);
123static void ste_restart_tx(struct ste_softc *);
124static int ste_rxeof(struct ste_softc *, int);
125static void ste_rxfilter(struct ste_softc *);
126static void ste_start(struct ifnet *);
127static void ste_start_locked(struct ifnet *);
128static void ste_stats_clear(struct ste_softc *);
129static void ste_stats_update(struct ste_softc *);
130static void ste_stop(struct ste_softc *);
131static void ste_sysctl_node(struct ste_softc *);
132static void ste_tick(void *);
133static void ste_txeoc(struct ste_softc *);
134static void ste_txeof(struct ste_softc *);
135static void ste_wait(struct ste_softc *);
136static void ste_watchdog(struct ste_softc *);
137
138static device_method_t ste_methods[] = {
139 /* Device interface */
140 DEVMETHOD(device_probe, ste_probe),
141 DEVMETHOD(device_attach, ste_attach),
142 DEVMETHOD(device_detach, ste_detach),
143 DEVMETHOD(device_shutdown, ste_shutdown),
144
145 /* bus interface */
146 DEVMETHOD(bus_print_child, bus_generic_print_child),
147 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
148
149 /* MII interface */
150 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
151 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
152 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
153
154 { 0, 0 }
155};
156
157static driver_t ste_driver = {
158 "ste",
159 ste_methods,
160 sizeof(struct ste_softc)
161};
162
163static devclass_t ste_devclass;
164
165DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
166DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
167
168#define STE_SETBIT4(sc, reg, x) \
169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
170
171#define STE_CLRBIT4(sc, reg, x) \
172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
173
174#define STE_SETBIT2(sc, reg, x) \
175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
176
177#define STE_CLRBIT2(sc, reg, x) \
178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
179
180#define STE_SETBIT1(sc, reg, x) \
181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
182
183#define STE_CLRBIT1(sc, reg, x) \
184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
185
186
187#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
188#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
189
190/*
191 * Sync the PHYs by setting data bit and strobing the clock 32 times.
192 */
193static void
194ste_mii_sync(struct ste_softc *sc)
195{
196 int i;
197
198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
199
200 for (i = 0; i < 32; i++) {
201 MII_SET(STE_PHYCTL_MCLK);
202 DELAY(1);
203 MII_CLR(STE_PHYCTL_MCLK);
204 DELAY(1);
205 }
206}
207
208/*
209 * Clock a series of bits through the MII.
210 */
211static void
212ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt)
213{
214 int i;
215
216 MII_CLR(STE_PHYCTL_MCLK);
217
218 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
219 if (bits & i) {
220 MII_SET(STE_PHYCTL_MDATA);
221 } else {
222 MII_CLR(STE_PHYCTL_MDATA);
223 }
224 DELAY(1);
225 MII_CLR(STE_PHYCTL_MCLK);
226 DELAY(1);
227 MII_SET(STE_PHYCTL_MCLK);
228 }
229}
230
231/*
232 * Read an PHY register through the MII.
233 */
234static int
235ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame)
236{
237 int i, ack;
238
239 /*
240 * Set up frame for RX.
241 */
242 frame->mii_stdelim = STE_MII_STARTDELIM;
243 frame->mii_opcode = STE_MII_READOP;
244 frame->mii_turnaround = 0;
245 frame->mii_data = 0;
246
247 CSR_WRITE_2(sc, STE_PHYCTL, 0);
248 /*
249 * Turn on data xmit.
250 */
251 MII_SET(STE_PHYCTL_MDIR);
252
253 ste_mii_sync(sc);
254
255 /*
256 * Send command/address info.
257 */
258 ste_mii_send(sc, frame->mii_stdelim, 2);
259 ste_mii_send(sc, frame->mii_opcode, 2);
260 ste_mii_send(sc, frame->mii_phyaddr, 5);
261 ste_mii_send(sc, frame->mii_regaddr, 5);
262
263 /* Turn off xmit. */
264 MII_CLR(STE_PHYCTL_MDIR);
265
266 /* Idle bit */
267 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
268 DELAY(1);
269 MII_SET(STE_PHYCTL_MCLK);
270 DELAY(1);
271
272 /* Check for ack */
273 MII_CLR(STE_PHYCTL_MCLK);
274 DELAY(1);
275 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
276 MII_SET(STE_PHYCTL_MCLK);
277 DELAY(1);
278
279 /*
280 * Now try reading data bits. If the ack failed, we still
281 * need to clock through 16 cycles to keep the PHY(s) in sync.
282 */
283 if (ack) {
284 for (i = 0; i < 16; i++) {
285 MII_CLR(STE_PHYCTL_MCLK);
286 DELAY(1);
287 MII_SET(STE_PHYCTL_MCLK);
288 DELAY(1);
289 }
290 goto fail;
291 }
292
293 for (i = 0x8000; i; i >>= 1) {
294 MII_CLR(STE_PHYCTL_MCLK);
295 DELAY(1);
296 if (!ack) {
297 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
298 frame->mii_data |= i;
299 DELAY(1);
300 }
301 MII_SET(STE_PHYCTL_MCLK);
302 DELAY(1);
303 }
304
305fail:
306
307 MII_CLR(STE_PHYCTL_MCLK);
308 DELAY(1);
309 MII_SET(STE_PHYCTL_MCLK);
310 DELAY(1);
311
312 if (ack)
313 return (1);
314 return (0);
315}
316
317/*
318 * Write to a PHY register through the MII.
319 */
320static int
321ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame)
322{
323
324 /*
325 * Set up frame for TX.
326 */
327
328 frame->mii_stdelim = STE_MII_STARTDELIM;
329 frame->mii_opcode = STE_MII_WRITEOP;
330 frame->mii_turnaround = STE_MII_TURNAROUND;
331
332 /*
333 * Turn on data output.
334 */
335 MII_SET(STE_PHYCTL_MDIR);
336
337 ste_mii_sync(sc);
338
339 ste_mii_send(sc, frame->mii_stdelim, 2);
340 ste_mii_send(sc, frame->mii_opcode, 2);
341 ste_mii_send(sc, frame->mii_phyaddr, 5);
342 ste_mii_send(sc, frame->mii_regaddr, 5);
343 ste_mii_send(sc, frame->mii_turnaround, 2);
344 ste_mii_send(sc, frame->mii_data, 16);
345
346 /* Idle bit. */
347 MII_SET(STE_PHYCTL_MCLK);
348 DELAY(1);
349 MII_CLR(STE_PHYCTL_MCLK);
350 DELAY(1);
351
352 /*
353 * Turn off xmit.
354 */
355 MII_CLR(STE_PHYCTL_MDIR);
356
357 return (0);
358}
359
360static int
361ste_miibus_readreg(device_t dev, int phy, int reg)
362{
363 struct ste_softc *sc;
364 struct ste_mii_frame frame;
365
366 sc = device_get_softc(dev);
367
368 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0)
369 return (0);
370
371 bzero((char *)&frame, sizeof(frame));
372
373 frame.mii_phyaddr = phy;
374 frame.mii_regaddr = reg;
375 ste_mii_readreg(sc, &frame);
376
377 return (frame.mii_data);
378}
379
380static int
381ste_miibus_writereg(device_t dev, int phy, int reg, int data)
382{
383 struct ste_softc *sc;
384 struct ste_mii_frame frame;
385
386 sc = device_get_softc(dev);
387 bzero((char *)&frame, sizeof(frame));
388
389 frame.mii_phyaddr = phy;
390 frame.mii_regaddr = reg;
391 frame.mii_data = data;
392
393 ste_mii_writereg(sc, &frame);
394
395 return (0);
396}
397
398static void
399ste_miibus_statchg(device_t dev)
400{
401 struct ste_softc *sc;
402 struct mii_data *mii;
403 struct ifnet *ifp;
404 uint16_t cfg;
405
406 sc = device_get_softc(dev);
407
408 mii = device_get_softc(sc->ste_miibus);
409 ifp = sc->ste_ifp;
410 if (mii == NULL || ifp == NULL ||
411 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
412 return;
413
414 sc->ste_flags &= ~STE_FLAG_LINK;
415 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
416 (IFM_ACTIVE | IFM_AVALID)) {
417 switch (IFM_SUBTYPE(mii->mii_media_active)) {
418 case IFM_10_T:
419 case IFM_100_TX:
420 case IFM_100_FX:
421 case IFM_100_T4:
422 sc->ste_flags |= STE_FLAG_LINK;
423 default:
424 break;
425 }
426 }
427
428 /* Program MACs with resolved speed/duplex/flow-control. */
429 if ((sc->ste_flags & STE_FLAG_LINK) != 0) {
430 cfg = CSR_READ_2(sc, STE_MACCTL0);
431 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX);
432 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
433 /*
434 * ST201 data sheet says driver should enable receiving
435 * MAC control frames bit of receive mode register to
436 * receive flow-control frames but the register has no
437 * such bits. In addition the controller has no ability
438 * to send pause frames so it should be handled in
439 * driver. Implementing pause timer handling in driver
440 * layer is not trivial, so don't enable flow-control
441 * here.
442 */
443 cfg |= STE_MACCTL0_FULLDUPLEX;
444 }
445 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
446 }
447}
448
449static int
450ste_ifmedia_upd(struct ifnet *ifp)
451{
452 struct ste_softc *sc;
453 struct mii_data *mii;
454 struct mii_softc *miisc;
455 int error;
456
457 sc = ifp->if_softc;
458 STE_LOCK(sc);
459 mii = device_get_softc(sc->ste_miibus);
460 if (mii->mii_instance) {
461 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
462 mii_phy_reset(miisc);
463 }
464 error = mii_mediachg(mii);
465 STE_UNLOCK(sc);
466
467 return (error);
468}
469
470static void
471ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
472{
473 struct ste_softc *sc;
474 struct mii_data *mii;
475
476 sc = ifp->if_softc;
477 mii = device_get_softc(sc->ste_miibus);
478
479 STE_LOCK(sc);
480 if ((ifp->if_flags & IFF_UP) == 0) {
481 STE_UNLOCK(sc);
482 return;
483 }
484 mii_pollstat(mii);
485 ifmr->ifm_active = mii->mii_media_active;
486 ifmr->ifm_status = mii->mii_media_status;
487 STE_UNLOCK(sc);
488}
489
490static void
491ste_wait(struct ste_softc *sc)
492{
493 int i;
494
495 for (i = 0; i < STE_TIMEOUT; i++) {
496 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
497 break;
498 DELAY(1);
499 }
500
501 if (i == STE_TIMEOUT)
502 device_printf(sc->ste_dev, "command never completed!\n");
503}
504
505/*
506 * The EEPROM is slow: give it time to come ready after issuing
507 * it a command.
508 */
509static int
510ste_eeprom_wait(struct ste_softc *sc)
511{
512 int i;
513
514 DELAY(1000);
515
516 for (i = 0; i < 100; i++) {
517 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
518 DELAY(1000);
519 else
520 break;
521 }
522
523 if (i == 100) {
524 device_printf(sc->ste_dev, "eeprom failed to come ready\n");
525 return (1);
526 }
527
528 return (0);
529}
530
531/*
532 * Read a sequence of words from the EEPROM. Note that ethernet address
533 * data is stored in the EEPROM in network byte order.
534 */
535static int
536ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap)
537{
538 uint16_t word, *ptr;
539 int err = 0, i;
540
541 if (ste_eeprom_wait(sc))
542 return (1);
543
544 for (i = 0; i < cnt; i++) {
545 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
546 err = ste_eeprom_wait(sc);
547 if (err)
548 break;
549 word = CSR_READ_2(sc, STE_EEPROM_DATA);
550 ptr = (uint16_t *)(dest + (i * 2));
551 if (swap)
552 *ptr = ntohs(word);
553 else
554 *ptr = word;
555 }
556
557 return (err ? 1 : 0);
558}
559
560static void
561ste_rxfilter(struct ste_softc *sc)
562{
563 struct ifnet *ifp;
564 struct ifmultiaddr *ifma;
565 uint32_t hashes[2] = { 0, 0 };
566 uint8_t rxcfg;
567 int h;
568
569 STE_LOCK_ASSERT(sc);
570
571 ifp = sc->ste_ifp;
572 rxcfg = CSR_READ_1(sc, STE_RX_MODE);
573 rxcfg |= STE_RXMODE_UNICAST;
574 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH |
575 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC);
576 if (ifp->if_flags & IFF_BROADCAST)
577 rxcfg |= STE_RXMODE_BROADCAST;
578 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
579 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
580 rxcfg |= STE_RXMODE_ALLMULTI;
581 if ((ifp->if_flags & IFF_PROMISC) != 0)
582 rxcfg |= STE_RXMODE_PROMISC;
583 goto chipit;
584 }
585
586 rxcfg |= STE_RXMODE_MULTIHASH;
587 /* Now program new ones. */
588 if_maddr_rlock(ifp);
589 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
590 if (ifma->ifma_addr->sa_family != AF_LINK)
591 continue;
592 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
593 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F;
594 if (h < 32)
595 hashes[0] |= (1 << h);
596 else
597 hashes[1] |= (1 << (h - 32));
598 }
599 if_maddr_runlock(ifp);
600
601chipit:
602 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
603 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
604 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
605 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
606 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
607 CSR_READ_1(sc, STE_RX_MODE);
608}
609
610#ifdef DEVICE_POLLING
611static poll_handler_t ste_poll, ste_poll_locked;
612
613static int
614ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
615{
616 struct ste_softc *sc = ifp->if_softc;
617 int rx_npkts = 0;
618
619 STE_LOCK(sc);
620 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
621 rx_npkts = ste_poll_locked(ifp, cmd, count);
622 STE_UNLOCK(sc);
623 return (rx_npkts);
624}
625
626static int
627ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
628{
629 struct ste_softc *sc = ifp->if_softc;
630 int rx_npkts;
631
632 STE_LOCK_ASSERT(sc);
633
634 rx_npkts = ste_rxeof(sc, count);
635 ste_txeof(sc);
636 ste_txeoc(sc);
637 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
638 ste_start_locked(ifp);
639
640 if (cmd == POLL_AND_CHECK_STATUS) {
641 uint16_t status;
642
643 status = CSR_READ_2(sc, STE_ISR_ACK);
644
645 if (status & STE_ISR_STATS_OFLOW)
646 ste_stats_update(sc);
647
648 if (status & STE_ISR_HOSTERR) {
649 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
650 ste_init_locked(sc);
651 }
652 }
653 return (rx_npkts);
654}
655#endif /* DEVICE_POLLING */
656
657static void
658ste_intr(void *xsc)
659{
660 struct ste_softc *sc;
661 struct ifnet *ifp;
662 uint16_t status;
663
664 sc = xsc;
665 STE_LOCK(sc);
666 ifp = sc->ste_ifp;
667
668#ifdef DEVICE_POLLING
669 if (ifp->if_capenable & IFCAP_POLLING) {
670 STE_UNLOCK(sc);
671 return;
672 }
673#endif
674
675 /* See if this is really our interrupt. */
676 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) {
677 STE_UNLOCK(sc);
678 return;
679 }
680
681 for (;;) {
682 status = CSR_READ_2(sc, STE_ISR_ACK);
683
684 if (!(status & STE_INTRS))
685 break;
686
687 if (status & STE_ISR_RX_DMADONE)
688 ste_rxeof(sc, -1);
689
690 if (status & STE_ISR_TX_DMADONE)
691 ste_txeof(sc);
692
693 if (status & STE_ISR_TX_DONE)
694 ste_txeoc(sc);
695
696 if (status & STE_ISR_STATS_OFLOW)
697 ste_stats_update(sc);
698
699 if (status & STE_ISR_HOSTERR) {
700 ste_init_locked(sc);
701 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
702 }
703 }
704
705 /* Re-enable interrupts */
706 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
707
708 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
709 ste_start_locked(ifp);
710
711 STE_UNLOCK(sc);
712}
713
714/*
715 * A frame has been uploaded: pass the resulting mbuf chain up to
716 * the higher level protocols.
717 */
718static int
719ste_rxeof(struct ste_softc *sc, int count)
720{
721 struct mbuf *m;
722 struct ifnet *ifp;
723 struct ste_chain_onefrag *cur_rx;
724 uint32_t rxstat;
725 int total_len, rx_npkts;
726
727 ifp = sc->ste_ifp;
728
729 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
730 sc->ste_cdata.ste_rx_list_map,
731 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
732
733 cur_rx = sc->ste_cdata.ste_rx_head;
734 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++,
735 cur_rx = cur_rx->ste_next) {
736 rxstat = le32toh(cur_rx->ste_ptr->ste_status);
737 if ((rxstat & STE_RXSTAT_DMADONE) == 0)
738 break;
739#ifdef DEVICE_POLLING
740 if (ifp->if_capenable & IFCAP_POLLING) {
741 if (count == 0)
742 break;
743 count--;
744 }
745#endif
746 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
747 break;
748 /*
749 * If an error occurs, update stats, clear the
750 * status word and leave the mbuf cluster in place:
751 * it should simply get re-used next time this descriptor
752 * comes up in the ring.
753 */
754 if (rxstat & STE_RXSTAT_FRAME_ERR) {
755 ifp->if_ierrors++;
756 cur_rx->ste_ptr->ste_status = 0;
757 continue;
758 }
759
760 /* No errors; receive the packet. */
761 m = cur_rx->ste_mbuf;
762 total_len = STE_RX_BYTES(rxstat);
763
764 /*
765 * Try to conjure up a new mbuf cluster. If that
766 * fails, it means we have an out of memory condition and
767 * should leave the buffer in place and continue. This will
768 * result in a lost packet, but there's little else we
769 * can do in this situation.
770 */
771 if (ste_newbuf(sc, cur_rx) != 0) {
772 ifp->if_ierrors++;
773 cur_rx->ste_ptr->ste_status = 0;
774 continue;
775 }
776
777 m->m_pkthdr.rcvif = ifp;
778 m->m_pkthdr.len = m->m_len = total_len;
779
780 ifp->if_ipackets++;
781 STE_UNLOCK(sc);
782 (*ifp->if_input)(ifp, m);
783 STE_LOCK(sc);
784 }
785
786 if (rx_npkts > 0) {
787 sc->ste_cdata.ste_rx_head = cur_rx;
788 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
789 sc->ste_cdata.ste_rx_list_map,
790 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
791 }
792
793 return (rx_npkts);
794}
795
796static void
797ste_txeoc(struct ste_softc *sc)
798{
799 uint16_t txstat;
800 struct ifnet *ifp;
801
802 STE_LOCK_ASSERT(sc);
803
804 ifp = sc->ste_ifp;
805
806 /*
807 * STE_TX_STATUS register implements a queue of up to 31
808 * transmit status byte. Writing an arbitrary value to the
809 * register will advance the queue to the next transmit
810 * status byte. This means if driver does not read
811 * STE_TX_STATUS register after completing sending more
812 * than 31 frames the controller would be stalled so driver
813 * should re-wake the Tx MAC. This is the most severe
814 * limitation of ST201 based controller.
815 */
816 for (;;) {
817 txstat = CSR_READ_2(sc, STE_TX_STATUS);
818 if ((txstat & STE_TXSTATUS_TXDONE) == 0)
819 break;
820 if ((txstat & (STE_TXSTATUS_UNDERRUN |
821 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR |
822 STE_TXSTATUS_STATSOFLOW)) != 0) {
823 ifp->if_oerrors++;
824#ifdef STE_SHOW_TXERRORS
825 device_printf(sc->ste_dev, "TX error : 0x%b\n",
826 txstat & 0xFF, STE_ERR_BITS);
827#endif
828 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 &&
829 sc->ste_tx_thresh < STE_PACKET_SIZE) {
830 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
831 if (sc->ste_tx_thresh > STE_PACKET_SIZE)
832 sc->ste_tx_thresh = STE_PACKET_SIZE;
833 device_printf(sc->ste_dev,
834 "TX underrun, increasing TX"
835 " start threshold to %d bytes\n",
836 sc->ste_tx_thresh);
837 /* Make sure to disable active DMA cycles. */
838 STE_SETBIT4(sc, STE_DMACTL,
839 STE_DMACTL_TXDMA_STALL);
840 ste_wait(sc);
841 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
842 ste_init_locked(sc);
843 break;
844 }
845 /* Restart Tx. */
846 ste_restart_tx(sc);
847 }
848 /*
849 * Advance to next status and ACK TxComplete
850 * interrupt. ST201 data sheet was wrong here, to
851 * get next Tx status, we have to write both
852 * STE_TX_STATUS and STE_TX_FRAMEID register.
853 * Otherwise controller returns the same status
854 * as well as not acknowledge Tx completion
855 * interrupt.
856 */
857 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
858 }
859}
860
861static void
862ste_tick(void *arg)
863{
864 struct ste_softc *sc;
865 struct mii_data *mii;
866
867 sc = (struct ste_softc *)arg;
868
869 STE_LOCK_ASSERT(sc);
870
871 mii = device_get_softc(sc->ste_miibus);
872 mii_tick(mii);
873 /*
874 * ukphy(4) does not seem to generate CB that reports
875 * resolved link state so if we know we lost a link,
876 * explicitly check the link state.
877 */
878 if ((sc->ste_flags & STE_FLAG_LINK) == 0)
879 ste_miibus_statchg(sc->ste_dev);
880 ste_stats_update(sc);
881 ste_watchdog(sc);
882 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
883}
884
885static void
886ste_txeof(struct ste_softc *sc)
887{
888 struct ifnet *ifp;
889 struct ste_chain *cur_tx;
890 uint32_t txstat;
891 int idx;
892
893 STE_LOCK_ASSERT(sc);
894
895 ifp = sc->ste_ifp;
896 idx = sc->ste_cdata.ste_tx_cons;
897 if (idx == sc->ste_cdata.ste_tx_prod)
898 return;
899
900 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
901 sc->ste_cdata.ste_tx_list_map,
902 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
903
904 while (idx != sc->ste_cdata.ste_tx_prod) {
905 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
906 txstat = le32toh(cur_tx->ste_ptr->ste_ctl);
907 if ((txstat & STE_TXCTL_DMADONE) == 0)
908 break;
909 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map,
910 BUS_DMASYNC_POSTWRITE);
911 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map);
912 KASSERT(cur_tx->ste_mbuf != NULL,
913 ("%s: freeing NULL mbuf!\n", __func__));
914 m_freem(cur_tx->ste_mbuf);
915 cur_tx->ste_mbuf = NULL;
916 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
917 ifp->if_opackets++;
918 sc->ste_cdata.ste_tx_cnt--;
919 STE_INC(idx, STE_TX_LIST_CNT);
920 }
921
922 sc->ste_cdata.ste_tx_cons = idx;
923 if (sc->ste_cdata.ste_tx_cnt == 0)
924 sc->ste_timer = 0;
925}
926
927static void
928ste_stats_clear(struct ste_softc *sc)
929{
930
931 STE_LOCK_ASSERT(sc);
932
933 /* Rx stats. */
934 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO);
935 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI);
936 CSR_READ_2(sc, STE_STAT_RX_FRAMES);
937 CSR_READ_1(sc, STE_STAT_RX_BCAST);
938 CSR_READ_1(sc, STE_STAT_RX_MCAST);
939 CSR_READ_1(sc, STE_STAT_RX_LOST);
940 /* Tx stats. */
941 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO);
942 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI);
943 CSR_READ_2(sc, STE_STAT_TX_FRAMES);
944 CSR_READ_1(sc, STE_STAT_TX_BCAST);
945 CSR_READ_1(sc, STE_STAT_TX_MCAST);
946 CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
947 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
948 CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
949 CSR_READ_1(sc, STE_STAT_LATE_COLLS);
950 CSR_READ_1(sc, STE_STAT_TX_DEFER);
951 CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
952 CSR_READ_1(sc, STE_STAT_TX_ABORT);
953}
954
955static void
956ste_stats_update(struct ste_softc *sc)
957{
958 struct ifnet *ifp;
959 struct ste_hw_stats *stats;
960 uint32_t val;
961
962 STE_LOCK_ASSERT(sc);
963
964 ifp = sc->ste_ifp;
965 stats = &sc->ste_stats;
966 /* Rx stats. */
967 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) |
968 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16;
969 val &= 0x000FFFFF;
970 stats->rx_bytes += val;
971 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES);
972 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST);
973 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST);
974 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST);
975 /* Tx stats. */
976 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) |
977 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16;
978 val &= 0x000FFFFF;
979 stats->tx_bytes += val;
980 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES);
981 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST);
982 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST);
983 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
984 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
985 stats->tx_single_colls += val;
986 ifp->if_collisions += val;
987 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
988 stats->tx_multi_colls += val;
989 ifp->if_collisions += val;
990 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS);
991 stats->tx_late_colls += val;
992 ifp->if_collisions += val;
993 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER);
994 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
995 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT);
996}
997
998/*
999 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
1000 * IDs against our list and return a device name if we find a match.
1001 */
1002static int
1003ste_probe(device_t dev)
1004{
1005 struct ste_type *t;
1006
1007 t = ste_devs;
1008
1009 while (t->ste_name != NULL) {
1010 if ((pci_get_vendor(dev) == t->ste_vid) &&
1011 (pci_get_device(dev) == t->ste_did)) {
1012 device_set_desc(dev, t->ste_name);
1013 return (BUS_PROBE_DEFAULT);
1014 }
1015 t++;
1016 }
1017
1018 return (ENXIO);
1019}
1020
1021/*
1022 * Attach the interface. Allocate softc structures, do ifmedia
1023 * setup and ethernet/BPF attach.
1024 */
1025static int
1026ste_attach(device_t dev)
1027{
1028 struct ste_softc *sc;
1029 struct ifnet *ifp;
1030 u_char eaddr[6];
1031 int error = 0, rid;
1032
1033 sc = device_get_softc(dev);
1034 sc->ste_dev = dev;
1035
1036 /*
1037 * Only use one PHY since this chip reports multiple
1038 * Note on the DFE-550 the PHY is at 1 on the DFE-580
1039 * it is at 0 & 1. It is rev 0x12.
1040 */
1041 if (pci_get_vendor(dev) == DL_VENDORID &&
1042 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
1043 pci_get_revid(dev) == 0x12 )
1044 sc->ste_flags |= STE_FLAG_ONE_PHY;
1045
1046 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1047 MTX_DEF);
1048 /*
1049 * Map control/status registers.
1050 */
1051 pci_enable_busmaster(dev);
1052
1053 /* Prefer memory space register mapping over IO space. */
1054 sc->ste_res_id = PCIR_BAR(1);
1055 sc->ste_res_type = SYS_RES_MEMORY;
1056 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
1057 &sc->ste_res_id, RF_ACTIVE);
1058 if (sc->ste_res == NULL) {
1059 sc->ste_res_id = PCIR_BAR(0);
1060 sc->ste_res_type = SYS_RES_IOPORT;
1061 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
1062 &sc->ste_res_id, RF_ACTIVE);
1063 }
1064 if (sc->ste_res == NULL) {
1065 device_printf(dev, "couldn't map ports/memory\n");
1066 error = ENXIO;
1067 goto fail;
1068 }
1069
1070 /* Allocate interrupt */
1071 rid = 0;
1072 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1073 RF_SHAREABLE | RF_ACTIVE);
1074
1075 if (sc->ste_irq == NULL) {
1076 device_printf(dev, "couldn't map interrupt\n");
1077 error = ENXIO;
1078 goto fail;
1079 }
1080
1081 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0);
1082
1083 /* Reset the adapter. */
1084 ste_reset(sc);
1085
1086 /*
1087 * Get station address from the EEPROM.
1088 */
1089 if (ste_read_eeprom(sc, eaddr,
1090 STE_EEADDR_NODE0, 3, 0)) {
1091 device_printf(dev, "failed to read station address\n");
1092 error = ENXIO;;
1093 goto fail;
1094 }
1095 ste_sysctl_node(sc);
1096
1097 if ((error = ste_dma_alloc(sc)) != 0)
1098 goto fail;
1099
1100 ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
1101 if (ifp == NULL) {
1102 device_printf(dev, "can not if_alloc()\n");
1103 error = ENOSPC;
1104 goto fail;
1105 }
1106
1107 /* Do MII setup. */
1108 if (mii_phy_probe(dev, &sc->ste_miibus,
1109 ste_ifmedia_upd, ste_ifmedia_sts)) {
1110 device_printf(dev, "MII without any phy!\n");
1111 error = ENXIO;
1112 goto fail;
1113 }
1114
1115 ifp->if_softc = sc;
1116 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1117 ifp->if_mtu = ETHERMTU;
1118 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1119 ifp->if_ioctl = ste_ioctl;
1120 ifp->if_start = ste_start;
1121 ifp->if_init = ste_init;
1122 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1123 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
1124 IFQ_SET_READY(&ifp->if_snd);
1125
1126 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1127
1128 /*
1129 * Call MI attach routine.
1130 */
1131 ether_ifattach(ifp, eaddr);
1132
1133 /*
1134 * Tell the upper layer(s) we support long frames.
1135 */
1136 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1137 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1138 ifp->if_capenable = ifp->if_capabilities;
1139#ifdef DEVICE_POLLING
1140 ifp->if_capabilities |= IFCAP_POLLING;
1141#endif
1142
1143 /* Hook interrupt last to avoid having to lock softc */
1144 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
1145 NULL, ste_intr, sc, &sc->ste_intrhand);
1146
1147 if (error) {
1148 device_printf(dev, "couldn't set up irq\n");
1149 ether_ifdetach(ifp);
1150 goto fail;
1151 }
1152
1153fail:
1154 if (error)
1155 ste_detach(dev);
1156
1157 return (error);
1158}
1159
1160/*
1161 * Shutdown hardware and free up resources. This can be called any
1162 * time after the mutex has been initialized. It is called in both
1163 * the error case in attach and the normal detach case so it needs
1164 * to be careful about only freeing resources that have actually been
1165 * allocated.
1166 */
1167static int
1168ste_detach(device_t dev)
1169{
1170 struct ste_softc *sc;
1171 struct ifnet *ifp;
1172
1173 sc = device_get_softc(dev);
1174 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1175 ifp = sc->ste_ifp;
1176
1177#ifdef DEVICE_POLLING
1178 if (ifp->if_capenable & IFCAP_POLLING)
1179 ether_poll_deregister(ifp);
1180#endif
1181
1182 /* These should only be active if attach succeeded */
1183 if (device_is_attached(dev)) {
1184 ether_ifdetach(ifp);
1185 STE_LOCK(sc);
1186 ste_stop(sc);
1187 STE_UNLOCK(sc);
1188 callout_drain(&sc->ste_callout);
1189 }
1190 if (sc->ste_miibus)
1191 device_delete_child(dev, sc->ste_miibus);
1192 bus_generic_detach(dev);
1193
1194 if (sc->ste_intrhand)
1195 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1196 if (sc->ste_irq)
1197 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1198 if (sc->ste_res)
1199 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id,
1200 sc->ste_res);
1201
1202 if (ifp)
1203 if_free(ifp);
1204
1205 ste_dma_free(sc);
1206 mtx_destroy(&sc->ste_mtx);
1207
1208 return (0);
1209}
1210
1211struct ste_dmamap_arg {
1212 bus_addr_t ste_busaddr;
1213};
1214
1215static void
1216ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1217{
1218 struct ste_dmamap_arg *ctx;
1219
1220 if (error != 0)
1221 return;
1222
1223 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1224
1225 ctx = (struct ste_dmamap_arg *)arg;
1226 ctx->ste_busaddr = segs[0].ds_addr;
1227}
1228
1229static int
1230ste_dma_alloc(struct ste_softc *sc)
1231{
1232 struct ste_chain *txc;
1233 struct ste_chain_onefrag *rxc;
1234 struct ste_dmamap_arg ctx;
1235 int error, i;
1236
1237 /* Create parent DMA tag. */
1238 error = bus_dma_tag_create(
1239 bus_get_dma_tag(sc->ste_dev), /* parent */
1240 1, 0, /* alignment, boundary */
1241 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1242 BUS_SPACE_MAXADDR, /* highaddr */
1243 NULL, NULL, /* filter, filterarg */
1244 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1245 0, /* nsegments */
1246 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1247 0, /* flags */
1248 NULL, NULL, /* lockfunc, lockarg */
1249 &sc->ste_cdata.ste_parent_tag);
1250 if (error != 0) {
1251 device_printf(sc->ste_dev,
1252 "could not create parent DMA tag.\n");
1253 goto fail;
1254 }
1255
1256 /* Create DMA tag for Tx descriptor list. */
1257 error = bus_dma_tag_create(
1258 sc->ste_cdata.ste_parent_tag, /* parent */
1259 STE_DESC_ALIGN, 0, /* alignment, boundary */
1260 BUS_SPACE_MAXADDR, /* lowaddr */
1261 BUS_SPACE_MAXADDR, /* highaddr */
1262 NULL, NULL, /* filter, filterarg */
1263 STE_TX_LIST_SZ, /* maxsize */
1264 1, /* nsegments */
1265 STE_TX_LIST_SZ, /* maxsegsize */
1266 0, /* flags */
1267 NULL, NULL, /* lockfunc, lockarg */
1268 &sc->ste_cdata.ste_tx_list_tag);
1269 if (error != 0) {
1270 device_printf(sc->ste_dev,
1271 "could not create Tx list DMA tag.\n");
1272 goto fail;
1273 }
1274
1275 /* Create DMA tag for Rx descriptor list. */
1276 error = bus_dma_tag_create(
1277 sc->ste_cdata.ste_parent_tag, /* parent */
1278 STE_DESC_ALIGN, 0, /* alignment, boundary */
1279 BUS_SPACE_MAXADDR, /* lowaddr */
1280 BUS_SPACE_MAXADDR, /* highaddr */
1281 NULL, NULL, /* filter, filterarg */
1282 STE_RX_LIST_SZ, /* maxsize */
1283 1, /* nsegments */
1284 STE_RX_LIST_SZ, /* maxsegsize */
1285 0, /* flags */
1286 NULL, NULL, /* lockfunc, lockarg */
1287 &sc->ste_cdata.ste_rx_list_tag);
1288 if (error != 0) {
1289 device_printf(sc->ste_dev,
1290 "could not create Rx list DMA tag.\n");
1291 goto fail;
1292 }
1293
1294 /* Create DMA tag for Tx buffers. */
1295 error = bus_dma_tag_create(
1296 sc->ste_cdata.ste_parent_tag, /* parent */
1297 1, 0, /* alignment, boundary */
1298 BUS_SPACE_MAXADDR, /* lowaddr */
1299 BUS_SPACE_MAXADDR, /* highaddr */
1300 NULL, NULL, /* filter, filterarg */
1301 MCLBYTES * STE_MAXFRAGS, /* maxsize */
1302 STE_MAXFRAGS, /* nsegments */
1303 MCLBYTES, /* maxsegsize */
1304 0, /* flags */
1305 NULL, NULL, /* lockfunc, lockarg */
1306 &sc->ste_cdata.ste_tx_tag);
1307 if (error != 0) {
1308 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n");
1309 goto fail;
1310 }
1311
1312 /* Create DMA tag for Rx buffers. */
1313 error = bus_dma_tag_create(
1314 sc->ste_cdata.ste_parent_tag, /* parent */
1315 1, 0, /* alignment, boundary */
1316 BUS_SPACE_MAXADDR, /* lowaddr */
1317 BUS_SPACE_MAXADDR, /* highaddr */
1318 NULL, NULL, /* filter, filterarg */
1319 MCLBYTES, /* maxsize */
1320 1, /* nsegments */
1321 MCLBYTES, /* maxsegsize */
1322 0, /* flags */
1323 NULL, NULL, /* lockfunc, lockarg */
1324 &sc->ste_cdata.ste_rx_tag);
1325 if (error != 0) {
1326 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n");
1327 goto fail;
1328 }
1329
1330 /* Allocate DMA'able memory and load the DMA map for Tx list. */
1331 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag,
1332 (void **)&sc->ste_ldata.ste_tx_list,
1333 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1334 &sc->ste_cdata.ste_tx_list_map);
1335 if (error != 0) {
1336 device_printf(sc->ste_dev,
1337 "could not allocate DMA'able memory for Tx list.\n");
1338 goto fail;
1339 }
1340 ctx.ste_busaddr = 0;
1341 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag,
1342 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list,
1343 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1344 if (error != 0 || ctx.ste_busaddr == 0) {
1345 device_printf(sc->ste_dev,
1346 "could not load DMA'able memory for Tx list.\n");
1347 goto fail;
1348 }
1349 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr;
1350
1351 /* Allocate DMA'able memory and load the DMA map for Rx list. */
1352 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag,
1353 (void **)&sc->ste_ldata.ste_rx_list,
1354 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1355 &sc->ste_cdata.ste_rx_list_map);
1356 if (error != 0) {
1357 device_printf(sc->ste_dev,
1358 "could not allocate DMA'able memory for Rx list.\n");
1359 goto fail;
1360 }
1361 ctx.ste_busaddr = 0;
1362 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag,
1363 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list,
1364 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1365 if (error != 0 || ctx.ste_busaddr == 0) {
1366 device_printf(sc->ste_dev,
1367 "could not load DMA'able memory for Rx list.\n");
1368 goto fail;
1369 }
1370 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr;
1371
1372 /* Create DMA maps for Tx buffers. */
1373 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1374 txc = &sc->ste_cdata.ste_tx_chain[i];
1375 txc->ste_ptr = NULL;
1376 txc->ste_mbuf = NULL;
1377 txc->ste_next = NULL;
1378 txc->ste_phys = 0;
1379 txc->ste_map = NULL;
1380 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0,
1381 &txc->ste_map);
1382 if (error != 0) {
1383 device_printf(sc->ste_dev,
1384 "could not create Tx dmamap.\n");
1385 goto fail;
1386 }
1387 }
1388 /* Create DMA maps for Rx buffers. */
1389 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1390 &sc->ste_cdata.ste_rx_sparemap)) != 0) {
1391 device_printf(sc->ste_dev,
1392 "could not create spare Rx dmamap.\n");
1393 goto fail;
1394 }
1395 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1396 rxc = &sc->ste_cdata.ste_rx_chain[i];
1397 rxc->ste_ptr = NULL;
1398 rxc->ste_mbuf = NULL;
1399 rxc->ste_next = NULL;
1400 rxc->ste_map = NULL;
1401 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1402 &rxc->ste_map);
1403 if (error != 0) {
1404 device_printf(sc->ste_dev,
1405 "could not create Rx dmamap.\n");
1406 goto fail;
1407 }
1408 }
1409
1410fail:
1411 return (error);
1412}
1413
1414static void
1415ste_dma_free(struct ste_softc *sc)
1416{
1417 struct ste_chain *txc;
1418 struct ste_chain_onefrag *rxc;
1419 int i;
1420
1421 /* Tx buffers. */
1422 if (sc->ste_cdata.ste_tx_tag != NULL) {
1423 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1424 txc = &sc->ste_cdata.ste_tx_chain[i];
1425 if (txc->ste_map != NULL) {
1426 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag,
1427 txc->ste_map);
1428 txc->ste_map = NULL;
1429 }
1430 }
1431 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag);
1432 sc->ste_cdata.ste_tx_tag = NULL;
1433 }
1434 /* Rx buffers. */
1435 if (sc->ste_cdata.ste_rx_tag != NULL) {
1436 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1437 rxc = &sc->ste_cdata.ste_rx_chain[i];
1438 if (rxc->ste_map != NULL) {
1439 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1440 rxc->ste_map);
1441 rxc->ste_map = NULL;
1442 }
1443 }
1444 if (sc->ste_cdata.ste_rx_sparemap != NULL) {
1445 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1446 sc->ste_cdata.ste_rx_sparemap);
1447 sc->ste_cdata.ste_rx_sparemap = NULL;
1448 }
1449 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag);
1450 sc->ste_cdata.ste_rx_tag = NULL;
1451 }
1452 /* Tx descriptor list. */
1453 if (sc->ste_cdata.ste_tx_list_tag != NULL) {
1454 if (sc->ste_cdata.ste_tx_list_map != NULL)
1455 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag,
1456 sc->ste_cdata.ste_tx_list_map);
1457 if (sc->ste_cdata.ste_tx_list_map != NULL &&
1458 sc->ste_ldata.ste_tx_list != NULL)
1459 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag,
1460 sc->ste_ldata.ste_tx_list,
1461 sc->ste_cdata.ste_tx_list_map);
1462 sc->ste_ldata.ste_tx_list = NULL;
1463 sc->ste_cdata.ste_tx_list_map = NULL;
1464 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag);
1465 sc->ste_cdata.ste_tx_list_tag = NULL;
1466 }
1467 /* Rx descriptor list. */
1468 if (sc->ste_cdata.ste_rx_list_tag != NULL) {
1469 if (sc->ste_cdata.ste_rx_list_map != NULL)
1470 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag,
1471 sc->ste_cdata.ste_rx_list_map);
1472 if (sc->ste_cdata.ste_rx_list_map != NULL &&
1473 sc->ste_ldata.ste_rx_list != NULL)
1474 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag,
1475 sc->ste_ldata.ste_rx_list,
1476 sc->ste_cdata.ste_rx_list_map);
1477 sc->ste_ldata.ste_rx_list = NULL;
1478 sc->ste_cdata.ste_rx_list_map = NULL;
1479 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag);
1480 sc->ste_cdata.ste_rx_list_tag = NULL;
1481 }
1482 if (sc->ste_cdata.ste_parent_tag != NULL) {
1483 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag);
1484 sc->ste_cdata.ste_parent_tag = NULL;
1485 }
1486}
1487
1488static int
1489ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc)
1490{
1491 struct mbuf *m;
1492 bus_dma_segment_t segs[1];
1493 bus_dmamap_t map;
1494 int error, nsegs;
1495
1496 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1497 if (m == NULL)
1498 return (ENOBUFS);
1499 m->m_len = m->m_pkthdr.len = MCLBYTES;
1500 m_adj(m, ETHER_ALIGN);
1501
1502 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag,
1503 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) {
1504 m_freem(m);
1505 return (error);
1506 }
1507 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1508
1509 if (rxc->ste_mbuf != NULL) {
1510 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1511 BUS_DMASYNC_POSTREAD);
1512 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map);
1513 }
1514 map = rxc->ste_map;
1515 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap;
1516 sc->ste_cdata.ste_rx_sparemap = map;
1517 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1518 BUS_DMASYNC_PREREAD);
1519 rxc->ste_mbuf = m;
1520 rxc->ste_ptr->ste_status = 0;
1521 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr);
1522 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len |
1523 STE_FRAG_LAST);
1524 return (0);
1525}
1526
1527static int
1528ste_init_rx_list(struct ste_softc *sc)
1529{
1530 struct ste_chain_data *cd;
1531 struct ste_list_data *ld;
1532 int error, i;
1533
1534 cd = &sc->ste_cdata;
1535 ld = &sc->ste_ldata;
1536 bzero(ld->ste_rx_list, STE_RX_LIST_SZ);
1537 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1538 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1539 error = ste_newbuf(sc, &cd->ste_rx_chain[i]);
1540 if (error != 0)
1541 return (error);
1542 if (i == (STE_RX_LIST_CNT - 1)) {
1543 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0];
1544 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr +
1545 (sizeof(struct ste_desc_onefrag) * 0);
1546 } else {
1547 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1];
1548 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr +
1549 (sizeof(struct ste_desc_onefrag) * (i + 1));
1550 }
1551 }
1552
1553 cd->ste_rx_head = &cd->ste_rx_chain[0];
1554 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
1555 sc->ste_cdata.ste_rx_list_map,
1556 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1557
1558 return (0);
1559}
1560
1561static void
1562ste_init_tx_list(struct ste_softc *sc)
1563{
1564 struct ste_chain_data *cd;
1565 struct ste_list_data *ld;
1566 int i;
1567
1568 cd = &sc->ste_cdata;
1569 ld = &sc->ste_ldata;
1570 bzero(ld->ste_tx_list, STE_TX_LIST_SZ);
1571 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1572 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1573 cd->ste_tx_chain[i].ste_mbuf = NULL;
1574 if (i == (STE_TX_LIST_CNT - 1)) {
1575 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0];
1576 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1577 ld->ste_tx_list_paddr +
1578 (sizeof(struct ste_desc) * 0)));
1579 } else {
1580 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1];
1581 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1582 ld->ste_tx_list_paddr +
1583 (sizeof(struct ste_desc) * (i + 1))));
1584 }
1585 }
1586
1587 cd->ste_last_tx = NULL;
1588 cd->ste_tx_prod = 0;
1589 cd->ste_tx_cons = 0;
1590 cd->ste_tx_cnt = 0;
1591
1592 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1593 sc->ste_cdata.ste_tx_list_map,
1594 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1595}
1596
1597static void
1598ste_init(void *xsc)
1599{
1600 struct ste_softc *sc;
1601
1602 sc = xsc;
1603 STE_LOCK(sc);
1604 ste_init_locked(sc);
1605 STE_UNLOCK(sc);
1606}
1607
1608static void
1609ste_init_locked(struct ste_softc *sc)
1610{
1611 struct ifnet *ifp;
1612 struct mii_data *mii;
1613 int i;
1614
1615 STE_LOCK_ASSERT(sc);
1616 ifp = sc->ste_ifp;
1617 mii = device_get_softc(sc->ste_miibus);
1618
1619 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1620 return;
1621
1622 ste_stop(sc);
1623 /* Reset the chip to a known state. */
1624 ste_reset(sc);
1625
1626 /* Init our MAC address */
1627 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1628 CSR_WRITE_2(sc, STE_PAR0 + i,
1629 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) |
1630 IF_LLADDR(sc->ste_ifp)[i + 1] << 8));
1631 }
1632
1633 /* Init RX list */
1634 if (ste_init_rx_list(sc) != 0) {
1635 device_printf(sc->ste_dev,
1636 "initialization failed: no memory for RX buffers\n");
1637 ste_stop(sc);
1638 return;
1639 }
1640
1641 /* Set RX polling interval */
1642 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1643
1644 /* Init TX descriptors */
1645 ste_init_tx_list(sc);
1646
1647 /* Set the TX freethresh value */
1648 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1649
1650 /* Set the TX start threshold for best performance. */
1651 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1652
1653 /* Set the TX reclaim threshold. */
1654 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1655
1656 /* Accept VLAN length packets */
1657 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1658
1659 /* Set up the RX filter. */
1660 ste_rxfilter(sc);
1661
1662 /* Load the address of the RX list. */
1663 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1664 ste_wait(sc);
1665 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1666 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr));
1667 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1668 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1669
1670 /* Set TX polling interval(defer until we TX first packet). */
1671 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1672
1673 /* Load address of the TX list */
1674 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1675 ste_wait(sc);
1676 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1677 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1678 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1679 ste_wait(sc);
1680
1681 /* Enable receiver and transmitter */
1682 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1683 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1684 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1685 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1686
1687 /* Enable stats counters. */
1688 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1689 /* Clear stats counters. */
1690 ste_stats_clear(sc);
1691
1692 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1693#ifdef DEVICE_POLLING
1694 /* Disable interrupts if we are polling. */
1695 if (ifp->if_capenable & IFCAP_POLLING)
1696 CSR_WRITE_2(sc, STE_IMR, 0);
1697 else
1698#endif
1699 /* Enable interrupts. */
1700 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1701
1702 sc->ste_flags &= ~STE_FLAG_LINK;
1703 /* Switch to the current media. */
1704 mii_mediachg(mii);
1705
1706 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1707 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1708
1709 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
1710}
1711
1712static void
1713ste_stop(struct ste_softc *sc)
1714{
1715 struct ifnet *ifp;
1716 struct ste_chain_onefrag *cur_rx;
1717 struct ste_chain *cur_tx;
1718 uint32_t val;
1719 int i;
1720
1721 STE_LOCK_ASSERT(sc);
1722 ifp = sc->ste_ifp;
1723
1724 callout_stop(&sc->ste_callout);
1725 sc->ste_timer = 0;
1726 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1727
1728 CSR_WRITE_2(sc, STE_IMR, 0);
1729 /* Stop pending DMA. */
1730 val = CSR_READ_4(sc, STE_DMACTL);
1731 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL;
1732 CSR_WRITE_4(sc, STE_DMACTL, val);
1733 ste_wait(sc);
1734 /* Disable auto-polling. */
1735 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0);
1736 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1737 /* Nullify DMA address to stop any further DMA. */
1738 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0);
1739 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1740 /* Stop TX/RX MAC. */
1741 val = CSR_READ_2(sc, STE_MACCTL1);
1742 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE |
1743 STE_MACCTL1_STATS_DISABLE;
1744 CSR_WRITE_2(sc, STE_MACCTL1, val);
1745 for (i = 0; i < STE_TIMEOUT; i++) {
1746 DELAY(10);
1747 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE |
1748 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0)
1749 break;
1750 }
1751 if (i == STE_TIMEOUT)
1752 device_printf(sc->ste_dev, "Stopping MAC timed out\n");
1753 /* Acknowledge any pending interrupts. */
1754 CSR_READ_2(sc, STE_ISR_ACK);
1755 ste_stats_update(sc);
1756
1757 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1758 cur_rx = &sc->ste_cdata.ste_rx_chain[i];
1759 if (cur_rx->ste_mbuf != NULL) {
1760 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag,
1761 cur_rx->ste_map, BUS_DMASYNC_POSTREAD);
1762 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag,
1763 cur_rx->ste_map);
1764 m_freem(cur_rx->ste_mbuf);
1765 cur_rx->ste_mbuf = NULL;
1766 }
1767 }
1768
1769 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1770 cur_tx = &sc->ste_cdata.ste_tx_chain[i];
1771 if (cur_tx->ste_mbuf != NULL) {
1772 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag,
1773 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE);
1774 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag,
1775 cur_tx->ste_map);
1776 m_freem(cur_tx->ste_mbuf);
1777 cur_tx->ste_mbuf = NULL;
1778 }
1779 }
1780}
1781
1782static void
1783ste_reset(struct ste_softc *sc)
1784{
1785 uint32_t ctl;
1786 int i;
1787
1788 ctl = CSR_READ_4(sc, STE_ASICCTL);
1789 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET |
1790 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET |
1791 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET |
1792 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET |
1793 STE_ASICCTL_EXTRESET_RESET;
1794 CSR_WRITE_4(sc, STE_ASICCTL, ctl);
1795 CSR_READ_4(sc, STE_ASICCTL);
1796 /*
1797 * Due to the need of accessing EEPROM controller can take
1798 * up to 1ms to complete the global reset.
1799 */
1800 DELAY(1000);
1801
1802 for (i = 0; i < STE_TIMEOUT; i++) {
1803 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1804 break;
1805 DELAY(10);
1806 }
1807
1808 if (i == STE_TIMEOUT)
1809 device_printf(sc->ste_dev, "global reset never completed\n");
1810}
1811
1812static void
1813ste_restart_tx(struct ste_softc *sc)
1814{
1815 uint16_t mac;
1816 int i;
1817
1818 for (i = 0; i < STE_TIMEOUT; i++) {
1819 mac = CSR_READ_2(sc, STE_MACCTL1);
1820 mac |= STE_MACCTL1_TX_ENABLE;
1821 CSR_WRITE_2(sc, STE_MACCTL1, mac);
1822 mac = CSR_READ_2(sc, STE_MACCTL1);
1823 if ((mac & STE_MACCTL1_TX_ENABLED) != 0)
1824 break;
1825 DELAY(10);
1826 }
1827
1828 if (i == STE_TIMEOUT)
1829 device_printf(sc->ste_dev, "starting Tx failed");
1830}
1831
1832static int
1833ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1834{
1835 struct ste_softc *sc;
1836 struct ifreq *ifr;
1837 struct mii_data *mii;
1838 int error = 0;
1839
1840 sc = ifp->if_softc;
1841 ifr = (struct ifreq *)data;
1842
1843 switch (command) {
1844 case SIOCSIFFLAGS:
1845 STE_LOCK(sc);
1846 if ((ifp->if_flags & IFF_UP) != 0) {
1847 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1848 ((ifp->if_flags ^ sc->ste_if_flags) &
1849 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1850 ste_rxfilter(sc);
1851 else
1852 ste_init_locked(sc);
1853 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1854 ste_stop(sc);
1855 sc->ste_if_flags = ifp->if_flags;
1856 STE_UNLOCK(sc);
1857 break;
1858 case SIOCADDMULTI:
1859 case SIOCDELMULTI:
1860 STE_LOCK(sc);
1861 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1862 ste_rxfilter(sc);
1863 STE_UNLOCK(sc);
1864 break;
1865 case SIOCGIFMEDIA:
1866 case SIOCSIFMEDIA:
1867 mii = device_get_softc(sc->ste_miibus);
1868 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1869 break;
1870 case SIOCSIFCAP:
1871#ifdef DEVICE_POLLING
1872 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1873 !(ifp->if_capenable & IFCAP_POLLING)) {
1874 error = ether_poll_register(ste_poll, ifp);
1875 if (error)
1876 return (error);
1877 STE_LOCK(sc);
1878 /* Disable interrupts */
1879 CSR_WRITE_2(sc, STE_IMR, 0);
1880 ifp->if_capenable |= IFCAP_POLLING;
1881 STE_UNLOCK(sc);
1882 return (error);
1883
1884 }
1885 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1886 ifp->if_capenable & IFCAP_POLLING) {
1887 error = ether_poll_deregister(ifp);
1888 /* Enable interrupts. */
1889 STE_LOCK(sc);
1890 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1891 ifp->if_capenable &= ~IFCAP_POLLING;
1892 STE_UNLOCK(sc);
1893 return (error);
1894 }
1895#endif /* DEVICE_POLLING */
1896 break;
1897 default:
1898 error = ether_ioctl(ifp, command, data);
1899 break;
1900 }
1901
1902 return (error);
1903}
1904
1905static int
1906ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc)
1907{
1908 struct ste_frag *frag;
1909 struct mbuf *m;
1910 struct ste_desc *desc;
1911 bus_dma_segment_t txsegs[STE_MAXFRAGS];
1912 int error, i, nsegs;
1913
1914 STE_LOCK_ASSERT(sc);
1915 M_ASSERTPKTHDR((*m_head));
1916
1917 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1918 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1919 if (error == EFBIG) {
1920 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS);
1921 if (m == NULL) {
1922 m_freem(*m_head);
1923 *m_head = NULL;
1924 return (ENOMEM);
1925 }
1926 *m_head = m;
1927 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1928 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1929 if (error != 0) {
1930 m_freem(*m_head);
1931 *m_head = NULL;
1932 return (error);
1933 }
1934 } else if (error != 0)
1935 return (error);
1936 if (nsegs == 0) {
1937 m_freem(*m_head);
1938 *m_head = NULL;
1939 return (EIO);
1940 }
1941 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map,
1942 BUS_DMASYNC_PREWRITE);
1943
1944 desc = txc->ste_ptr;
1945 for (i = 0; i < nsegs; i++) {
1946 frag = &desc->ste_frags[i];
1947 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr));
1948 frag->ste_len = htole32(txsegs[i].ds_len);
1949 }
1950 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST);
1951 /*
1952 * Because we use Tx polling we can't chain multiple
1953 * Tx descriptors here. Otherwise we race with controller.
1954 */
1955 desc->ste_next = 0;
1956 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | STE_TXCTL_DMAINTR);
1957 txc->ste_mbuf = *m_head;
1958 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT);
1959 sc->ste_cdata.ste_tx_cnt++;
1960
1961 return (0);
1962}
1963
1964static void
1965ste_start(struct ifnet *ifp)
1966{
1967 struct ste_softc *sc;
1968
1969 sc = ifp->if_softc;
1970 STE_LOCK(sc);
1971 ste_start_locked(ifp);
1972 STE_UNLOCK(sc);
1973}
1974
1975static void
1976ste_start_locked(struct ifnet *ifp)
1977{
1978 struct ste_softc *sc;
1979 struct ste_chain *cur_tx;
1980 struct mbuf *m_head = NULL;
1981 int enq;
1982
1983 sc = ifp->if_softc;
1984 STE_LOCK_ASSERT(sc);
1985
1986 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1987 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0)
1988 return;
1989
1990 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
1991 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) {
1992 /*
1993 * Controller may have cached copy of the last used
1994 * next ptr so we have to reserve one TFD to avoid
1995 * TFD overruns.
1996 */
1997 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1998 break;
1999 }
2000 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2001 if (m_head == NULL)
2002 break;
2003 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod];
2004 if (ste_encap(sc, &m_head, cur_tx) != 0) {
2005 if (m_head == NULL)
2006 break;
2007 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2008 break;
2009 }
2010 if (sc->ste_cdata.ste_last_tx == NULL) {
2011 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
2012 sc->ste_cdata.ste_tx_list_map,
2013 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2014 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
2015 ste_wait(sc);
2016 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
2017 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr));
2018 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
2019 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
2020 ste_wait(sc);
2021 } else {
2022 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next =
2023 sc->ste_cdata.ste_last_tx->ste_phys;
2024 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
2025 sc->ste_cdata.ste_tx_list_map,
2026 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2027 }
2028 sc->ste_cdata.ste_last_tx = cur_tx;
2029
2030 enq++;
2031 /*
2032 * If there's a BPF listener, bounce a copy of this frame
2033 * to him.
2034 */
2035 BPF_MTAP(ifp, m_head);
2036 }
2037
2038 if (enq > 0)
2039 sc->ste_timer = STE_TX_TIMEOUT;
2040}
2041
2042static void
2043ste_watchdog(struct ste_softc *sc)
2044{
2045 struct ifnet *ifp;
2046
2047 ifp = sc->ste_ifp;
2048 STE_LOCK_ASSERT(sc);
2049
2050 if (sc->ste_timer == 0 || --sc->ste_timer)
2051 return;
2052
2053 ifp->if_oerrors++;
2054 if_printf(ifp, "watchdog timeout\n");
2055
2056 ste_txeof(sc);
2057 ste_txeoc(sc);
2058 ste_rxeof(sc, -1);
2059 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2060 ste_init_locked(sc);
2061
2062 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2063 ste_start_locked(ifp);
2064}
2065
2066static int
2067ste_shutdown(device_t dev)
2068{
2069 struct ste_softc *sc;
2070
2071 sc = device_get_softc(dev);
2072
2073 STE_LOCK(sc);
2074 ste_stop(sc);
2075 STE_UNLOCK(sc);
2076
2077 return (0);
2078}
2079
2080#define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
2081 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
2082#define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
2083 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
2084
2085static void
2086ste_sysctl_node(struct ste_softc *sc)
2087{
2088 struct sysctl_ctx_list *ctx;
2089 struct sysctl_oid_list *child, *parent;
2090 struct sysctl_oid *tree;
2091 struct ste_hw_stats *stats;
2092
2093 stats = &sc->ste_stats;
2094 ctx = device_get_sysctl_ctx(sc->ste_dev);
2095 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev));
2096
2097 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
2098 NULL, "STE statistics");
2099 parent = SYSCTL_CHILDREN(tree);
2100
2101 /* Rx statistics. */
2102 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
2103 NULL, "Rx MAC statistics");
2104 child = SYSCTL_CHILDREN(tree);
2105 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2106 &stats->rx_bytes, "Good octets");
2107 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2108 &stats->rx_frames, "Good frames");
2109 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2110 &stats->rx_bcast_frames, "Good broadcast frames");
2111 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2112 &stats->rx_mcast_frames, "Good multicast frames");
2113 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames",
2114 &stats->rx_lost_frames, "Lost frames");
2115
2116 /* Tx statistics. */
2117 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
2118 NULL, "Tx MAC statistics");
2119 child = SYSCTL_CHILDREN(tree);
2120 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2121 &stats->tx_bytes, "Good octets");
2122 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2123 &stats->tx_frames, "Good frames");
2124 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2125 &stats->tx_bcast_frames, "Good broadcast frames");
2126 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2127 &stats->tx_mcast_frames, "Good multicast frames");
2128 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs",
2129 &stats->tx_carrsense_errs, "Carrier sense errors");
2130 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
2131 &stats->tx_single_colls, "Single collisions");
2132 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
2133 &stats->tx_multi_colls, "Multiple collisions");
2134 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
2135 &stats->tx_late_colls, "Late collisions");
2136 STE_SYSCTL_STAT_ADD32(ctx, child, "defers",
2137 &stats->tx_frames_defered, "Frames with deferrals");
2138 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
2139 &stats->tx_excess_defers, "Frames with excessive derferrals");
2140 STE_SYSCTL_STAT_ADD32(ctx, child, "abort",
2141 &stats->tx_abort, "Aborted frames due to Excessive collisions");
2142}
2143
2144#undef STE_SYSCTL_STAT_ADD32
2145#undef STE_SYSCTL_STAT_ADD64