1/*
2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
3 * Copyright Luigi Rizzo, 1997,1998
4 * Copyright by Hannu Savolainen 1994, 1995
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
| 1/*
2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
3 * Copyright Luigi Rizzo, 1997,1998
4 * Copyright by Hannu Savolainen 1994, 1995
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/sound/isa/mss.c 53512 1999-11-21 17:15:12Z cg $
| 28 * $FreeBSD: head/sys/dev/sound/isa/mss.c 53553 1999-11-22 06:07:49Z tanimura $
|
29 */
30
31#include <dev/sound/pcm/sound.h>
32
33#if NPCM > 0
34
35/* board-specific include files */
36#include <dev/sound/isa/mss.h>
| 29 */
30
31#include <dev/sound/pcm/sound.h>
32
33#if NPCM > 0
34
35/* board-specific include files */
36#include <dev/sound/isa/mss.h>
|
| 37#include <dev/sound/chip.h>
|
37
| 38
|
| 39#include "gusc.h"
40#if notyet
41#include "midi.h"
42#endif /* notyet */
43
|
38#define abs(x) (((x) < 0) ? -(x) : (x))
39
40struct mss_info;
41
42struct mss_chinfo {
43 struct mss_info *parent;
44 pcm_channel *channel;
45 snd_dbuf *buffer;
46 int dir;
47};
48
49struct mss_info {
50 struct resource *io_base; /* primary I/O address for the board */
51 int io_rid;
52 struct resource *conf_base; /* and the opti931 also has a config space */
53 int conf_rid;
54 struct resource *irq;
55 int irq_rid;
56 struct resource *drq1; /* play */
57 int drq1_rid;
58 struct resource *drq2; /* rec */
59 int drq2_rid;
60 bus_dma_tag_t parent_dmat;
61
62 int pdma, rdma;
63 int bd_id; /* used to hold board-id info, eg. sb version,
64 * mss codec type, etc. etc.
65 */
66 int opti_offset; /* offset from config_base for opti931 */
67 u_long bd_flags; /* board-specific flags */
68 struct mss_chinfo pch, rch;
69};
70
71static int mss_probe(device_t dev);
72static int mss_attach(device_t dev);
73
74static driver_intr_t mss_intr;
75
76/* prototypes for local functions */
77static int mss_detect(device_t dev, struct mss_info *mss);
78static char *ymf_test(device_t dev, struct mss_info *mss);
79static void ad_unmute(struct mss_info *mss);
80
81/* mixer set funcs */
82static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
83static int mss_set_recsrc(struct mss_info *mss, int mask);
84
85/* io funcs */
86static int ad_wait_init(struct mss_info *mss, int x);
87static int ad_read(struct mss_info *mss, int reg);
88static void ad_write(struct mss_info *mss, int reg, u_char data);
89static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
90
91/* io primitives */
92static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
93static u_char conf_rd(struct mss_info *mss, u_char reg);
94
95#if NPNP > 0
96static int pnpmss_probe(device_t dev);
97static int pnpmss_attach(device_t dev);
98
99static driver_intr_t opti931_intr;
100#endif
101
102static int mssmix_init(snd_mixer *m);
103static int mssmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right);
104static int mssmix_setrecsrc(snd_mixer *m, u_int32_t src);
105static snd_mixer mss_mixer = {
106 "MSS mixer",
107 mssmix_init,
108 mssmix_set,
109 mssmix_setrecsrc,
110};
111
112static int ymmix_init(snd_mixer *m);
113static int ymmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right);
114static int ymmix_setrecsrc(snd_mixer *m, u_int32_t src);
115static snd_mixer yamaha_mixer = {
116 "OPL3-SAx mixer",
117 ymmix_init,
118 ymmix_set,
119 ymmix_setrecsrc,
120};
121
122static devclass_t pcm_devclass;
123
124/* channel interface */
125static void *msschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir);
126static int msschan_setdir(void *data, int dir);
127static int msschan_setformat(void *data, u_int32_t format);
128static int msschan_setspeed(void *data, u_int32_t speed);
129static int msschan_setblocksize(void *data, u_int32_t blocksize);
130static int msschan_trigger(void *data, int go);
131static int msschan_getptr(void *data);
132static pcmchan_caps *msschan_getcaps(void *data);
133
134static pcmchan_caps mss_caps = {
135 4000, 48000,
136 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
137 AFMT_STEREO | AFMT_S16_LE
138};
139
140static pcmchan_caps guspnp_caps = {
141 4000, 48000,
142 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE | AFMT_A_LAW,
143 AFMT_STEREO | AFMT_S16_LE
144};
145
146static pcmchan_caps opti931_caps = {
147 4000, 48000,
148 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE,
149 AFMT_STEREO | AFMT_S16_LE
150};
151
152static pcm_channel mss_chantemplate = {
153 msschan_init,
154 msschan_setdir,
155 msschan_setformat,
156 msschan_setspeed,
157 msschan_setblocksize,
158 msschan_trigger,
159 msschan_getptr,
160 msschan_getcaps,
161};
162
163#define MD_AD1848 0x91
164#define MD_AD1845 0x92
165#define MD_CS4248 0xA1
166#define MD_CS4231 0xA2
167#define MD_CS4231A 0xA3
168#define MD_CS4232 0xA4
169#define MD_CS4232A 0xA5
170#define MD_CS4236 0xA6
171#define MD_CS4237 0xA7
172#define MD_OPTI931 0xB1
173#define MD_OPTI925 0xB2
174#define MD_GUSPNP 0xB8
| 44#define abs(x) (((x) < 0) ? -(x) : (x))
45
46struct mss_info;
47
48struct mss_chinfo {
49 struct mss_info *parent;
50 pcm_channel *channel;
51 snd_dbuf *buffer;
52 int dir;
53};
54
55struct mss_info {
56 struct resource *io_base; /* primary I/O address for the board */
57 int io_rid;
58 struct resource *conf_base; /* and the opti931 also has a config space */
59 int conf_rid;
60 struct resource *irq;
61 int irq_rid;
62 struct resource *drq1; /* play */
63 int drq1_rid;
64 struct resource *drq2; /* rec */
65 int drq2_rid;
66 bus_dma_tag_t parent_dmat;
67
68 int pdma, rdma;
69 int bd_id; /* used to hold board-id info, eg. sb version,
70 * mss codec type, etc. etc.
71 */
72 int opti_offset; /* offset from config_base for opti931 */
73 u_long bd_flags; /* board-specific flags */
74 struct mss_chinfo pch, rch;
75};
76
77static int mss_probe(device_t dev);
78static int mss_attach(device_t dev);
79
80static driver_intr_t mss_intr;
81
82/* prototypes for local functions */
83static int mss_detect(device_t dev, struct mss_info *mss);
84static char *ymf_test(device_t dev, struct mss_info *mss);
85static void ad_unmute(struct mss_info *mss);
86
87/* mixer set funcs */
88static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
89static int mss_set_recsrc(struct mss_info *mss, int mask);
90
91/* io funcs */
92static int ad_wait_init(struct mss_info *mss, int x);
93static int ad_read(struct mss_info *mss, int reg);
94static void ad_write(struct mss_info *mss, int reg, u_char data);
95static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
96
97/* io primitives */
98static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
99static u_char conf_rd(struct mss_info *mss, u_char reg);
100
101#if NPNP > 0
102static int pnpmss_probe(device_t dev);
103static int pnpmss_attach(device_t dev);
104
105static driver_intr_t opti931_intr;
106#endif
107
108static int mssmix_init(snd_mixer *m);
109static int mssmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right);
110static int mssmix_setrecsrc(snd_mixer *m, u_int32_t src);
111static snd_mixer mss_mixer = {
112 "MSS mixer",
113 mssmix_init,
114 mssmix_set,
115 mssmix_setrecsrc,
116};
117
118static int ymmix_init(snd_mixer *m);
119static int ymmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right);
120static int ymmix_setrecsrc(snd_mixer *m, u_int32_t src);
121static snd_mixer yamaha_mixer = {
122 "OPL3-SAx mixer",
123 ymmix_init,
124 ymmix_set,
125 ymmix_setrecsrc,
126};
127
128static devclass_t pcm_devclass;
129
130/* channel interface */
131static void *msschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir);
132static int msschan_setdir(void *data, int dir);
133static int msschan_setformat(void *data, u_int32_t format);
134static int msschan_setspeed(void *data, u_int32_t speed);
135static int msschan_setblocksize(void *data, u_int32_t blocksize);
136static int msschan_trigger(void *data, int go);
137static int msschan_getptr(void *data);
138static pcmchan_caps *msschan_getcaps(void *data);
139
140static pcmchan_caps mss_caps = {
141 4000, 48000,
142 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
143 AFMT_STEREO | AFMT_S16_LE
144};
145
146static pcmchan_caps guspnp_caps = {
147 4000, 48000,
148 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE | AFMT_A_LAW,
149 AFMT_STEREO | AFMT_S16_LE
150};
151
152static pcmchan_caps opti931_caps = {
153 4000, 48000,
154 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE,
155 AFMT_STEREO | AFMT_S16_LE
156};
157
158static pcm_channel mss_chantemplate = {
159 msschan_init,
160 msschan_setdir,
161 msschan_setformat,
162 msschan_setspeed,
163 msschan_setblocksize,
164 msschan_trigger,
165 msschan_getptr,
166 msschan_getcaps,
167};
168
169#define MD_AD1848 0x91
170#define MD_AD1845 0x92
171#define MD_CS4248 0xA1
172#define MD_CS4231 0xA2
173#define MD_CS4231A 0xA3
174#define MD_CS4232 0xA4
175#define MD_CS4232A 0xA5
176#define MD_CS4236 0xA6
177#define MD_CS4237 0xA7
178#define MD_OPTI931 0xB1
179#define MD_OPTI925 0xB2
180#define MD_GUSPNP 0xB8
|
| 181#define MD_GUSMAX 0xB9
|
175#define MD_YM0020 0xC1
176#define MD_VIVO 0xD1
177
178#define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
179
180#define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
181
182static int
183port_rd(struct resource *port, int off)
184{
185 if (port)
186 return bus_space_read_1(rman_get_bustag(port),
187 rman_get_bushandle(port),
188 off);
189 else
190 return -1;
191}
192
193static void
194port_wr(struct resource *port, int off, u_int8_t data)
195{
196 if (port)
197 return bus_space_write_1(rman_get_bustag(port),
198 rman_get_bushandle(port),
199 off, data);
200}
201
202static int
203io_rd(struct mss_info *mss, int reg)
204{
205 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
206 return port_rd(mss->io_base, reg);
207}
208
209static void
210io_wr(struct mss_info *mss, int reg, u_int8_t data)
211{
212 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
213 return port_wr(mss->io_base, reg, data);
214}
215
216static void
217conf_wr(struct mss_info *mss, u_char reg, u_char value)
218{
219 port_wr(mss->conf_base, 0, reg);
220 port_wr(mss->conf_base, 1, value);
221}
222
223static u_char
224conf_rd(struct mss_info *mss, u_char reg)
225{
226 port_wr(mss->conf_base, 0, reg);
227 return port_rd(mss->conf_base, 1);
228}
229
230static void
231opti_wr(struct mss_info *mss, u_char reg, u_char value)
232{
233 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
234 port_wr(mss->conf_base, mss->opti_offset + 1, value);
235}
236
237static u_char
238opti_rd(struct mss_info *mss, u_char reg)
239{
240 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
241 return port_rd(mss->conf_base, mss->opti_offset + 1);
242}
243
| 182#define MD_YM0020 0xC1
183#define MD_VIVO 0xD1
184
185#define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
186
187#define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
188
189static int
190port_rd(struct resource *port, int off)
191{
192 if (port)
193 return bus_space_read_1(rman_get_bustag(port),
194 rman_get_bushandle(port),
195 off);
196 else
197 return -1;
198}
199
200static void
201port_wr(struct resource *port, int off, u_int8_t data)
202{
203 if (port)
204 return bus_space_write_1(rman_get_bustag(port),
205 rman_get_bushandle(port),
206 off, data);
207}
208
209static int
210io_rd(struct mss_info *mss, int reg)
211{
212 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
213 return port_rd(mss->io_base, reg);
214}
215
216static void
217io_wr(struct mss_info *mss, int reg, u_int8_t data)
218{
219 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
220 return port_wr(mss->io_base, reg, data);
221}
222
223static void
224conf_wr(struct mss_info *mss, u_char reg, u_char value)
225{
226 port_wr(mss->conf_base, 0, reg);
227 port_wr(mss->conf_base, 1, value);
228}
229
230static u_char
231conf_rd(struct mss_info *mss, u_char reg)
232{
233 port_wr(mss->conf_base, 0, reg);
234 return port_rd(mss->conf_base, 1);
235}
236
237static void
238opti_wr(struct mss_info *mss, u_char reg, u_char value)
239{
240 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
241 port_wr(mss->conf_base, mss->opti_offset + 1, value);
242}
243
244static u_char
245opti_rd(struct mss_info *mss, u_char reg)
246{
247 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
248 return port_rd(mss->conf_base, mss->opti_offset + 1);
249}
250
|
244#if NPNP > 0
| 251#if NPNP > 0 || NGUSC > 0
|
245static void
246gus_wr(struct mss_info *mss, u_char reg, u_char value)
247{
248 port_wr(mss->conf_base, 3, reg);
249 port_wr(mss->conf_base, 5, value);
250}
251
252static u_char
253gus_rd(struct mss_info *mss, u_char reg)
254{
255 port_wr(mss->conf_base, 3, reg);
256 return port_rd(mss->conf_base, 5);
257}
| 252static void
253gus_wr(struct mss_info *mss, u_char reg, u_char value)
254{
255 port_wr(mss->conf_base, 3, reg);
256 port_wr(mss->conf_base, 5, value);
257}
258
259static u_char
260gus_rd(struct mss_info *mss, u_char reg)
261{
262 port_wr(mss->conf_base, 3, reg);
263 return port_rd(mss->conf_base, 5);
264}
|
258#endif
| 265#endif /* NPNP > 0 || NGUSC > 0 */
|
259
260static void
261mss_release_resources(struct mss_info *mss, device_t dev)
262{
263 if (mss->irq) {
264 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
265 mss->irq);
266 mss->irq = 0;
267 }
268 if (mss->drq1) {
269 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
270 mss->drq1);
271 mss->drq1 = 0;
272 mss->pdma = -1;
273 }
274 if (mss->drq2) {
275 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
276 mss->drq2);
277 mss->drq2 = 0;
278 mss->rdma = -1;
279 }
280 if (mss->io_base) {
281 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
282 mss->io_base);
283 mss->io_base = 0;
284 }
285 if (mss->conf_base) {
286 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
287 mss->conf_base);
288 mss->conf_base = 0;
289 }
290 free(mss, M_DEVBUF);
291}
292
293static int
294mss_alloc_resources(struct mss_info *mss, device_t dev)
295{
296 int ok = 1;
297 if (!mss->io_base)
298 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
299 0, ~0, 1, RF_ACTIVE);
300 if (!mss->irq)
301 mss->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &mss->irq_rid,
302 0, ~0, 1, RF_ACTIVE);
303 if (!mss->drq1)
304 mss->drq1 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq1_rid,
305 0, ~0, 1, RF_ACTIVE);
306 if (mss->conf_rid >= 0 && !mss->conf_base)
307 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
308 0, ~0, 1, RF_ACTIVE);
309 if (mss->drq2_rid >= 0 && !mss->drq2)
310 mss->drq2 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq2_rid,
311 0, ~0, 1, RF_ACTIVE);
312
313 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
314 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
315 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
316
317 if (ok) {
318 mss->pdma = rman_get_start(mss->drq1);
319 isa_dma_acquire(mss->pdma);
320 isa_dmainit(mss->pdma, DSP_BUFFSIZE);
321 mss->bd_flags &= ~BD_F_DUPLEX;
322 if (mss->drq2) {
323 mss->rdma = rman_get_start(mss->drq2);
324 isa_dma_acquire(mss->rdma);
325 isa_dmainit(mss->rdma, DSP_BUFFSIZE);
326 mss->bd_flags |= BD_F_DUPLEX;
327 } else mss->rdma = mss->pdma;
328 }
329 return ok;
330}
331
| 266
267static void
268mss_release_resources(struct mss_info *mss, device_t dev)
269{
270 if (mss->irq) {
271 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
272 mss->irq);
273 mss->irq = 0;
274 }
275 if (mss->drq1) {
276 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
277 mss->drq1);
278 mss->drq1 = 0;
279 mss->pdma = -1;
280 }
281 if (mss->drq2) {
282 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
283 mss->drq2);
284 mss->drq2 = 0;
285 mss->rdma = -1;
286 }
287 if (mss->io_base) {
288 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
289 mss->io_base);
290 mss->io_base = 0;
291 }
292 if (mss->conf_base) {
293 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
294 mss->conf_base);
295 mss->conf_base = 0;
296 }
297 free(mss, M_DEVBUF);
298}
299
300static int
301mss_alloc_resources(struct mss_info *mss, device_t dev)
302{
303 int ok = 1;
304 if (!mss->io_base)
305 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
306 0, ~0, 1, RF_ACTIVE);
307 if (!mss->irq)
308 mss->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &mss->irq_rid,
309 0, ~0, 1, RF_ACTIVE);
310 if (!mss->drq1)
311 mss->drq1 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq1_rid,
312 0, ~0, 1, RF_ACTIVE);
313 if (mss->conf_rid >= 0 && !mss->conf_base)
314 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
315 0, ~0, 1, RF_ACTIVE);
316 if (mss->drq2_rid >= 0 && !mss->drq2)
317 mss->drq2 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq2_rid,
318 0, ~0, 1, RF_ACTIVE);
319
320 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
321 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
322 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
323
324 if (ok) {
325 mss->pdma = rman_get_start(mss->drq1);
326 isa_dma_acquire(mss->pdma);
327 isa_dmainit(mss->pdma, DSP_BUFFSIZE);
328 mss->bd_flags &= ~BD_F_DUPLEX;
329 if (mss->drq2) {
330 mss->rdma = rman_get_start(mss->drq2);
331 isa_dma_acquire(mss->rdma);
332 isa_dmainit(mss->rdma, DSP_BUFFSIZE);
333 mss->bd_flags |= BD_F_DUPLEX;
334 } else mss->rdma = mss->pdma;
335 }
336 return ok;
337}
338
|
| 339#if NGUSC > 0
340/*
341 * XXX This might be better off in the gusc driver.
342 */
343static void
344gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
345{
346 static const unsigned char irq_bits[16] = {
347 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
348 };
349 static const unsigned char dma_bits[8] = {
350 0, 1, 0, 2, 0, 3, 4, 5
351 };
352 device_t parent = device_get_parent(dev);
353 unsigned char irqctl, dmactl;
354 int s;
355
356 s = splhigh();
357
358 port_wr(alt, 0x0f, 0x05);
359 port_wr(alt, 0x00, 0x0c);
360 port_wr(alt, 0x0b, 0x00);
361
362 port_wr(alt, 0x0f, 0x00);
363
364 irqctl = irq_bits[isa_get_irq(parent)];
365#if notyet
366#if NMIDI > 0
367 /* Share the IRQ with the MIDI driver. */
368 irqctl |= 0x40;
369#endif /* NMIDI > 0 */
370#endif /* notyet */
371 dmactl = dma_bits[isa_get_drq(parent)];
372 if (device_get_flags(parent) & DV_F_DUAL_DMA)
373 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
374 << 3;
375
376 /*
377 * Set the DMA and IRQ control latches.
378 */
379 port_wr(alt, 0x00, 0x0c);
380 port_wr(alt, 0x0b, dmactl | 0x80);
381 port_wr(alt, 0x00, 0x4c);
382 port_wr(alt, 0x0b, irqctl);
383
384 port_wr(alt, 0x00, 0x0c);
385 port_wr(alt, 0x0b, dmactl);
386 port_wr(alt, 0x00, 0x4c);
387 port_wr(alt, 0x0b, irqctl);
388
389 port_wr(mss->conf_base, 2, 0);
390 port_wr(alt, 0x00, 0x0c);
391 port_wr(mss->conf_base, 2, 0);
392
393 splx(s);
394}
395#endif /* NGUSC > 0 */
396
|
332static int
333mss_init(struct mss_info *mss, device_t dev)
334{
335 u_char r6, r9;
336 struct resource *alt;
337 int rid, tmp;
338
339 mss->bd_flags |= BD_F_MCE_BIT;
340 switch(mss->bd_id) {
341#if NPNP > 0
342 case MD_OPTI931:
343 /*
344 * The MED3931 v.1.0 allocates 3 bytes for the config
345 * space, whereas v.2.0 allocates 4 bytes. What I know
346 * for sure is that the upper two ports must be used,
347 * and they should end on a boundary of 4 bytes. So I
348 * need the following trick.
349 */
350 mss->opti_offset =
351 (rman_get_start(mss->conf_base) & ~3) + 2
352 - rman_get_start(mss->conf_base);
353 printf("mss_init: opti_offset=%d\n", mss->opti_offset);
354 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
355 ad_write(mss, 10, 2); /* enable interrupts */
356 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
357 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
358 break;
| 397static int
398mss_init(struct mss_info *mss, device_t dev)
399{
400 u_char r6, r9;
401 struct resource *alt;
402 int rid, tmp;
403
404 mss->bd_flags |= BD_F_MCE_BIT;
405 switch(mss->bd_id) {
406#if NPNP > 0
407 case MD_OPTI931:
408 /*
409 * The MED3931 v.1.0 allocates 3 bytes for the config
410 * space, whereas v.2.0 allocates 4 bytes. What I know
411 * for sure is that the upper two ports must be used,
412 * and they should end on a boundary of 4 bytes. So I
413 * need the following trick.
414 */
415 mss->opti_offset =
416 (rman_get_start(mss->conf_base) & ~3) + 2
417 - rman_get_start(mss->conf_base);
418 printf("mss_init: opti_offset=%d\n", mss->opti_offset);
419 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
420 ad_write(mss, 10, 2); /* enable interrupts */
421 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
422 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
423 break;
|
| 424#endif /* NPNP > 0 */
|
359
| 425
|
| 426#if NPNP > 0 || NGUSC > 0
|
360 case MD_GUSPNP:
| 427 case MD_GUSPNP:
|
| 428 case MD_GUSMAX:
|
361 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
362 DELAY(1000 * 30);
363 /* release reset and enable DAC */
364 gus_wr(mss, 0x4c /* _URSTI */, 3);
365 DELAY(1000 * 30);
366 /* end of reset */
367
368 rid = 0;
369 alt = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
370 0, ~0, 1, RF_ACTIVE);
| 429 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
430 DELAY(1000 * 30);
431 /* release reset and enable DAC */
432 gus_wr(mss, 0x4c /* _URSTI */, 3);
433 DELAY(1000 * 30);
434 /* end of reset */
435
436 rid = 0;
437 alt = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
438 0, ~0, 1, RF_ACTIVE);
|
| 439 if (alt == NULL) {
440 printf("XXX couldn't init GUS PnP/MAX\n");
441 break;
442 }
|
371 port_wr(alt, 0, 0xC); /* enable int and dma */
| 443 port_wr(alt, 0, 0xC); /* enable int and dma */
|
| 444#if NGUSC > 0
445 if (mss->bd_id == MD_GUSMAX)
446 gusmax_setup(mss, dev, alt);
447#endif
|
372 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
373
374 /*
375 * unmute left & right line. Need to go in mode3, unmute,
376 * and back to mode 2
377 */
378 tmp = ad_read(mss, 0x0c);
379 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
380 ad_write(mss, 0x19, 0); /* unmute left */
381 ad_write(mss, 0x1b, 0); /* unmute right */
382 ad_write(mss, 0x0c, tmp); /* restore old mode */
383
384 /* send codec interrupts on irq1 and only use that one */
385 gus_wr(mss, 0x5a, 0x4f);
386
387 /* enable access to hidden regs */
388 tmp = gus_rd(mss, 0x5b /* IVERI */);
389 gus_wr(mss, 0x5b, tmp | 1);
390 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
391 break;
| 448 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
449
450 /*
451 * unmute left & right line. Need to go in mode3, unmute,
452 * and back to mode 2
453 */
454 tmp = ad_read(mss, 0x0c);
455 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
456 ad_write(mss, 0x19, 0); /* unmute left */
457 ad_write(mss, 0x1b, 0); /* unmute right */
458 ad_write(mss, 0x0c, tmp); /* restore old mode */
459
460 /* send codec interrupts on irq1 and only use that one */
461 gus_wr(mss, 0x5a, 0x4f);
462
463 /* enable access to hidden regs */
464 tmp = gus_rd(mss, 0x5b /* IVERI */);
465 gus_wr(mss, 0x5b, tmp | 1);
466 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
467 break;
|
392#endif
| 468#endif /* NPNP > 0 || NGUSC > 0 */
469
|
393 case MD_YM0020:
394 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
395 r6 = conf_rd(mss, OPL3SAx_DMACONF);
396 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
397 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
398 /* yamaha - set volume to max */
399 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
400 conf_wr(mss, OPL3SAx_VOLUMER, 0);
401 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
402 break;
403 }
404 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
405 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
406 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
407 ad_write(mss, 10, 2); /* int enable */
408 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
409 /* the following seem required on the CS4232 */
410 ad_unmute(mss);
411 return 0;
412}
413
414/*
415 * mss_probe() is the probe routine. Note, it is not necessary to
416 * go through this for PnP devices, since they are already
417 * indentified precisely using their PnP id.
418 *
419 * The base address supplied in the device refers to the old MSS
420 * specs where the four 4 registers in io space contain configuration
421 * information. Some boards (as an example, early MSS boards)
422 * has such a block of registers, whereas others (generally CS42xx)
423 * do not. In order to distinguish between the two and do not have
424 * to supply two separate probe routines, the flags entry in isa_device
425 * has a bit to mark this.
426 *
427 */
428
429static int
430mss_probe(device_t dev)
431{
432 u_char tmp, tmpx;
433 int flags, irq, drq, result = ENXIO, setres = 0;
434 struct mss_info *mss;
435
436 if (isa_get_vendorid(dev)) return ENXIO; /* not yet */
437
438 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT);
439 if (!mss) return ENXIO;
440 bzero(mss, sizeof *mss);
441
442 mss->io_rid = 0;
443 mss->conf_rid = -1;
444 mss->irq_rid = 0;
445 mss->drq1_rid = 0;
446 mss->drq2_rid = -1;
447 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
448 0, ~0, 8, RF_ACTIVE);
449 if (!mss->io_base) {
450 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530));
451 mss->io_rid = 0;
452 /* XXX verify this */
453 setres = 1;
454 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
455 0x530, 8);
456 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
457 0, ~0, 8, RF_ACTIVE);
458 }
459 if (!mss->io_base) goto no;
460
461 /* got irq/dma regs? */
462 flags = device_get_flags(dev);
463 irq = isa_get_irq(dev);
464 drq = isa_get_drq(dev);
465
466 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
467
468 /*
469 * Check if the IO port returns valid signature. The original MS
470 * Sound system returns 0x04 while some cards
471 * (AudioTriX Pro for example) return 0x00 or 0x0f.
472 */
473
474 device_set_desc(dev, "MSS");
475 tmpx = tmp = io_rd(mss, 3);
476 if (tmp == 0xff) { /* Bus float */
477 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
478 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
479 goto mss_probe_end;
480 }
481 tmp &= 0x3f;
482 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) {
483 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n",
484 rman_get_start(mss->io_base), tmpx));
485 goto no;
486 }
487 if (irq > 11) {
488 printf("MSS: Bad IRQ %d\n", irq);
489 goto no;
490 }
491 if (!(drq == 0 || drq == 1 || drq == 3)) {
492 printf("MSS: Bad DMA %d\n", drq);
493 goto no;
494 }
495 if (tmpx & 0x80) {
496 /* 8-bit board: only drq1/3 and irq7/9 */
497 if (drq == 0) {
498 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
499 goto no;
500 }
501 if (!(irq == 7 || irq == 9)) {
502 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
503 irq);
504 goto no;
505 }
506 }
507 mss_probe_end:
508 result = mss_detect(dev, mss);
509 no:
510 mss_release_resources(mss, dev);
511#if 0
512 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
513 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
514#endif
515 return result;
516}
517
518static int
519mss_detect(device_t dev, struct mss_info *mss)
520{
521 int i;
522 u_char tmp, tmp1, tmp2;
523 char *name, *yamaha;
524
525 if (mss->bd_id != 0) {
526 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
527 device_get_desc(dev));
528 return 0;
529 }
530
531 name = "AD1848";
532 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
533
534 /*
535 * Check that the I/O address is in use.
536 *
537 * bit 7 of the base I/O port is known to be 0 after the chip has
538 * performed its power on initialization. Just assume this has
539 * happened before the OS is starting.
540 *
541 * If the I/O address is unused, it typically returns 0xff.
542 */
543
544 for (i = 0; i < 10; i++)
545 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
546 else break;
547
548 if (i >= 10) { /* Not a AD1848 */
549 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp));
550 goto no;
551 }
552 /*
553 * Test if it's possible to change contents of the indirect
554 * registers. Registers 0 and 1 are ADC volume registers. The bit
555 * 0x10 is read only so try to avoid using it.
556 */
557
558 ad_write(mss, 0, 0xaa);
559 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
560 tmp1 = ad_read(mss, 0);
561 tmp2 = ad_read(mss, 1);
562 if (tmp1 != 0xaa || tmp2 != 0x45) {
563 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
564 goto no;
565 }
566
567 ad_write(mss, 0, 0x45);
568 ad_write(mss, 1, 0xaa);
569 tmp1 = ad_read(mss, 0);
570 tmp2 = ad_read(mss, 1);
571 if (tmp1 != 0x45 || tmp2 != 0xaa) {
572 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
573 goto no;
574 }
575
576 /*
577 * The indirect register I12 has some read only bits. Lets try to
578 * change them.
579 */
580
581 tmp = ad_read(mss, 12);
582 ad_write(mss, 12, (~tmp) & 0x0f);
583 tmp1 = ad_read(mss, 12);
584
585 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
586 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
587 goto no;
588 }
589
590 /*
591 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
592 * 0x01=RevB
593 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
594 */
595
596 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
597
598 /*
599 * The original AD1848/CS4248 has just 16 indirect registers. This
600 * means that I0 and I16 should return the same value (etc.). Ensure
601 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
602 * with new parts.
603 */
604
605 ad_write(mss, 12, 0); /* Mode2=disabled */
606#if 0
607 for (i = 0; i < 16; i++) {
608 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
609 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
610 i, tmp1, tmp2));
611 /*
612 * note - this seems to fail on the 4232 on I11. So we just break
613 * rather than fail. (which makes this test pointless - cg)
614 */
615 break; /* return 0; */
616 }
617 }
618#endif
619 /*
620 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
621 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
622 *
623 * On the OPTi931, however, I12 is readonly and only contains the
624 * chip revision ID (as in the CS4231A). The upper bits return 0.
625 */
626
627 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
628
629 tmp1 = ad_read(mss, 12);
630 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
631 if ((tmp1 & 0xf0) == 0x00) {
632 BVDDB(printf("this should be an OPTi931\n");)
633 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
634 /*
635 * The 4231 has bit7=1 always, and bit6 we just set to 1.
636 * We want to check that this is really a CS4231
637 * Verify that setting I0 doesn't change I16.
638 */
639 ad_write(mss, 16, 0); /* Set I16 to known value */
640 ad_write(mss, 0, 0x45);
641 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
642
643 ad_write(mss, 0, 0xaa);
644 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
645 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1));
646 goto no;
647 }
648 /* Verify that some bits of I25 are read only. */
649 tmp1 = ad_read(mss, 25); /* Original bits */
650 ad_write(mss, 25, ~tmp1); /* Invert all bits */
651 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
652 int id;
653
654 /* It's at least CS4231 */
655 name = "CS4231";
656 mss->bd_id = MD_CS4231;
657
658 /*
659 * It could be an AD1845 or CS4231A as well.
660 * CS4231 and AD1845 report the same revision info in I25
661 * while the CS4231A reports different.
662 */
663
664 id = ad_read(mss, 25) & 0xe7;
665 /*
666 * b7-b5 = version number;
667 * 100 : all CS4231
668 * 101 : CS4231A
669 *
670 * b2-b0 = chip id;
671 */
672 switch (id) {
673
674 case 0xa0:
675 name = "CS4231A";
676 mss->bd_id = MD_CS4231A;
677 break;
678
679 case 0xa2:
680 name = "CS4232";
681 mss->bd_id = MD_CS4232;
682 break;
683
684 case 0xb2:
685 /* strange: the 4231 data sheet says b4-b3 are XX
686 * so this should be the same as 0xa2
687 */
688 name = "CS4232A";
689 mss->bd_id = MD_CS4232A;
690 break;
691
692 case 0x80:
693 /*
694 * It must be a CS4231 or AD1845. The register I23
695 * of CS4231 is undefined and it appears to be read
696 * only. AD1845 uses I23 for setting sample rate.
697 * Assume the chip is AD1845 if I23 is changeable.
698 */
699
700 tmp = ad_read(mss, 23);
701
702 ad_write(mss, 23, ~tmp);
703 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
704 name = "AD1845";
705 mss->bd_id = MD_AD1845;
706 }
707 ad_write(mss, 23, tmp); /* Restore */
708
709 yamaha = ymf_test(dev, mss);
710 if (yamaha) {
711 mss->bd_id = MD_YM0020;
712 name = yamaha;
713 }
714 break;
715
716 case 0x83: /* CS4236 */
717 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */
718 name = "CS4236";
719 mss->bd_id = MD_CS4236;
720 break;
721
722 default: /* Assume CS4231 */
723 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);)
724 mss->bd_id = MD_CS4231;
725 }
726 }
727 ad_write(mss, 25, tmp1); /* Restore bits */
728gotit:
729 BVDDB(printf("mss_detect() - Detected %s\n", name));
730 device_set_desc(dev, name);
731 device_set_flags(dev,
732 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
733 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
734 return 0;
735no:
736 return ENXIO;
737}
738
739static char *
740ymf_test(device_t dev, struct mss_info *mss)
741{
742 static int ports[] = {0x370, 0x310, 0x538};
743 int p, i, j, version;
744 static char *chipset[] = {
745 NULL, /* 0 */
746 "OPL3-SA2 (YMF711)", /* 1 */
747 "OPL3-SA3 (YMF715)", /* 2 */
748 "OPL3-SA3 (YMF715)", /* 3 */
749 "OPL3-SAx (YMF719)", /* 4 */
750 "OPL3-SAx (YMF719)", /* 5 */
751 "OPL3-SAx (YMF719)", /* 6 */
752 "OPL3-SAx (YMF719)", /* 7 */
753 };
754
755 for (p = 0; p < 3; p++) {
756 mss->conf_rid = 1;
757 mss->conf_base = bus_alloc_resource(dev,
758 SYS_RES_IOPORT,
759 &mss->conf_rid,
760 ports[p], ports[p] + 1, 2,
761 RF_ACTIVE);
762 if (!mss->conf_base) return 0;
763
764 /* Test the index port of the config registers */
765 i = port_rd(mss->conf_base, 0);
766 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
767 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
768 port_wr(mss->conf_base, 0, i);
769 if (!j) {
770 bus_release_resource(dev, SYS_RES_IOPORT,
771 mss->conf_rid, mss->conf_base);
772 mss->conf_base = 0;
773 continue;
774 }
775 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
776 return chipset[version];
777 }
778 return NULL;
779}
780
781static int
782mss_doattach(device_t dev, struct mss_info *mss)
783{
784 snddev_info *d = device_get_softc(dev);
785 void *ih;
786 int flags = device_get_flags(dev);
787 char status[SND_STATUSLEN];
788
789 if (!mss_alloc_resources(mss, dev)) goto no;
790 mss_init(mss, dev);
791 if (flags & DV_F_TRUE_MSS) {
792 /* has IRQ/DMA registers, set IRQ and DMA addr */
793 static char interrupt_bits[12] =
794 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
795 static char pdma_bits[4] = {1, 2, -1, 3};
796 static char valid_rdma[4] = {1, 0, -1, 0};
797 char bits;
798
799 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
800 goto no;
801 io_wr(mss, 0, bits | 0x40); /* config port */
802 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
803 /* Write IRQ+DMA setup */
804 if (pdma_bits[mss->pdma] == -1) goto no;
805 bits |= pdma_bits[mss->pdma];
806 if (mss->pdma != mss->rdma) {
807 if (mss->rdma == valid_rdma[mss->pdma]) bits |= 4;
808 else {
809 printf("invalid dual dma config %d:%d\n",
810 mss->pdma, mss->rdma);
811 goto no;
812 }
813 }
814 io_wr(mss, 0, bits);
815 printf("drq/irq conf %x\n", io_rd(mss, 0));
816 }
817 mixer_init(d, (mss->bd_id == MD_YM0020)? &yamaha_mixer : &mss_mixer, mss);
818 switch (mss->bd_id) {
819 #if NPNP > 0
820 case MD_OPTI931:
821 bus_setup_intr(dev, mss->irq, INTR_TYPE_TTY, opti931_intr, mss, &ih);
822 break;
823 #endif
824 default:
825 bus_setup_intr(dev, mss->irq, INTR_TYPE_TTY, mss_intr, mss, &ih);
826 }
827 if (mss->pdma == mss->rdma)
828 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
829 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
830 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
831 /*highaddr*/BUS_SPACE_MAXADDR,
832 /*filter*/NULL, /*filterarg*/NULL,
833 /*maxsize*/DSP_BUFFSIZE, /*nsegments*/1,
834 /*maxsegz*/0x3ffff,
835 /*flags*/0, &mss->parent_dmat) != 0) {
836 device_printf(dev, "unable to create dma tag\n");
837 goto no;
838 }
839 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d",
840 rman_get_start(mss->io_base), rman_get_start(mss->irq), mss->pdma);
841 if (mss->pdma != mss->rdma) snprintf(status + strlen(status),
842 SND_STATUSLEN - strlen(status), ":%d", mss->rdma);
843
844 if (pcm_register(dev, mss, 1, 1)) goto no;
845 pcm_addchan(dev, PCMDIR_REC, &mss_chantemplate, mss);
846 pcm_addchan(dev, PCMDIR_PLAY, &mss_chantemplate, mss);
847 pcm_setstatus(dev, status);
848
849 return 0;
850no:
851 mss_release_resources(mss, dev);
852 return ENXIO;
853}
854
855static int
856mss_attach(device_t dev)
857{
858 struct mss_info *mss;
859 int flags = device_get_flags(dev);
860
861 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT);
862 if (!mss) return ENXIO;
863 bzero(mss, sizeof *mss);
864
865 mss->io_rid = 0;
866 mss->conf_rid = -1;
867 mss->irq_rid = 0;
868 mss->drq1_rid = 0;
869 mss->drq2_rid = -1;
870 if (flags & DV_F_DUAL_DMA) {
871 bus_set_resource(dev, SYS_RES_DRQ, 1,
872 flags & DV_F_DRQ_MASK, 1);
873 mss->drq2_rid = 1;
874 }
875 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
876 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
877 return mss_doattach(dev, mss);
878}
879
880static device_method_t mss_methods[] = {
881 /* Device interface */
882 DEVMETHOD(device_probe, mss_probe),
883 DEVMETHOD(device_attach, mss_attach),
884
885 { 0, 0 }
886};
887
888static driver_t mss_driver = {
889 "pcm",
890 mss_methods,
891 sizeof(snddev_info),
892};
893
894DRIVER_MODULE(mss, isa, mss_driver, pcm_devclass, 0, 0);
895
896/*
897 * main irq handler for the CS423x. The OPTi931 code is
898 * a separate one.
899 * The correct way to operate for a device with multiple internal
900 * interrupt sources is to loop on the status register and ack
901 * interrupts until all interrupts are served and none are reported. At
902 * this point the IRQ line to the ISA IRQ controller should go low
903 * and be raised at the next interrupt.
904 *
905 * Since the ISA IRQ controller is sent EOI _before_ passing control
906 * to the isr, it might happen that we serve an interrupt early, in
907 * which case the status register at the next interrupt should just
908 * say that there are no more interrupts...
909 */
910
911static void
912mss_intr(void *arg)
913{
914 struct mss_info *mss = arg;
915 u_char c = 0, served = 0;
916 int i;
917
918 DEB(printf("mss_intr\n"));
919 ad_read(mss, 11); /* fake read of status bits */
920
921 /* loop until there are interrupts, but no more than 10 times. */
922 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
923 /* get exact reason for full-duplex boards */
924 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
925 c &= ~served;
926 if (mss->pch.buffer->dl && (c & 0x10)) {
927 served |= 0x10;
928 chn_intr(mss->pch.channel);
929 }
930 if (mss->rch.buffer->dl && (c & 0x20)) {
931 served |= 0x20;
932 chn_intr(mss->rch.channel);
933 }
934 /* now ack the interrupt */
935 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
936 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
937 }
938 if (i == 10) printf("mss_intr: irq, but not from mss\n");
939 else if (served == 0) {
940 printf("mss_intr: unexpected irq with reason %x\n", c);
941 /*
942 * this should not happen... I have no idea what to do now.
943 * maybe should do a sanity check and restart dmas ?
944 */
945 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
946 }
947}
948
949/*
950 * AD_WAIT_INIT waits if we are initializing the board and
951 * we cannot modify its settings
952 */
953static int
954ad_wait_init(struct mss_info *mss, int x)
955{
956 int arg = x, n = 0; /* to shut up the compiler... */
957 for (; x > 0; x--)
958 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
959 else return n;
960 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
961 return n;
962}
963
964static int
965ad_read(struct mss_info *mss, int reg)
966{
967 u_long flags;
968 int x;
969
970 flags = spltty();
971 ad_wait_init(mss, 201);
972 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
973 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
974 x = io_rd(mss, MSS_IDATA);
975 splx(flags);
976 /* printf("ad_read %d, %x\n", reg, x); */
977 return x;
978}
979
980static void
981ad_write(struct mss_info *mss, int reg, u_char data)
982{
983 u_long flags;
984
985 int x;
986 /* printf("ad_write %d, %x\n", reg, data); */
987 flags = spltty();
988 ad_wait_init(mss, 1002);
989 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
990 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
991 io_wr(mss, MSS_IDATA, data);
992 splx(flags);
993}
994
995static void
996ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
997{
998 ad_write(mss, reg+1, cnt & 0xff);
999 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
1000}
1001
1002static void
1003wait_for_calibration(struct mss_info *mss)
1004{
1005 int n, t;
1006
1007 /*
1008 * Wait until the auto calibration process has finished.
1009 *
1010 * 1) Wait until the chip becomes ready (reads don't return 0x80).
1011 * 2) Wait until the ACI bit of I11 gets on
1012 * 3) Wait until the ACI bit of I11 gets off
1013 */
1014
1015 n = ad_wait_init(mss, 1000);
1016 if (n & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");
1017
| 470 case MD_YM0020:
471 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
472 r6 = conf_rd(mss, OPL3SAx_DMACONF);
473 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
474 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
475 /* yamaha - set volume to max */
476 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
477 conf_wr(mss, OPL3SAx_VOLUMER, 0);
478 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
479 break;
480 }
481 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
482 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
483 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
484 ad_write(mss, 10, 2); /* int enable */
485 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
486 /* the following seem required on the CS4232 */
487 ad_unmute(mss);
488 return 0;
489}
490
491/*
492 * mss_probe() is the probe routine. Note, it is not necessary to
493 * go through this for PnP devices, since they are already
494 * indentified precisely using their PnP id.
495 *
496 * The base address supplied in the device refers to the old MSS
497 * specs where the four 4 registers in io space contain configuration
498 * information. Some boards (as an example, early MSS boards)
499 * has such a block of registers, whereas others (generally CS42xx)
500 * do not. In order to distinguish between the two and do not have
501 * to supply two separate probe routines, the flags entry in isa_device
502 * has a bit to mark this.
503 *
504 */
505
506static int
507mss_probe(device_t dev)
508{
509 u_char tmp, tmpx;
510 int flags, irq, drq, result = ENXIO, setres = 0;
511 struct mss_info *mss;
512
513 if (isa_get_vendorid(dev)) return ENXIO; /* not yet */
514
515 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT);
516 if (!mss) return ENXIO;
517 bzero(mss, sizeof *mss);
518
519 mss->io_rid = 0;
520 mss->conf_rid = -1;
521 mss->irq_rid = 0;
522 mss->drq1_rid = 0;
523 mss->drq2_rid = -1;
524 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
525 0, ~0, 8, RF_ACTIVE);
526 if (!mss->io_base) {
527 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530));
528 mss->io_rid = 0;
529 /* XXX verify this */
530 setres = 1;
531 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
532 0x530, 8);
533 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
534 0, ~0, 8, RF_ACTIVE);
535 }
536 if (!mss->io_base) goto no;
537
538 /* got irq/dma regs? */
539 flags = device_get_flags(dev);
540 irq = isa_get_irq(dev);
541 drq = isa_get_drq(dev);
542
543 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
544
545 /*
546 * Check if the IO port returns valid signature. The original MS
547 * Sound system returns 0x04 while some cards
548 * (AudioTriX Pro for example) return 0x00 or 0x0f.
549 */
550
551 device_set_desc(dev, "MSS");
552 tmpx = tmp = io_rd(mss, 3);
553 if (tmp == 0xff) { /* Bus float */
554 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
555 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
556 goto mss_probe_end;
557 }
558 tmp &= 0x3f;
559 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) {
560 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n",
561 rman_get_start(mss->io_base), tmpx));
562 goto no;
563 }
564 if (irq > 11) {
565 printf("MSS: Bad IRQ %d\n", irq);
566 goto no;
567 }
568 if (!(drq == 0 || drq == 1 || drq == 3)) {
569 printf("MSS: Bad DMA %d\n", drq);
570 goto no;
571 }
572 if (tmpx & 0x80) {
573 /* 8-bit board: only drq1/3 and irq7/9 */
574 if (drq == 0) {
575 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
576 goto no;
577 }
578 if (!(irq == 7 || irq == 9)) {
579 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
580 irq);
581 goto no;
582 }
583 }
584 mss_probe_end:
585 result = mss_detect(dev, mss);
586 no:
587 mss_release_resources(mss, dev);
588#if 0
589 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
590 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
591#endif
592 return result;
593}
594
595static int
596mss_detect(device_t dev, struct mss_info *mss)
597{
598 int i;
599 u_char tmp, tmp1, tmp2;
600 char *name, *yamaha;
601
602 if (mss->bd_id != 0) {
603 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
604 device_get_desc(dev));
605 return 0;
606 }
607
608 name = "AD1848";
609 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
610
611 /*
612 * Check that the I/O address is in use.
613 *
614 * bit 7 of the base I/O port is known to be 0 after the chip has
615 * performed its power on initialization. Just assume this has
616 * happened before the OS is starting.
617 *
618 * If the I/O address is unused, it typically returns 0xff.
619 */
620
621 for (i = 0; i < 10; i++)
622 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
623 else break;
624
625 if (i >= 10) { /* Not a AD1848 */
626 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp));
627 goto no;
628 }
629 /*
630 * Test if it's possible to change contents of the indirect
631 * registers. Registers 0 and 1 are ADC volume registers. The bit
632 * 0x10 is read only so try to avoid using it.
633 */
634
635 ad_write(mss, 0, 0xaa);
636 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
637 tmp1 = ad_read(mss, 0);
638 tmp2 = ad_read(mss, 1);
639 if (tmp1 != 0xaa || tmp2 != 0x45) {
640 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
641 goto no;
642 }
643
644 ad_write(mss, 0, 0x45);
645 ad_write(mss, 1, 0xaa);
646 tmp1 = ad_read(mss, 0);
647 tmp2 = ad_read(mss, 1);
648 if (tmp1 != 0x45 || tmp2 != 0xaa) {
649 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
650 goto no;
651 }
652
653 /*
654 * The indirect register I12 has some read only bits. Lets try to
655 * change them.
656 */
657
658 tmp = ad_read(mss, 12);
659 ad_write(mss, 12, (~tmp) & 0x0f);
660 tmp1 = ad_read(mss, 12);
661
662 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
663 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
664 goto no;
665 }
666
667 /*
668 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
669 * 0x01=RevB
670 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
671 */
672
673 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
674
675 /*
676 * The original AD1848/CS4248 has just 16 indirect registers. This
677 * means that I0 and I16 should return the same value (etc.). Ensure
678 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
679 * with new parts.
680 */
681
682 ad_write(mss, 12, 0); /* Mode2=disabled */
683#if 0
684 for (i = 0; i < 16; i++) {
685 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
686 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
687 i, tmp1, tmp2));
688 /*
689 * note - this seems to fail on the 4232 on I11. So we just break
690 * rather than fail. (which makes this test pointless - cg)
691 */
692 break; /* return 0; */
693 }
694 }
695#endif
696 /*
697 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
698 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
699 *
700 * On the OPTi931, however, I12 is readonly and only contains the
701 * chip revision ID (as in the CS4231A). The upper bits return 0.
702 */
703
704 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
705
706 tmp1 = ad_read(mss, 12);
707 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
708 if ((tmp1 & 0xf0) == 0x00) {
709 BVDDB(printf("this should be an OPTi931\n");)
710 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
711 /*
712 * The 4231 has bit7=1 always, and bit6 we just set to 1.
713 * We want to check that this is really a CS4231
714 * Verify that setting I0 doesn't change I16.
715 */
716 ad_write(mss, 16, 0); /* Set I16 to known value */
717 ad_write(mss, 0, 0x45);
718 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
719
720 ad_write(mss, 0, 0xaa);
721 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
722 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1));
723 goto no;
724 }
725 /* Verify that some bits of I25 are read only. */
726 tmp1 = ad_read(mss, 25); /* Original bits */
727 ad_write(mss, 25, ~tmp1); /* Invert all bits */
728 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
729 int id;
730
731 /* It's at least CS4231 */
732 name = "CS4231";
733 mss->bd_id = MD_CS4231;
734
735 /*
736 * It could be an AD1845 or CS4231A as well.
737 * CS4231 and AD1845 report the same revision info in I25
738 * while the CS4231A reports different.
739 */
740
741 id = ad_read(mss, 25) & 0xe7;
742 /*
743 * b7-b5 = version number;
744 * 100 : all CS4231
745 * 101 : CS4231A
746 *
747 * b2-b0 = chip id;
748 */
749 switch (id) {
750
751 case 0xa0:
752 name = "CS4231A";
753 mss->bd_id = MD_CS4231A;
754 break;
755
756 case 0xa2:
757 name = "CS4232";
758 mss->bd_id = MD_CS4232;
759 break;
760
761 case 0xb2:
762 /* strange: the 4231 data sheet says b4-b3 are XX
763 * so this should be the same as 0xa2
764 */
765 name = "CS4232A";
766 mss->bd_id = MD_CS4232A;
767 break;
768
769 case 0x80:
770 /*
771 * It must be a CS4231 or AD1845. The register I23
772 * of CS4231 is undefined and it appears to be read
773 * only. AD1845 uses I23 for setting sample rate.
774 * Assume the chip is AD1845 if I23 is changeable.
775 */
776
777 tmp = ad_read(mss, 23);
778
779 ad_write(mss, 23, ~tmp);
780 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
781 name = "AD1845";
782 mss->bd_id = MD_AD1845;
783 }
784 ad_write(mss, 23, tmp); /* Restore */
785
786 yamaha = ymf_test(dev, mss);
787 if (yamaha) {
788 mss->bd_id = MD_YM0020;
789 name = yamaha;
790 }
791 break;
792
793 case 0x83: /* CS4236 */
794 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */
795 name = "CS4236";
796 mss->bd_id = MD_CS4236;
797 break;
798
799 default: /* Assume CS4231 */
800 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);)
801 mss->bd_id = MD_CS4231;
802 }
803 }
804 ad_write(mss, 25, tmp1); /* Restore bits */
805gotit:
806 BVDDB(printf("mss_detect() - Detected %s\n", name));
807 device_set_desc(dev, name);
808 device_set_flags(dev,
809 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
810 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
811 return 0;
812no:
813 return ENXIO;
814}
815
816static char *
817ymf_test(device_t dev, struct mss_info *mss)
818{
819 static int ports[] = {0x370, 0x310, 0x538};
820 int p, i, j, version;
821 static char *chipset[] = {
822 NULL, /* 0 */
823 "OPL3-SA2 (YMF711)", /* 1 */
824 "OPL3-SA3 (YMF715)", /* 2 */
825 "OPL3-SA3 (YMF715)", /* 3 */
826 "OPL3-SAx (YMF719)", /* 4 */
827 "OPL3-SAx (YMF719)", /* 5 */
828 "OPL3-SAx (YMF719)", /* 6 */
829 "OPL3-SAx (YMF719)", /* 7 */
830 };
831
832 for (p = 0; p < 3; p++) {
833 mss->conf_rid = 1;
834 mss->conf_base = bus_alloc_resource(dev,
835 SYS_RES_IOPORT,
836 &mss->conf_rid,
837 ports[p], ports[p] + 1, 2,
838 RF_ACTIVE);
839 if (!mss->conf_base) return 0;
840
841 /* Test the index port of the config registers */
842 i = port_rd(mss->conf_base, 0);
843 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
844 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
845 port_wr(mss->conf_base, 0, i);
846 if (!j) {
847 bus_release_resource(dev, SYS_RES_IOPORT,
848 mss->conf_rid, mss->conf_base);
849 mss->conf_base = 0;
850 continue;
851 }
852 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
853 return chipset[version];
854 }
855 return NULL;
856}
857
858static int
859mss_doattach(device_t dev, struct mss_info *mss)
860{
861 snddev_info *d = device_get_softc(dev);
862 void *ih;
863 int flags = device_get_flags(dev);
864 char status[SND_STATUSLEN];
865
866 if (!mss_alloc_resources(mss, dev)) goto no;
867 mss_init(mss, dev);
868 if (flags & DV_F_TRUE_MSS) {
869 /* has IRQ/DMA registers, set IRQ and DMA addr */
870 static char interrupt_bits[12] =
871 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
872 static char pdma_bits[4] = {1, 2, -1, 3};
873 static char valid_rdma[4] = {1, 0, -1, 0};
874 char bits;
875
876 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
877 goto no;
878 io_wr(mss, 0, bits | 0x40); /* config port */
879 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
880 /* Write IRQ+DMA setup */
881 if (pdma_bits[mss->pdma] == -1) goto no;
882 bits |= pdma_bits[mss->pdma];
883 if (mss->pdma != mss->rdma) {
884 if (mss->rdma == valid_rdma[mss->pdma]) bits |= 4;
885 else {
886 printf("invalid dual dma config %d:%d\n",
887 mss->pdma, mss->rdma);
888 goto no;
889 }
890 }
891 io_wr(mss, 0, bits);
892 printf("drq/irq conf %x\n", io_rd(mss, 0));
893 }
894 mixer_init(d, (mss->bd_id == MD_YM0020)? &yamaha_mixer : &mss_mixer, mss);
895 switch (mss->bd_id) {
896 #if NPNP > 0
897 case MD_OPTI931:
898 bus_setup_intr(dev, mss->irq, INTR_TYPE_TTY, opti931_intr, mss, &ih);
899 break;
900 #endif
901 default:
902 bus_setup_intr(dev, mss->irq, INTR_TYPE_TTY, mss_intr, mss, &ih);
903 }
904 if (mss->pdma == mss->rdma)
905 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
906 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
907 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
908 /*highaddr*/BUS_SPACE_MAXADDR,
909 /*filter*/NULL, /*filterarg*/NULL,
910 /*maxsize*/DSP_BUFFSIZE, /*nsegments*/1,
911 /*maxsegz*/0x3ffff,
912 /*flags*/0, &mss->parent_dmat) != 0) {
913 device_printf(dev, "unable to create dma tag\n");
914 goto no;
915 }
916 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d",
917 rman_get_start(mss->io_base), rman_get_start(mss->irq), mss->pdma);
918 if (mss->pdma != mss->rdma) snprintf(status + strlen(status),
919 SND_STATUSLEN - strlen(status), ":%d", mss->rdma);
920
921 if (pcm_register(dev, mss, 1, 1)) goto no;
922 pcm_addchan(dev, PCMDIR_REC, &mss_chantemplate, mss);
923 pcm_addchan(dev, PCMDIR_PLAY, &mss_chantemplate, mss);
924 pcm_setstatus(dev, status);
925
926 return 0;
927no:
928 mss_release_resources(mss, dev);
929 return ENXIO;
930}
931
932static int
933mss_attach(device_t dev)
934{
935 struct mss_info *mss;
936 int flags = device_get_flags(dev);
937
938 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT);
939 if (!mss) return ENXIO;
940 bzero(mss, sizeof *mss);
941
942 mss->io_rid = 0;
943 mss->conf_rid = -1;
944 mss->irq_rid = 0;
945 mss->drq1_rid = 0;
946 mss->drq2_rid = -1;
947 if (flags & DV_F_DUAL_DMA) {
948 bus_set_resource(dev, SYS_RES_DRQ, 1,
949 flags & DV_F_DRQ_MASK, 1);
950 mss->drq2_rid = 1;
951 }
952 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
953 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
954 return mss_doattach(dev, mss);
955}
956
957static device_method_t mss_methods[] = {
958 /* Device interface */
959 DEVMETHOD(device_probe, mss_probe),
960 DEVMETHOD(device_attach, mss_attach),
961
962 { 0, 0 }
963};
964
965static driver_t mss_driver = {
966 "pcm",
967 mss_methods,
968 sizeof(snddev_info),
969};
970
971DRIVER_MODULE(mss, isa, mss_driver, pcm_devclass, 0, 0);
972
973/*
974 * main irq handler for the CS423x. The OPTi931 code is
975 * a separate one.
976 * The correct way to operate for a device with multiple internal
977 * interrupt sources is to loop on the status register and ack
978 * interrupts until all interrupts are served and none are reported. At
979 * this point the IRQ line to the ISA IRQ controller should go low
980 * and be raised at the next interrupt.
981 *
982 * Since the ISA IRQ controller is sent EOI _before_ passing control
983 * to the isr, it might happen that we serve an interrupt early, in
984 * which case the status register at the next interrupt should just
985 * say that there are no more interrupts...
986 */
987
988static void
989mss_intr(void *arg)
990{
991 struct mss_info *mss = arg;
992 u_char c = 0, served = 0;
993 int i;
994
995 DEB(printf("mss_intr\n"));
996 ad_read(mss, 11); /* fake read of status bits */
997
998 /* loop until there are interrupts, but no more than 10 times. */
999 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
1000 /* get exact reason for full-duplex boards */
1001 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
1002 c &= ~served;
1003 if (mss->pch.buffer->dl && (c & 0x10)) {
1004 served |= 0x10;
1005 chn_intr(mss->pch.channel);
1006 }
1007 if (mss->rch.buffer->dl && (c & 0x20)) {
1008 served |= 0x20;
1009 chn_intr(mss->rch.channel);
1010 }
1011 /* now ack the interrupt */
1012 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
1013 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
1014 }
1015 if (i == 10) printf("mss_intr: irq, but not from mss\n");
1016 else if (served == 0) {
1017 printf("mss_intr: unexpected irq with reason %x\n", c);
1018 /*
1019 * this should not happen... I have no idea what to do now.
1020 * maybe should do a sanity check and restart dmas ?
1021 */
1022 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
1023 }
1024}
1025
1026/*
1027 * AD_WAIT_INIT waits if we are initializing the board and
1028 * we cannot modify its settings
1029 */
1030static int
1031ad_wait_init(struct mss_info *mss, int x)
1032{
1033 int arg = x, n = 0; /* to shut up the compiler... */
1034 for (; x > 0; x--)
1035 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
1036 else return n;
1037 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
1038 return n;
1039}
1040
1041static int
1042ad_read(struct mss_info *mss, int reg)
1043{
1044 u_long flags;
1045 int x;
1046
1047 flags = spltty();
1048 ad_wait_init(mss, 201);
1049 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
1050 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
1051 x = io_rd(mss, MSS_IDATA);
1052 splx(flags);
1053 /* printf("ad_read %d, %x\n", reg, x); */
1054 return x;
1055}
1056
1057static void
1058ad_write(struct mss_info *mss, int reg, u_char data)
1059{
1060 u_long flags;
1061
1062 int x;
1063 /* printf("ad_write %d, %x\n", reg, data); */
1064 flags = spltty();
1065 ad_wait_init(mss, 1002);
1066 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
1067 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
1068 io_wr(mss, MSS_IDATA, data);
1069 splx(flags);
1070}
1071
1072static void
1073ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
1074{
1075 ad_write(mss, reg+1, cnt & 0xff);
1076 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
1077}
1078
1079static void
1080wait_for_calibration(struct mss_info *mss)
1081{
1082 int n, t;
1083
1084 /*
1085 * Wait until the auto calibration process has finished.
1086 *
1087 * 1) Wait until the chip becomes ready (reads don't return 0x80).
1088 * 2) Wait until the ACI bit of I11 gets on
1089 * 3) Wait until the ACI bit of I11 gets off
1090 */
1091
1092 n = ad_wait_init(mss, 1000);
1093 if (n & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");
1094
|
1018 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
| 1095 /*
1096 * There is no guarantee that we'll ever see ACI go on,
1097 * calibration may finish before we get here.
1098 *
1099 * XXX Are there docs that even state that it might ever be
1100 * visible off before calibration starts using any chip?
1101 */
1102 if (mss->bd_id == MD_GUSMAX) {
1103 /* 10 ms of busy-waiting is not reasonable normal behavior */
1104 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--)
1105 ;
1106 if (t > 0 && t != 100)
1107 printf("debug: ACI turned on: t = %d\n", t);
1108 } else {
1109 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
1110 }
|
1019 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
1020}
1021
1022static void
1023ad_unmute(struct mss_info *mss)
1024{
1025 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
1026 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
1027}
1028
1029static void
1030ad_enter_MCE(struct mss_info *mss)
1031{
1032 int prev;
1033
1034 mss->bd_flags |= BD_F_MCE_BIT;
1035 ad_wait_init(mss, 203);
1036 prev = io_rd(mss, MSS_INDEX);
1037 prev &= ~MSS_TRD;
1038 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
1039}
1040
1041static void
1042ad_leave_MCE(struct mss_info *mss)
1043{
1044 u_long flags;
1045 u_char prev;
1046
1047 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
1048 printf("--- hey, leave_MCE: MCE bit was not set!\n");
1049 return;
1050 }
1051
1052 ad_wait_init(mss, 1000);
1053
1054 flags = spltty();
1055 mss->bd_flags &= ~BD_F_MCE_BIT;
1056
1057 prev = io_rd(mss, MSS_INDEX);
1058 prev &= ~MSS_TRD;
1059 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
1060 wait_for_calibration(mss);
1061 splx(flags);
1062}
1063
1064/*
1065 * only one source can be set...
1066 */
1067static int
1068mss_set_recsrc(struct mss_info *mss, int mask)
1069{
1070 u_char recdev;
1071
1072 switch (mask) {
1073 case SOUND_MASK_LINE:
1074 case SOUND_MASK_LINE3:
1075 recdev = 0;
1076 break;
1077
1078 case SOUND_MASK_CD:
1079 case SOUND_MASK_LINE1:
1080 recdev = 0x40;
1081 break;
1082
1083 case SOUND_MASK_IMIX:
1084 recdev = 0xc0;
1085 break;
1086
1087 case SOUND_MASK_MIC:
1088 default:
1089 mask = SOUND_MASK_MIC;
1090 recdev = 0x80;
1091 }
1092 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
1093 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
1094 return mask;
1095}
1096
1097/* there are differences in the mixer depending on the actual sound card. */
1098static int
1099mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
1100{
1101 int regoffs;
1102 mixer_tab *mix_d = (mss->bd_id == MD_OPTI931)? &opti931_devices : &mix_devices;
1103 u_char old, val;
1104
1105 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
1106 DEB(printf("nbits = 0 for dev %d\n", dev));
1107 return -1;
1108 }
1109
1110 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
1111
1112 /* Set the left channel */
1113
1114 regoffs = (*mix_d)[dev][LEFT_CHN].regno;
1115 old = val = ad_read(mss, regoffs);
1116 /* if volume is 0, mute chan. Otherwise, unmute. */
1117 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
1118 change_bits(mix_d, &val, dev, LEFT_CHN, left);
1119 ad_write(mss, regoffs, val);
1120
1121 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
1122 dev, regoffs, old, val));
1123
1124 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
1125 /* Set the right channel */
1126 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
1127 old = val = ad_read(mss, regoffs);
1128 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
1129 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
1130 ad_write(mss, regoffs, val);
1131
1132 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
1133 dev, regoffs, old, val));
1134 }
1135 return 0; /* success */
1136}
1137
1138static int
1139mss_speed(struct mss_chinfo *ch, int speed)
1140{
1141 struct mss_info *mss = ch->parent;
1142 /*
1143 * In the CS4231, the low 4 bits of I8 are used to hold the
1144 * sample rate. Only a fixed number of values is allowed. This
1145 * table lists them. The speed-setting routines scans the table
1146 * looking for the closest match. This is the only supported method.
1147 *
1148 * In the CS4236, there is an alternate metod (which we do not
1149 * support yet) which provides almost arbitrary frequency setting.
1150 * In the AD1845, it looks like the sample rate can be
1151 * almost arbitrary, and written directly to a register.
1152 * In the OPTi931, there is a SB command which provides for
1153 * almost arbitrary frequency setting.
1154 *
1155 */
1156 ad_enter_MCE(mss);
1157 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
1158 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
1159 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
1160 /* XXX must also do something in I27 for the ad1845 */
1161 } else {
1162 int i, sel = 0; /* assume entry 0 does not contain -1 */
1163 static int speeds[] =
1164 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
1165 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
1166
1167 for (i = 1; i < 16; i++)
1168 if (speeds[i] > 0 &&
1169 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
1170 speed = speeds[sel];
1171 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
1172 }
1173 ad_leave_MCE(mss);
1174
1175 return speed;
1176}
1177
1178/*
1179 * mss_format checks that the format is supported (or defaults to AFMT_U8)
1180 * and returns the bit setting for the 1848 register corresponding to
1181 * the desired format.
1182 *
1183 * fixed lr970724
1184 */
1185
1186static int
1187mss_format(struct mss_chinfo *ch, u_int32_t format)
1188{
1189 struct mss_info *mss = ch->parent;
1190 int i, arg = format & ~AFMT_STEREO;
1191
1192 /*
1193 * The data format uses 3 bits (just 2 on the 1848). For each
1194 * bit setting, the following array returns the corresponding format.
1195 * The code scans the array looking for a suitable format. In
1196 * case it is not found, default to AFMT_U8 (not such a good
1197 * choice, but let's do it for compatibility...).
1198 */
1199
1200 static int fmts[] =
1201 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
1202 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
1203
1204 for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
1205 arg = i << 1;
1206 if (format & AFMT_STEREO) arg |= 1;
1207 arg <<= 4;
1208 ad_enter_MCE(mss);
1209 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
1210 if (FULL_DUPLEX(mss)) ad_write(mss, 28, arg); /* capture mode */
1211 ad_leave_MCE(mss);
1212 return format;
1213}
1214
1215static int
1216mss_trigger(struct mss_chinfo *ch, int go)
1217{
1218 struct mss_info *mss = ch->parent;
1219 u_char m;
1220 int retry, wr, cnt;
1221
1222 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
1223 m = ad_read(mss, 9);
1224 switch (go) {
1225 case PCMTRIG_START:
1226 cnt = (ch->buffer->dl / ch->buffer->sample_size) - 1;
1227
1228 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m););
1229 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
1230 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1231 break;
1232
1233 case PCMTRIG_STOP:
1234 case PCMTRIG_ABORT: /* XXX check this... */
1235 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
1236#if 0
1237 /*
1238 * try to disable DMA by clearing count registers. Not sure it
1239 * is needed, and it might cause false interrupts when the
1240 * DMA is re-enabled later.
1241 */
1242 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1243#endif
1244 }
1245 /* on the OPTi931 the enable bit seems hard to set... */
1246 for (retry = 10; retry > 0; retry--) {
1247 ad_write(mss, 9, m);
1248 if (ad_read(mss, 9) == m) break;
1249 }
1250 if (retry == 0) printf("start dma, failed to set bit 0x%02x 0x%02x\n",
1251 m, ad_read(mss, 9));
1252 return 0;
1253}
1254
1255#if NPNP > 0
1256static int
1257pnpmss_probe(device_t dev)
1258{
1259 char *s = NULL;
1260 u_int32_t logical_id = isa_get_logicalid(dev);
1261 u_int32_t vend_id = isa_get_vendorid(dev);
1262 u_int32_t id = vend_id & 0xff00ffff;
1263
1264 switch (logical_id) {
1265 case 0x0000630e: /* CSC0000 */
1266 if (id == 0x3700630e) s = "CS4237";
1267 else if (id == 0x2500630e) s = "CS4235";
1268 else if (id == 0x3600630e) s = "CS4236";
1269 else if (id == 0x3500630e) s = "CS4236B";
1270 else if (id == 0x3200630e) s = "CS4232";
1271 else s = "Unknown CS";
1272 break;
1273
1274 case 0x2100a865: /* YMH0021 */
1275 if (id == 0x2000a865) s = "Yamaha SA2";
1276 else if (id == 0x3000a865) s = "Yamaha SA3";
1277 else if (id == 0x0000a865) s = "Yamaha YMF719 OPL-SA3";
1278 else s = "Yamaha OPL-SAx";
1279 break;
1280
1281 case 0x1110d315: /* ENS1011 */
1282 s = "ENSONIQ SoundscapeVIVO";
1283 break;
1284
1285 case 0x1093143e: /* OPT9310 */
1286 s = "OPTi931";
1287 break;
1288
1289 case 0x5092143e: /* OPT9250 XXX guessing */
1290 s = "OPTi925";
1291 break;
1292
| 1111 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
1112}
1113
1114static void
1115ad_unmute(struct mss_info *mss)
1116{
1117 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
1118 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
1119}
1120
1121static void
1122ad_enter_MCE(struct mss_info *mss)
1123{
1124 int prev;
1125
1126 mss->bd_flags |= BD_F_MCE_BIT;
1127 ad_wait_init(mss, 203);
1128 prev = io_rd(mss, MSS_INDEX);
1129 prev &= ~MSS_TRD;
1130 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
1131}
1132
1133static void
1134ad_leave_MCE(struct mss_info *mss)
1135{
1136 u_long flags;
1137 u_char prev;
1138
1139 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
1140 printf("--- hey, leave_MCE: MCE bit was not set!\n");
1141 return;
1142 }
1143
1144 ad_wait_init(mss, 1000);
1145
1146 flags = spltty();
1147 mss->bd_flags &= ~BD_F_MCE_BIT;
1148
1149 prev = io_rd(mss, MSS_INDEX);
1150 prev &= ~MSS_TRD;
1151 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
1152 wait_for_calibration(mss);
1153 splx(flags);
1154}
1155
1156/*
1157 * only one source can be set...
1158 */
1159static int
1160mss_set_recsrc(struct mss_info *mss, int mask)
1161{
1162 u_char recdev;
1163
1164 switch (mask) {
1165 case SOUND_MASK_LINE:
1166 case SOUND_MASK_LINE3:
1167 recdev = 0;
1168 break;
1169
1170 case SOUND_MASK_CD:
1171 case SOUND_MASK_LINE1:
1172 recdev = 0x40;
1173 break;
1174
1175 case SOUND_MASK_IMIX:
1176 recdev = 0xc0;
1177 break;
1178
1179 case SOUND_MASK_MIC:
1180 default:
1181 mask = SOUND_MASK_MIC;
1182 recdev = 0x80;
1183 }
1184 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
1185 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
1186 return mask;
1187}
1188
1189/* there are differences in the mixer depending on the actual sound card. */
1190static int
1191mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
1192{
1193 int regoffs;
1194 mixer_tab *mix_d = (mss->bd_id == MD_OPTI931)? &opti931_devices : &mix_devices;
1195 u_char old, val;
1196
1197 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
1198 DEB(printf("nbits = 0 for dev %d\n", dev));
1199 return -1;
1200 }
1201
1202 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
1203
1204 /* Set the left channel */
1205
1206 regoffs = (*mix_d)[dev][LEFT_CHN].regno;
1207 old = val = ad_read(mss, regoffs);
1208 /* if volume is 0, mute chan. Otherwise, unmute. */
1209 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
1210 change_bits(mix_d, &val, dev, LEFT_CHN, left);
1211 ad_write(mss, regoffs, val);
1212
1213 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
1214 dev, regoffs, old, val));
1215
1216 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
1217 /* Set the right channel */
1218 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
1219 old = val = ad_read(mss, regoffs);
1220 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
1221 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
1222 ad_write(mss, regoffs, val);
1223
1224 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
1225 dev, regoffs, old, val));
1226 }
1227 return 0; /* success */
1228}
1229
1230static int
1231mss_speed(struct mss_chinfo *ch, int speed)
1232{
1233 struct mss_info *mss = ch->parent;
1234 /*
1235 * In the CS4231, the low 4 bits of I8 are used to hold the
1236 * sample rate. Only a fixed number of values is allowed. This
1237 * table lists them. The speed-setting routines scans the table
1238 * looking for the closest match. This is the only supported method.
1239 *
1240 * In the CS4236, there is an alternate metod (which we do not
1241 * support yet) which provides almost arbitrary frequency setting.
1242 * In the AD1845, it looks like the sample rate can be
1243 * almost arbitrary, and written directly to a register.
1244 * In the OPTi931, there is a SB command which provides for
1245 * almost arbitrary frequency setting.
1246 *
1247 */
1248 ad_enter_MCE(mss);
1249 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
1250 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
1251 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
1252 /* XXX must also do something in I27 for the ad1845 */
1253 } else {
1254 int i, sel = 0; /* assume entry 0 does not contain -1 */
1255 static int speeds[] =
1256 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
1257 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
1258
1259 for (i = 1; i < 16; i++)
1260 if (speeds[i] > 0 &&
1261 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
1262 speed = speeds[sel];
1263 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
1264 }
1265 ad_leave_MCE(mss);
1266
1267 return speed;
1268}
1269
1270/*
1271 * mss_format checks that the format is supported (or defaults to AFMT_U8)
1272 * and returns the bit setting for the 1848 register corresponding to
1273 * the desired format.
1274 *
1275 * fixed lr970724
1276 */
1277
1278static int
1279mss_format(struct mss_chinfo *ch, u_int32_t format)
1280{
1281 struct mss_info *mss = ch->parent;
1282 int i, arg = format & ~AFMT_STEREO;
1283
1284 /*
1285 * The data format uses 3 bits (just 2 on the 1848). For each
1286 * bit setting, the following array returns the corresponding format.
1287 * The code scans the array looking for a suitable format. In
1288 * case it is not found, default to AFMT_U8 (not such a good
1289 * choice, but let's do it for compatibility...).
1290 */
1291
1292 static int fmts[] =
1293 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
1294 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
1295
1296 for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
1297 arg = i << 1;
1298 if (format & AFMT_STEREO) arg |= 1;
1299 arg <<= 4;
1300 ad_enter_MCE(mss);
1301 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
1302 if (FULL_DUPLEX(mss)) ad_write(mss, 28, arg); /* capture mode */
1303 ad_leave_MCE(mss);
1304 return format;
1305}
1306
1307static int
1308mss_trigger(struct mss_chinfo *ch, int go)
1309{
1310 struct mss_info *mss = ch->parent;
1311 u_char m;
1312 int retry, wr, cnt;
1313
1314 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
1315 m = ad_read(mss, 9);
1316 switch (go) {
1317 case PCMTRIG_START:
1318 cnt = (ch->buffer->dl / ch->buffer->sample_size) - 1;
1319
1320 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m););
1321 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
1322 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1323 break;
1324
1325 case PCMTRIG_STOP:
1326 case PCMTRIG_ABORT: /* XXX check this... */
1327 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
1328#if 0
1329 /*
1330 * try to disable DMA by clearing count registers. Not sure it
1331 * is needed, and it might cause false interrupts when the
1332 * DMA is re-enabled later.
1333 */
1334 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1335#endif
1336 }
1337 /* on the OPTi931 the enable bit seems hard to set... */
1338 for (retry = 10; retry > 0; retry--) {
1339 ad_write(mss, 9, m);
1340 if (ad_read(mss, 9) == m) break;
1341 }
1342 if (retry == 0) printf("start dma, failed to set bit 0x%02x 0x%02x\n",
1343 m, ad_read(mss, 9));
1344 return 0;
1345}
1346
1347#if NPNP > 0
1348static int
1349pnpmss_probe(device_t dev)
1350{
1351 char *s = NULL;
1352 u_int32_t logical_id = isa_get_logicalid(dev);
1353 u_int32_t vend_id = isa_get_vendorid(dev);
1354 u_int32_t id = vend_id & 0xff00ffff;
1355
1356 switch (logical_id) {
1357 case 0x0000630e: /* CSC0000 */
1358 if (id == 0x3700630e) s = "CS4237";
1359 else if (id == 0x2500630e) s = "CS4235";
1360 else if (id == 0x3600630e) s = "CS4236";
1361 else if (id == 0x3500630e) s = "CS4236B";
1362 else if (id == 0x3200630e) s = "CS4232";
1363 else s = "Unknown CS";
1364 break;
1365
1366 case 0x2100a865: /* YMH0021 */
1367 if (id == 0x2000a865) s = "Yamaha SA2";
1368 else if (id == 0x3000a865) s = "Yamaha SA3";
1369 else if (id == 0x0000a865) s = "Yamaha YMF719 OPL-SA3";
1370 else s = "Yamaha OPL-SAx";
1371 break;
1372
1373 case 0x1110d315: /* ENS1011 */
1374 s = "ENSONIQ SoundscapeVIVO";
1375 break;
1376
1377 case 0x1093143e: /* OPT9310 */
1378 s = "OPTi931";
1379 break;
1380
1381 case 0x5092143e: /* OPT9250 XXX guessing */
1382 s = "OPTi925";
1383 break;
1384
|
| 1385#if 0
|
1293 case 0x0000561e:
1294 s = "GusPnP";
1295 break;
| 1386 case 0x0000561e:
1387 s = "GusPnP";
1388 break;
|
| 1389#endif
|
1296
1297 case 0x01000000:
1298 if (vend_id == 0x0100a90d) s = "CMI8330";
1299 break;
1300 }
1301
1302 if (s) {
1303 device_set_desc(dev, s);
1304 return 0;
1305 }
1306 return ENXIO;
1307}
1308
1309static int
1310pnpmss_attach(device_t dev)
1311{
1312 struct mss_info *mss;
1313 u_int32_t vend_id = isa_get_vendorid(dev);
1314
1315 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT);
1316 if (!mss) return ENXIO;
1317 bzero(mss, sizeof *mss);
1318
1319 mss->io_rid = 0;
1320 mss->conf_rid = -1;
1321 mss->irq_rid = 0;
1322 mss->drq1_rid = 0;
1323 mss->drq2_rid = 1;
1324
1325 switch (vend_id & 0xff00ffff) {
1326 case 0x2000a865: /* Yamaha SA2 */
1327 case 0x3000a865: /* Yamaha SA3 */
1328 case 0x0000a865: /* Yamaha YMF719 SA3 */
1329 case 0x2100a865: /* pnpbios sets vendor=logical */
1330 mss->io_rid = 1;
1331 mss->conf_rid = 4;
1332 mss->bd_id = MD_YM0020;
1333 break;
1334
1335 case 0x8100d315: /* ENSONIQ SoundscapeVIVO */
1336 mss->io_rid = 1;
1337 mss->bd_id = MD_VIVO;
1338 break;
1339
1340 case 0x3700630e: /* CS4237 */
1341 case 0x2500630e: /* AOpen AW37, CS4235 */
1342 mss->bd_flags |= BD_F_MSS_OFFSET;
1343 mss->bd_id = MD_CS4237;
1344 break;
1345
1346 case 0x3500630e: /* CS4236B */
1347 case 0x3600630e: /* CS4236 */
1348 mss->bd_flags |= BD_F_MSS_OFFSET;
1349 mss->bd_id = MD_CS4236;
1350 break;
1351
1352 case 0x3100143e: /* opti931 */
1353 mss->bd_flags |= BD_F_MSS_OFFSET;
1354 mss->conf_rid = 3;
1355 mss->bd_id = MD_OPTI931;
1356 break;
1357
1358 case 0x2500143e: /* opti925 */
1359 mss->io_rid = 1;
1360 mss->conf_rid = 3;
1361 mss->bd_id = MD_OPTI925;
1362 break;
1363
| 1390
1391 case 0x01000000:
1392 if (vend_id == 0x0100a90d) s = "CMI8330";
1393 break;
1394 }
1395
1396 if (s) {
1397 device_set_desc(dev, s);
1398 return 0;
1399 }
1400 return ENXIO;
1401}
1402
1403static int
1404pnpmss_attach(device_t dev)
1405{
1406 struct mss_info *mss;
1407 u_int32_t vend_id = isa_get_vendorid(dev);
1408
1409 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT);
1410 if (!mss) return ENXIO;
1411 bzero(mss, sizeof *mss);
1412
1413 mss->io_rid = 0;
1414 mss->conf_rid = -1;
1415 mss->irq_rid = 0;
1416 mss->drq1_rid = 0;
1417 mss->drq2_rid = 1;
1418
1419 switch (vend_id & 0xff00ffff) {
1420 case 0x2000a865: /* Yamaha SA2 */
1421 case 0x3000a865: /* Yamaha SA3 */
1422 case 0x0000a865: /* Yamaha YMF719 SA3 */
1423 case 0x2100a865: /* pnpbios sets vendor=logical */
1424 mss->io_rid = 1;
1425 mss->conf_rid = 4;
1426 mss->bd_id = MD_YM0020;
1427 break;
1428
1429 case 0x8100d315: /* ENSONIQ SoundscapeVIVO */
1430 mss->io_rid = 1;
1431 mss->bd_id = MD_VIVO;
1432 break;
1433
1434 case 0x3700630e: /* CS4237 */
1435 case 0x2500630e: /* AOpen AW37, CS4235 */
1436 mss->bd_flags |= BD_F_MSS_OFFSET;
1437 mss->bd_id = MD_CS4237;
1438 break;
1439
1440 case 0x3500630e: /* CS4236B */
1441 case 0x3600630e: /* CS4236 */
1442 mss->bd_flags |= BD_F_MSS_OFFSET;
1443 mss->bd_id = MD_CS4236;
1444 break;
1445
1446 case 0x3100143e: /* opti931 */
1447 mss->bd_flags |= BD_F_MSS_OFFSET;
1448 mss->conf_rid = 3;
1449 mss->bd_id = MD_OPTI931;
1450 break;
1451
1452 case 0x2500143e: /* opti925 */
1453 mss->io_rid = 1;
1454 mss->conf_rid = 3;
1455 mss->bd_id = MD_OPTI925;
1456 break;
1457
|
| 1458#if 0
|
1364 case 0x0100561e: /* guspnp */
1365 mss->bd_flags |= BD_F_MSS_OFFSET;
1366 mss->io_rid = 2;
1367 mss->conf_rid = 1;
1368 mss->drq1_rid = 1;
1369 mss->drq2_rid = 0;
1370 mss->bd_id = MD_GUSPNP;
1371 break;
| 1459 case 0x0100561e: /* guspnp */
1460 mss->bd_flags |= BD_F_MSS_OFFSET;
1461 mss->io_rid = 2;
1462 mss->conf_rid = 1;
1463 mss->drq1_rid = 1;
1464 mss->drq2_rid = 0;
1465 mss->bd_id = MD_GUSPNP;
1466 break;
|
| 1467#endif
|
1372
1373 default:
1374 mss->bd_flags |= BD_F_MSS_OFFSET;
1375 mss->bd_id = MD_CS4232;
1376 break;
1377 }
1378 return mss_doattach(dev, mss);
1379}
1380
1381static device_method_t pnpmss_methods[] = {
1382 /* Device interface */
1383 DEVMETHOD(device_probe, pnpmss_probe),
1384 DEVMETHOD(device_attach, pnpmss_attach),
1385
1386 { 0, 0 }
1387};
1388
1389static driver_t pnpmss_driver = {
1390 "pcm",
1391 pnpmss_methods,
1392 sizeof(snddev_info),
1393};
1394
1395DRIVER_MODULE(pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
1396
1397/*
1398 * the opti931 seems to miss interrupts when working in full
1399 * duplex, so we try some heuristics to catch them.
1400 */
1401static void
1402opti931_intr(void *arg)
1403{
1404 struct mss_info *mss = (struct mss_info *)arg;
1405 u_char masked = 0, i11, mc11, c = 0;
1406 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
1407 int loops = 10;
1408
1409#if 0
1410 reason = io_rd(mss, MSS_STATUS);
1411 if (!(reason & 1)) {/* no int, maybe a shared line ? */
1412 printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11));
1413 return;
1414 }
1415#endif
1416 i11 = ad_read(mss, 11); /* XXX what's for ? */
1417 again:
1418
1419 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1420 mc11 &= 0x0c;
1421 if (c & 0x10) {
1422 DEB(printf("Warning: CD interrupt\n");)
1423 mc11 |= 0x10;
1424 }
1425 if (c & 0x20) {
1426 DEB(printf("Warning: MPU interrupt\n");)
1427 mc11 |= 0x20;
1428 }
1429 if (mc11 & masked) printf("irq reset failed, mc11 0x%02x, 0x%02x\n",
1430 mc11, masked);
1431 masked |= mc11;
1432 /*
1433 * the nice OPTi931 sets the IRQ line before setting the bits in
1434 * mc11. So, on some occasions I have to retry (max 10 times).
1435 */
1436 if (mc11 == 0) { /* perhaps can return ... */
1437 reason = io_rd(mss, MSS_STATUS);
1438 if (reason & 1) {
1439 DEB(printf("one more try...\n");)
1440 if (--loops) goto again;
1441 else DDB(printf("intr, but mc11 not set\n");)
1442 }
1443 if (loops == 0) printf("intr, nothing in mcir11 0x%02x\n", mc11);
1444 return;
1445 }
1446
1447 if (mss->rch.buffer->dl && (mc11 & 8)) chn_intr(mss->rch.channel);
1448 if (mss->pch.buffer->dl && (mc11 & 4)) chn_intr(mss->pch.channel);
1449 opti_wr(mss, 11, ~mc11); /* ack */
1450 if (--loops) goto again;
1451 DEB(printf("xxx too many loops\n");)
1452}
1453
1454#endif /* NPNP > 0 */
1455
| 1468
1469 default:
1470 mss->bd_flags |= BD_F_MSS_OFFSET;
1471 mss->bd_id = MD_CS4232;
1472 break;
1473 }
1474 return mss_doattach(dev, mss);
1475}
1476
1477static device_method_t pnpmss_methods[] = {
1478 /* Device interface */
1479 DEVMETHOD(device_probe, pnpmss_probe),
1480 DEVMETHOD(device_attach, pnpmss_attach),
1481
1482 { 0, 0 }
1483};
1484
1485static driver_t pnpmss_driver = {
1486 "pcm",
1487 pnpmss_methods,
1488 sizeof(snddev_info),
1489};
1490
1491DRIVER_MODULE(pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
1492
1493/*
1494 * the opti931 seems to miss interrupts when working in full
1495 * duplex, so we try some heuristics to catch them.
1496 */
1497static void
1498opti931_intr(void *arg)
1499{
1500 struct mss_info *mss = (struct mss_info *)arg;
1501 u_char masked = 0, i11, mc11, c = 0;
1502 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
1503 int loops = 10;
1504
1505#if 0
1506 reason = io_rd(mss, MSS_STATUS);
1507 if (!(reason & 1)) {/* no int, maybe a shared line ? */
1508 printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11));
1509 return;
1510 }
1511#endif
1512 i11 = ad_read(mss, 11); /* XXX what's for ? */
1513 again:
1514
1515 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1516 mc11 &= 0x0c;
1517 if (c & 0x10) {
1518 DEB(printf("Warning: CD interrupt\n");)
1519 mc11 |= 0x10;
1520 }
1521 if (c & 0x20) {
1522 DEB(printf("Warning: MPU interrupt\n");)
1523 mc11 |= 0x20;
1524 }
1525 if (mc11 & masked) printf("irq reset failed, mc11 0x%02x, 0x%02x\n",
1526 mc11, masked);
1527 masked |= mc11;
1528 /*
1529 * the nice OPTi931 sets the IRQ line before setting the bits in
1530 * mc11. So, on some occasions I have to retry (max 10 times).
1531 */
1532 if (mc11 == 0) { /* perhaps can return ... */
1533 reason = io_rd(mss, MSS_STATUS);
1534 if (reason & 1) {
1535 DEB(printf("one more try...\n");)
1536 if (--loops) goto again;
1537 else DDB(printf("intr, but mc11 not set\n");)
1538 }
1539 if (loops == 0) printf("intr, nothing in mcir11 0x%02x\n", mc11);
1540 return;
1541 }
1542
1543 if (mss->rch.buffer->dl && (mc11 & 8)) chn_intr(mss->rch.channel);
1544 if (mss->pch.buffer->dl && (mc11 & 4)) chn_intr(mss->pch.channel);
1545 opti_wr(mss, 11, ~mc11); /* ack */
1546 if (--loops) goto again;
1547 DEB(printf("xxx too many loops\n");)
1548}
1549
1550#endif /* NPNP > 0 */
1551
|
| 1552#if NGUSC > 0
1553
|
1456static int
| 1554static int
|
| 1555guspcm_probe(device_t dev)
1556{
1557 struct sndcard_func *func;
1558
1559 func = device_get_ivars(dev);
1560 if (func == NULL || func->func != SCF_PCM)
1561 return ENXIO;
1562
1563 device_set_desc(dev, "GUS CS4231");
1564 return 0;
1565}
1566
1567static int
1568guspcm_attach(device_t dev)
1569{
1570 device_t parent = device_get_parent(dev);
1571 struct mss_info *mss;
1572 int base, flags;
1573 unsigned char ctl;
1574
1575 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT);
1576 if (mss == NULL)
1577 return ENOMEM;
1578 bzero(mss, sizeof *mss);
1579
1580 mss->bd_flags = BD_F_MSS_OFFSET;
1581 mss->io_rid = 2;
1582 mss->conf_rid = 1;
1583 mss->irq_rid = 0;
1584 mss->drq1_rid = 1;
1585 mss->drq2_rid = -1;
1586
1587 if (isa_get_vendorid(parent) == 0)
1588 mss->bd_id = MD_GUSMAX;
1589 else {
1590 mss->bd_id = MD_GUSPNP;
1591 mss->drq2_rid = 0;
1592 goto skip_setup;
1593 }
1594
1595 flags = device_get_flags(parent);
1596 if (flags & DV_F_DUAL_DMA)
1597 mss->drq2_rid = 0;
1598
1599 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
1600 0, ~0, 8, RF_ACTIVE);
1601
1602 if (mss->conf_base == NULL) {
1603 mss_release_resources(mss, dev);
1604 return ENXIO;
1605 }
1606
1607 base = isa_get_port(parent);
1608
1609 ctl = 0x40; /* CS4231 enable */
1610 if (isa_get_drq(dev) > 3)
1611 ctl |= 0x10; /* 16-bit dma channel 1 */
1612 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
1613 ctl |= 0x20; /* 16-bit dma channel 2 */
1614 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */
1615 port_wr(mss->conf_base, 6, ctl);
1616
1617skip_setup:
1618 return mss_doattach(dev, mss);
1619}
1620
1621static device_method_t guspcm_methods[] = {
1622 DEVMETHOD(device_probe, guspcm_probe),
1623 DEVMETHOD(device_attach, guspcm_attach),
1624
1625 { 0, 0 }
1626};
1627
1628static driver_t guspcm_driver = {
1629 "pcm",
1630 guspcm_methods,
1631 sizeof(snddev_info),
1632};
1633
1634DRIVER_MODULE(guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0);
1635#endif /* NGUSC > 0 */
1636
1637static int
|
1457mssmix_init(snd_mixer *m)
1458{
1459 struct mss_info *mss = mix_getdevinfo(m);
1460
1461 mix_setdevs(m, MODE2_MIXER_DEVICES);
1462 mix_setrecdevs(m, MSS_REC_DEVICES);
1463 switch(mss->bd_id) {
1464 case MD_OPTI931:
1465 mix_setdevs(m, OPTI931_MIXER_DEVICES);
1466 ad_write(mss, 20, 0x88);
1467 ad_write(mss, 21, 0x88);
1468 break;
1469
1470 case MD_AD1848:
1471 mix_setdevs(m, MODE1_MIXER_DEVICES);
1472 break;
1473
1474 case MD_GUSPNP:
| 1638mssmix_init(snd_mixer *m)
1639{
1640 struct mss_info *mss = mix_getdevinfo(m);
1641
1642 mix_setdevs(m, MODE2_MIXER_DEVICES);
1643 mix_setrecdevs(m, MSS_REC_DEVICES);
1644 switch(mss->bd_id) {
1645 case MD_OPTI931:
1646 mix_setdevs(m, OPTI931_MIXER_DEVICES);
1647 ad_write(mss, 20, 0x88);
1648 ad_write(mss, 21, 0x88);
1649 break;
1650
1651 case MD_AD1848:
1652 mix_setdevs(m, MODE1_MIXER_DEVICES);
1653 break;
1654
1655 case MD_GUSPNP:
|
| 1656 case MD_GUSMAX:
|
1475 /* this is only necessary in mode 3 ... */
1476 ad_write(mss, 22, 0x88);
1477 ad_write(mss, 23, 0x88);
1478 break;
1479 }
1480 return 0;
1481}
1482
1483static int
1484mssmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right)
1485{
1486 struct mss_info *mss = mix_getdevinfo(m);
1487
1488 mss_mixer_set(mss, dev, left, right);
1489
1490 return left | (right << 8);
1491}
1492
1493static int
1494mssmix_setrecsrc(snd_mixer *m, u_int32_t src)
1495{
1496 struct mss_info *mss = mix_getdevinfo(m);
1497
1498 src = mss_set_recsrc(mss, src);
1499 return src;
1500}
1501
1502static int
1503ymmix_init(snd_mixer *m)
1504{
1505 struct mss_info *mss = mix_getdevinfo(m);
1506
1507 mssmix_init(m);
1508 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC);
1509 /* Set master volume */
1510 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
1511 conf_wr(mss, OPL3SAx_VOLUMER, 7);
1512
1513 return 0;
1514}
1515
1516static int
1517ymmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right)
1518{
1519 struct mss_info *mss = mix_getdevinfo(m);
1520 int t;
1521
1522 switch (dev) {
1523 case SOUND_MIXER_VOLUME:
1524 if (left) t = 15 - (left * 15) / 100;
1525 else t = 0x80; /* mute */
1526 conf_wr(mss, OPL3SAx_VOLUMEL, t);
1527 if (right) t = 15 - (right * 15) / 100;
1528 else t = 0x80; /* mute */
1529 conf_wr(mss, OPL3SAx_VOLUMER, t);
1530 break;
1531
1532 case SOUND_MIXER_MIC:
1533 t = left;
1534 if (left) t = 31 - (left * 31) / 100;
1535 else t = 0x80; /* mute */
1536 conf_wr(mss, OPL3SAx_MIC, t);
1537 break;
1538
1539 case SOUND_MIXER_BASS:
1540 case SOUND_MIXER_TREBLE:
1541 /* Later maybe */
1542
1543 default:
1544 mss_mixer_set(mss, dev, left, right);
1545 }
1546
1547 return left | (right << 8);
1548}
1549
1550static int
1551ymmix_setrecsrc(snd_mixer *m, u_int32_t src)
1552{
1553 struct mss_info *mss = mix_getdevinfo(m);
1554 src = mss_set_recsrc(mss, src);
1555 return src;
1556}
1557
1558/* channel interface */
1559static void *
1560msschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
1561{
1562 struct mss_info *mss = devinfo;
1563 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1564
1565 ch->parent = mss;
1566 ch->channel = c;
1567 ch->buffer = b;
1568 ch->buffer->bufsize = DSP_BUFFSIZE;
1569 if (chn_allocbuf(ch->buffer, mss->parent_dmat) == -1) return NULL;
1570 return ch;
1571}
1572
1573static int
1574msschan_setdir(void *data, int dir)
1575{
1576 struct mss_chinfo *ch = data;
1577
1578 ch->buffer->chan = (dir == PCMDIR_PLAY)? ch->parent->pdma : ch->parent->rdma;
1579 ch->dir = dir;
1580 return 0;
1581}
1582
1583static int
1584msschan_setformat(void *data, u_int32_t format)
1585{
1586 struct mss_chinfo *ch = data;
1587
1588 mss_format(ch, format);
1589 return 0;
1590}
1591
1592static int
1593msschan_setspeed(void *data, u_int32_t speed)
1594{
1595 struct mss_chinfo *ch = data;
1596
1597 return mss_speed(ch, speed);
1598}
1599
1600static int
1601msschan_setblocksize(void *data, u_int32_t blocksize)
1602{
1603 return blocksize;
1604}
1605
1606static int
1607msschan_trigger(void *data, int go)
1608{
1609 struct mss_chinfo *ch = data;
1610
1611 buf_isadma(ch->buffer, go);
1612 mss_trigger(ch, go);
1613 return 0;
1614}
1615
1616static int
1617msschan_getptr(void *data)
1618{
1619 struct mss_chinfo *ch = data;
1620 return buf_isadmaptr(ch->buffer);
1621}
1622
1623static pcmchan_caps *
1624msschan_getcaps(void *data)
1625{
1626 struct mss_chinfo *ch = data;
1627
1628 switch(ch->parent->bd_id) {
1629 case MD_OPTI931:
1630 return &opti931_caps;
1631 break;
1632
1633 case MD_GUSPNP:
| 1657 /* this is only necessary in mode 3 ... */
1658 ad_write(mss, 22, 0x88);
1659 ad_write(mss, 23, 0x88);
1660 break;
1661 }
1662 return 0;
1663}
1664
1665static int
1666mssmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right)
1667{
1668 struct mss_info *mss = mix_getdevinfo(m);
1669
1670 mss_mixer_set(mss, dev, left, right);
1671
1672 return left | (right << 8);
1673}
1674
1675static int
1676mssmix_setrecsrc(snd_mixer *m, u_int32_t src)
1677{
1678 struct mss_info *mss = mix_getdevinfo(m);
1679
1680 src = mss_set_recsrc(mss, src);
1681 return src;
1682}
1683
1684static int
1685ymmix_init(snd_mixer *m)
1686{
1687 struct mss_info *mss = mix_getdevinfo(m);
1688
1689 mssmix_init(m);
1690 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC);
1691 /* Set master volume */
1692 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
1693 conf_wr(mss, OPL3SAx_VOLUMER, 7);
1694
1695 return 0;
1696}
1697
1698static int
1699ymmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right)
1700{
1701 struct mss_info *mss = mix_getdevinfo(m);
1702 int t;
1703
1704 switch (dev) {
1705 case SOUND_MIXER_VOLUME:
1706 if (left) t = 15 - (left * 15) / 100;
1707 else t = 0x80; /* mute */
1708 conf_wr(mss, OPL3SAx_VOLUMEL, t);
1709 if (right) t = 15 - (right * 15) / 100;
1710 else t = 0x80; /* mute */
1711 conf_wr(mss, OPL3SAx_VOLUMER, t);
1712 break;
1713
1714 case SOUND_MIXER_MIC:
1715 t = left;
1716 if (left) t = 31 - (left * 31) / 100;
1717 else t = 0x80; /* mute */
1718 conf_wr(mss, OPL3SAx_MIC, t);
1719 break;
1720
1721 case SOUND_MIXER_BASS:
1722 case SOUND_MIXER_TREBLE:
1723 /* Later maybe */
1724
1725 default:
1726 mss_mixer_set(mss, dev, left, right);
1727 }
1728
1729 return left | (right << 8);
1730}
1731
1732static int
1733ymmix_setrecsrc(snd_mixer *m, u_int32_t src)
1734{
1735 struct mss_info *mss = mix_getdevinfo(m);
1736 src = mss_set_recsrc(mss, src);
1737 return src;
1738}
1739
1740/* channel interface */
1741static void *
1742msschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
1743{
1744 struct mss_info *mss = devinfo;
1745 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1746
1747 ch->parent = mss;
1748 ch->channel = c;
1749 ch->buffer = b;
1750 ch->buffer->bufsize = DSP_BUFFSIZE;
1751 if (chn_allocbuf(ch->buffer, mss->parent_dmat) == -1) return NULL;
1752 return ch;
1753}
1754
1755static int
1756msschan_setdir(void *data, int dir)
1757{
1758 struct mss_chinfo *ch = data;
1759
1760 ch->buffer->chan = (dir == PCMDIR_PLAY)? ch->parent->pdma : ch->parent->rdma;
1761 ch->dir = dir;
1762 return 0;
1763}
1764
1765static int
1766msschan_setformat(void *data, u_int32_t format)
1767{
1768 struct mss_chinfo *ch = data;
1769
1770 mss_format(ch, format);
1771 return 0;
1772}
1773
1774static int
1775msschan_setspeed(void *data, u_int32_t speed)
1776{
1777 struct mss_chinfo *ch = data;
1778
1779 return mss_speed(ch, speed);
1780}
1781
1782static int
1783msschan_setblocksize(void *data, u_int32_t blocksize)
1784{
1785 return blocksize;
1786}
1787
1788static int
1789msschan_trigger(void *data, int go)
1790{
1791 struct mss_chinfo *ch = data;
1792
1793 buf_isadma(ch->buffer, go);
1794 mss_trigger(ch, go);
1795 return 0;
1796}
1797
1798static int
1799msschan_getptr(void *data)
1800{
1801 struct mss_chinfo *ch = data;
1802 return buf_isadmaptr(ch->buffer);
1803}
1804
1805static pcmchan_caps *
1806msschan_getcaps(void *data)
1807{
1808 struct mss_chinfo *ch = data;
1809
1810 switch(ch->parent->bd_id) {
1811 case MD_OPTI931:
1812 return &opti931_caps;
1813 break;
1814
1815 case MD_GUSPNP:
|
| 1816 case MD_GUSMAX:
|
1634 return &guspnp_caps;
1635 break;
1636
1637 default:
1638 return &mss_caps;
1639 break;
1640 }
1641}
1642
1643#endif /* NPCM > 0 */
| 1817 return &guspnp_caps;
1818 break;
1819
1820 default:
1821 return &mss_caps;
1822 break;
1823 }
1824}
1825
1826#endif /* NPCM > 0 */
|