| if_sisreg.h (72197) | if_sisreg.h (72200) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_sisreg.h 72197 2001-02-09 00:45:29Z wpaul $ | 32 * $FreeBSD: head/sys/pci/if_sisreg.h 72200 2001-02-09 06:11:45Z bmilekic $ |
| 33 */ 34 35/* 36 * Register definitions for the SiS 900 and SiS 7016 chipsets. The 37 * 7016 is actually an older chip and some of its registers differ 38 * from the 900, however the core operational registers are the same: 39 * the differences lie in the OnNow/Wake on LAN stuff which we don't 40 * use anyway. The 7016 needs an external MII compliant PHY while the --- 353 unchanged lines hidden (view full) --- 394 u_int8_t sis_type; 395 u_int8_t sis_link; 396 struct sis_list_data *sis_ldata; 397 struct sis_ring_data sis_cdata; 398 struct callout_handle sis_stat_ch; 399 struct mtx sis_mtx; 400}; 401 | 33 */ 34 35/* 36 * Register definitions for the SiS 900 and SiS 7016 chipsets. The 37 * 7016 is actually an older chip and some of its registers differ 38 * from the 900, however the core operational registers are the same: 39 * the differences lie in the OnNow/Wake on LAN stuff which we don't 40 * use anyway. The 7016 needs an external MII compliant PHY while the --- 353 unchanged lines hidden (view full) --- 394 u_int8_t sis_type; 395 u_int8_t sis_link; 396 struct sis_list_data *sis_ldata; 397 struct sis_ring_data sis_cdata; 398 struct callout_handle sis_stat_ch; 399 struct mtx sis_mtx; 400}; 401 |
| 402#define SIS_LOCK(_sc) mtx_enter(&(_sc)->sis_mtx, MTX_DEF) 403#define SIS_UNLOCK(_sc) mtx_exit(&(_sc)->sis_mtx, MTX_DEF) | 402#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 403#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) |
| 404 405/* 406 * register space access macros 407 */ 408#define CSR_WRITE_4(sc, reg, val) \ 409 bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val) 410 411#define CSR_READ_4(sc, reg) \ --- 49 unchanged lines hidden --- | 404 405/* 406 * register space access macros 407 */ 408#define CSR_WRITE_4(sc, reg, val) \ 409 bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val) 410 411#define CSR_READ_4(sc, reg) \ --- 49 unchanged lines hidden --- |