| if_sfreg.h (50477) | if_sfreg.h (50675) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/sf/if_sfreg.h 50477 1999-08-28 01:08:13Z peter $ | 32 * $FreeBSD: head/sys/dev/sf/if_sfreg.h 50675 1999-08-30 23:08:32Z wpaul $ |
| 33 */ 34 35/* 36 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 37 * register space. These registers can be accessed in the following way: 38 * - PCI config registers are always accessible through PCI config space 39 * - Full 512K space mapped into memory using PCI memory mapped access 40 * - 256-byte I/O space mapped through PCI I/O access --- 964 unchanged lines hidden (view full) --- 1005 struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT]; 1006 struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT]; 1007 struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT]; 1008 struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT]; 1009}; 1010 1011struct sf_softc { 1012 struct arpcom arpcom; /* interface info */ | 33 */ 34 35/* 36 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 37 * register space. These registers can be accessed in the following way: 38 * - PCI config registers are always accessible through PCI config space 39 * - Full 512K space mapped into memory using PCI memory mapped access 40 * - 256-byte I/O space mapped through PCI I/O access --- 964 unchanged lines hidden (view full) --- 1005 struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT]; 1006 struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT]; 1007 struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT]; 1008 struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT]; 1009}; 1010 1011struct sf_softc { 1012 struct arpcom arpcom; /* interface info */ |
| 1013 struct ifmedia ifmedia; /* media info */ | |
| 1014 bus_space_handle_t sf_bhandle; /* bus space handle */ 1015 bus_space_tag_t sf_btag; /* bus space tag */ 1016 void *sf_intrhand; /* interrupt handler cookie */ 1017 struct resource *sf_irq; /* irq resource descriptor */ 1018 struct resource *sf_res; /* mem/ioport resource */ 1019 struct sf_type *sf_info; /* Starfire adapter info */ | 1013 bus_space_handle_t sf_bhandle; /* bus space handle */ 1014 bus_space_tag_t sf_btag; /* bus space tag */ 1015 void *sf_intrhand; /* interrupt handler cookie */ 1016 struct resource *sf_irq; /* irq resource descriptor */ 1017 struct resource *sf_res; /* mem/ioport resource */ 1018 struct sf_type *sf_info; /* Starfire adapter info */ |
| 1020 struct sf_type *sf_pinfo; /* phy info */ | 1019 device_t sf_miibus; |
| 1021 u_int8_t sf_unit; /* interface number */ | 1020 u_int8_t sf_unit; /* interface number */ |
| 1022 u_int8_t sf_type; 1023 u_int8_t sf_phy_addr; /* PHY address */ 1024 u_int8_t sf_tx_pend; /* TX pending */ 1025 u_int8_t sf_want_auto; 1026 u_int8_t sf_autoneg; | |
| 1027 struct sf_list_data *sf_ldata; 1028 int sf_tx_cnt; 1029 struct callout_handle sf_stat_ch; 1030}; 1031 1032#define SF_TIMEOUT 1000 1033 | 1021 struct sf_list_data *sf_ldata; 1022 int sf_tx_cnt; 1023 struct callout_handle sf_stat_ch; 1024}; 1025 1026#define SF_TIMEOUT 1000 1027 |
| 1034#define SF_FLAG_FORCEDELAY 1 1035#define SF_FLAG_SCHEDDELAY 2 1036#define SF_FLAG_DELAYTIMEO 3 1037 1038/* 1039 * Texas Instruments PHY identifiers 1040 */ 1041#define TI_PHY_VENDORID 0x4000 1042#define TI_PHY_10BT 0x501F 1043#define TI_PHY_100VGPMI 0x502F 1044 1045/* 1046 * These ID values are for the NS DP83840A 10/100 PHY 1047 */ 1048#define NS_PHY_VENDORID 0x2000 1049#define NS_PHY_83840A 0x5C0F 1050 1051/* 1052 * Level 1 10/100 PHY 1053 */ 1054#define LEVEL1_PHY_VENDORID 0x7810 1055#define LEVEL1_PHY_LXT970 0x000F 1056 1057/* 1058 * Intel 82555 10/100 PHY 1059 */ 1060#define INTEL_PHY_VENDORID 0x0A28 1061#define INTEL_PHY_82555 0x015F 1062 1063/* 1064 * SEEQ 80220 10/100 PHY 1065 */ 1066#define SEEQ_PHY_VENDORID 0x0016 1067#define SEEQ_PHY_80220 0xF83F 1068 1069#define PHY_UNKNOWN 6 1070 1071#define SF_PHYADDR_MIN 0x00 1072#define SF_PHYADDR_MAX 0x1F 1073 1074#define PHY_BMCR 0x00 1075#define PHY_BMSR 0x01 1076#define PHY_VENID 0x02 1077#define PHY_DEVID 0x03 1078#define PHY_ANAR 0x04 1079#define PHY_LPAR 0x05 1080#define PHY_ANEXP 0x06 1081 1082#define PHY_ANAR_NEXTPAGE 0x8000 1083#define PHY_ANAR_RSVD0 0x4000 1084#define PHY_ANAR_TLRFLT 0x2000 1085#define PHY_ANAR_RSVD1 0x1000 1086#define PHY_ANAR_RSVD2 0x0800 1087#define PHY_ANAR_RSVD3 0x0400 1088#define PHY_ANAR_100BT4 0x0200 1089#define PHY_ANAR_100BTXFULL 0x0100 1090#define PHY_ANAR_100BTXHALF 0x0080 1091#define PHY_ANAR_10BTFULL 0x0040 1092#define PHY_ANAR_10BTHALF 0x0020 1093#define PHY_ANAR_PROTO4 0x0010 1094#define PHY_ANAR_PROTO3 0x0008 1095#define PHY_ANAR_PROTO2 0x0004 1096#define PHY_ANAR_PROTO1 0x0002 1097#define PHY_ANAR_PROTO0 0x0001 1098 1099/* 1100 * These are the register definitions for the PHY (physical layer 1101 * interface chip). 1102 */ 1103/* 1104 * PHY BMCR Basic Mode Control Register 1105 */ 1106#define PHY_BMCR_RESET 0x8000 1107#define PHY_BMCR_LOOPBK 0x4000 1108#define PHY_BMCR_SPEEDSEL 0x2000 1109#define PHY_BMCR_AUTONEGENBL 0x1000 1110#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 1111#define PHY_BMCR_ISOLATE 0x0400 1112#define PHY_BMCR_AUTONEGRSTR 0x0200 1113#define PHY_BMCR_DUPLEX 0x0100 1114#define PHY_BMCR_COLLTEST 0x0080 1115#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 1116#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 1117#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 1118#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 1119#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 1120#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 1121#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 1122/* 1123 * RESET: 1 == software reset, 0 == normal operation 1124 * Resets status and control registers to default values. 1125 * Relatches all hardware config values. 1126 * 1127 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 1128 * 1129 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 1130 * Link speed is selected byt his bit or if auto-negotiation if bit 1131 * 12 (AUTONEGENBL) is set (in which case the value of this register 1132 * is ignored). 1133 * 1134 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 1135 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 1136 * determine speed and mode. Should be cleared and then set if PHY configured 1137 * for no autoneg on startup. 1138 * 1139 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 1140 * 1141 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 1142 * 1143 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 1144 * 1145 * COLLTEST: 1 == collision test enabled, 0 == normal operation 1146 */ 1147 1148/* 1149 * PHY, BMSR Basic Mode Status Register 1150 */ 1151#define PHY_BMSR_100BT4 0x8000 1152#define PHY_BMSR_100BTXFULL 0x4000 1153#define PHY_BMSR_100BTXHALF 0x2000 1154#define PHY_BMSR_10BTFULL 0x1000 1155#define PHY_BMSR_10BTHALF 0x0800 1156#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 1157#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 1158#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 1159#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 1160#define PHY_BMSR_MFPRESUP 0x0040 1161#define PHY_BMSR_AUTONEGCOMP 0x0020 1162#define PHY_BMSR_REMFAULT 0x0010 1163#define PHY_BMSR_CANAUTONEG 0x0008 1164#define PHY_BMSR_LINKSTAT 0x0004 1165#define PHY_BMSR_JABBER 0x0002 1166#define PHY_BMSR_EXTENDED 0x0001 1167 | |
| 1168#ifdef __alpha__ 1169#undef vtophys 1170#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1171#endif | 1028#ifdef __alpha__ 1029#undef vtophys 1030#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1031#endif |