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if_sfreg.h (175520) if_sfreg.h (175526)
1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/sf/if_sfreg.h 162317 2006-09-15 11:01:23Z ru $
32 * $FreeBSD: head/sys/dev/sf/if_sfreg.h 175526 2008-01-21 06:38:23Z yongari $
33 */
34
35/*
36 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K
37 * register space. These registers can be accessed in the following way:
38 * - PCI config registers are always accessible through PCI config space
39 * - Full 512K space mapped into memory using PCI memory mapped access
40 * - 256-byte I/O space mapped through PCI I/O access

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191#define SF_CURTIME 0x0078
192#define SF_ISR 0x0080
193#define SF_ISR_SHADOW 0x0084
194#define SF_IMR 0x0088
195#define SF_GPIO 0x008C
196#define SF_TXDQ_CTL 0x0090
197#define SF_TXDQ_ADDR_HIPRIO 0x0094
198#define SF_TXDQ_ADDR_LOPRIO 0x0098
33 */
34
35/*
36 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K
37 * register space. These registers can be accessed in the following way:
38 * - PCI config registers are always accessible through PCI config space
39 * - Full 512K space mapped into memory using PCI memory mapped access
40 * - 256-byte I/O space mapped through PCI I/O access

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191#define SF_CURTIME 0x0078
192#define SF_ISR 0x0080
193#define SF_ISR_SHADOW 0x0084
194#define SF_IMR 0x0088
195#define SF_GPIO 0x008C
196#define SF_TXDQ_CTL 0x0090
197#define SF_TXDQ_ADDR_HIPRIO 0x0094
198#define SF_TXDQ_ADDR_LOPRIO 0x0098
199#define SF_TXDQ_ADDR_HIADDR 0x009C
199#define SF_TXDQ_ADDR_HI 0x009C
200#define SF_TXDQ_PRODIDX 0x00A0
201#define SF_TXDQ_CONSIDX 0x00A4
202#define SF_TXDMA_STS1 0x00A8
203#define SF_TXDMA_STS2 0x00AC
204#define SF_TX_FRAMCTL 0x00B0
200#define SF_TXDQ_PRODIDX 0x00A0
201#define SF_TXDQ_CONSIDX 0x00A4
202#define SF_TXDMA_STS1 0x00A8
203#define SF_TXDMA_STS2 0x00AC
204#define SF_TX_FRAMCTL 0x00B0
205#define SF_TXCQ_ADDR_HI 0x00B4
205#define SF_CQ_ADDR_HI 0x00B4
206#define SF_TXCQ_CTL 0x00B8
207#define SF_RXCQ_CTL_1 0x00BC
208#define SF_RXCQ_CTL_2 0x00C0
209#define SF_CQ_CONSIDX 0x00C4
210#define SF_CQ_PRODIDX 0x00C8
211#define SF_CQ_RXQ2 0x00CC
212#define SF_RXDMA_CTL 0x00D0
213#define SF_RXDQ_CTL_1 0x00D4
214#define SF_RXDQ_CTL_2 0x00D8
206#define SF_TXCQ_CTL 0x00B8
207#define SF_RXCQ_CTL_1 0x00BC
208#define SF_RXCQ_CTL_2 0x00C0
209#define SF_CQ_CONSIDX 0x00C4
210#define SF_CQ_PRODIDX 0x00C8
211#define SF_CQ_RXQ2 0x00CC
212#define SF_RXDMA_CTL 0x00D0
213#define SF_RXDQ_CTL_1 0x00D4
214#define SF_RXDQ_CTL_2 0x00D8
215#define SF_RXDQ_ADDR_HIADDR 0x00DC
215#define SF_RXDQ_ADDR_HI 0x00DC
216#define SF_RXDQ_ADDR_Q1 0x00E0
217#define SF_RXDQ_ADDR_Q2 0x00E4
218#define SF_RXDQ_PTR_Q1 0x00E8
219#define SF_RXDQ_PTR_Q2 0x00EC
220#define SF_RXDMA_STS 0x00F0
221#define SF_RXFILT 0x00F4
222#define SF_RX_FRAMETEST_OUT 0x00F8
223

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244#define SF_TIMER_ONESHOT 0x01000000
245#define SF_TIMER_GENTIMER_RES 0x02000000
246#define SF_TIMER_TIMEST_RES 0x04000000
247#define SF_TIMER_RXQ2DONE_DLY 0x10000000
248#define SF_TIMER_EARLYRX2_DLY 0x20000000
249#define SF_TIMER_RXQ1DONE_DLY 0x40000000
250#define SF_TIMER_EARLYRX1_DLY 0x80000000
251
216#define SF_RXDQ_ADDR_Q1 0x00E0
217#define SF_RXDQ_ADDR_Q2 0x00E4
218#define SF_RXDQ_PTR_Q1 0x00E8
219#define SF_RXDQ_PTR_Q2 0x00EC
220#define SF_RXDMA_STS 0x00F0
221#define SF_RXFILT 0x00F4
222#define SF_RX_FRAMETEST_OUT 0x00F8
223

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244#define SF_TIMER_ONESHOT 0x01000000
245#define SF_TIMER_GENTIMER_RES 0x02000000
246#define SF_TIMER_TIMEST_RES 0x04000000
247#define SF_TIMER_RXQ2DONE_DLY 0x10000000
248#define SF_TIMER_EARLYRX2_DLY 0x20000000
249#define SF_TIMER_RXQ1DONE_DLY 0x40000000
250#define SF_TIMER_EARLYRX1_DLY 0x80000000
251
252/* Timer resolution is 0.8us * 128. */
253#define SF_IM_MIN 0
254#define SF_IM_MAX 0x1F /* 3.276ms */
255#define SF_IM_DEFAULT 1 /* 102.4us */
256
252/* Interrupt status register */
253#define SF_ISR_PCIINT_ASSERTED 0x00000001
254#define SF_ISR_GFP_TX 0x00000002
255#define SF_ISR_GFP_RX 0x00000004
256#define SF_ISR_TX_BADID_HIPRIO 0x00000008
257#define SF_ISR_TX_BADID_LOPRIO 0x00000010
258#define SF_ISR_NO_TX_CSUM 0x00000020
259#define SF_ISR_RXDQ2_NOBUFS 0x00000040

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342#define SF_IMR_GENTIMER 0x01000000
343#define SF_IMR_ABNORMALINTR 0x02000000
344#define SF_IMR_RSVD0 0x04000000
345#define SF_IMR_STATSOFLOW 0x08000000
346#define SF_IMR_GPIO 0xF0000000
347
348#define SF_INTRS \
349 (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE| \
257/* Interrupt status register */
258#define SF_ISR_PCIINT_ASSERTED 0x00000001
259#define SF_ISR_GFP_TX 0x00000002
260#define SF_ISR_GFP_RX 0x00000004
261#define SF_ISR_TX_BADID_HIPRIO 0x00000008
262#define SF_ISR_TX_BADID_LOPRIO 0x00000010
263#define SF_ISR_NO_TX_CSUM 0x00000020
264#define SF_ISR_RXDQ2_NOBUFS 0x00000040

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347#define SF_IMR_GENTIMER 0x01000000
348#define SF_IMR_ABNORMALINTR 0x02000000
349#define SF_IMR_RSVD0 0x04000000
350#define SF_IMR_STATSOFLOW 0x08000000
351#define SF_IMR_GPIO 0xF0000000
352
353#define SF_INTRS \
354 (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE| \
350 SF_IMR_TX_TXDONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE| \
355 SF_IMR_TX_DMADONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE| \
351 SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS| \
352 SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW| \
356 SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS| \
357 SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW| \
353 SF_IMR_TX_LOFIFO)
358 SF_IMR_TX_LOFIFO|SF_IMR_DMAERR|SF_IMR_RXGFP_NORESP| \
359 SF_IMR_NO_TX_CSUM)
354
355/* TX descriptor queue control registers */
356#define SF_TXDQCTL_DESCTYPE 0x00000007
357#define SF_TXDQCTL_NODMACMP 0x00000008
358#define SF_TXDQCTL_MINSPACE 0x00000070
359#define SF_TXDQCTL_64BITADDR 0x00000080
360#define SF_TXDQCTL_BURSTLEN 0x00003F00
361#define SF_TXDQCTL_SKIPLEN 0x001F0000
362#define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000
363
360
361/* TX descriptor queue control registers */
362#define SF_TXDQCTL_DESCTYPE 0x00000007
363#define SF_TXDQCTL_NODMACMP 0x00000008
364#define SF_TXDQCTL_MINSPACE 0x00000070
365#define SF_TXDQCTL_64BITADDR 0x00000080
366#define SF_TXDQCTL_BURSTLEN 0x00003F00
367#define SF_TXDQCTL_SKIPLEN 0x001F0000
368#define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000
369
370#define SF_TXDMA_HIPRIO_THRESH 2
371#define SF_TXDDMA_BURST (128 / 32)
372
364#define SF_TXBUFDESC_TYPE0 0x00000000
365#define SF_TXBUFDESC_TYPE1 0x00000001
366#define SF_TXBUFDESC_TYPE2 0x00000002
367#define SF_TXBUFDESC_TYPE3 0x00000003
368#define SF_TXBUFDESC_TYPE4 0x00000004
369
370#define SF_TXMINSPACE_UNLIMIT 0x00000000
371#define SF_TXMINSPACE_32BYTES 0x00000010

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429#define SF_CQ_RXQ2_RXTHRMODE 0x00008000
430#define SF_CQ_RXQ2_PRODIDX 0x03FF0000
431
432#define SF_CQ_RXTHRMODE_INT_ON 0x00008000
433#define SF_CQ_RXTHRMODE_INT_OFF 0x00000000
434#define SF_CQ_TXTHRMODE_INT_ON 0x80000000
435#define SF_CQ_TXTHRMODE_INT_OFF 0x00000000
436
373#define SF_TXBUFDESC_TYPE0 0x00000000
374#define SF_TXBUFDESC_TYPE1 0x00000001
375#define SF_TXBUFDESC_TYPE2 0x00000002
376#define SF_TXBUFDESC_TYPE3 0x00000003
377#define SF_TXBUFDESC_TYPE4 0x00000004
378
379#define SF_TXMINSPACE_UNLIMIT 0x00000000
380#define SF_TXMINSPACE_32BYTES 0x00000010

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438#define SF_CQ_RXQ2_RXTHRMODE 0x00008000
439#define SF_CQ_RXQ2_PRODIDX 0x03FF0000
440
441#define SF_CQ_RXTHRMODE_INT_ON 0x00008000
442#define SF_CQ_RXTHRMODE_INT_OFF 0x00000000
443#define SF_CQ_TXTHRMODE_INT_ON 0x80000000
444#define SF_CQ_TXTHRMODE_INT_OFF 0x00000000
445
437#define SF_IDX_LO(x) ((x) & 0x000007FF)
438#define SF_IDX_HI(x) (((x) >> 16) & 0x000007FF)
439
440/* RX DMA control register */
441#define SF_RXDMA_BURSTSIZE 0x0000007F
442#define SF_RXDMA_FPTESTMODE 0x00000080
443#define SF_RXDMA_HIPRIOTHRESH 0x00000F00
444#define SF_RXDMA_RXEARLYTHRESH 0x0001F000
445#define SF_RXDMA_DMACRC 0x00040000
446#define SF_RXDMA_USEBKUPQUEUE 0x00080000
447#define SF_RXDMA_QUEUEMODE 0x00700000
448#define SF_RXDMA_RXCQ2_ON 0x00800000
449#define SF_RXDMA_CSUMMODE 0x03000000
450#define SF_RXDMA_DMAPAUSEPKTS 0x04000000
451#define SF_RXDMA_DMACTLPKTS 0x08000000
452#define SF_RXDMA_DMACRXERRPKTS 0x10000000
453#define SF_RXDMA_DMABADPKTS 0x20000000
454#define SF_RXDMA_DMARUNTS 0x40000000
455#define SF_RXDMA_REPORTBADPKTS 0x80000000
446/* RX DMA control register */
447#define SF_RXDMA_BURSTSIZE 0x0000007F
448#define SF_RXDMA_FPTESTMODE 0x00000080
449#define SF_RXDMA_HIPRIOTHRESH 0x00000F00
450#define SF_RXDMA_RXEARLYTHRESH 0x0001F000
451#define SF_RXDMA_DMACRC 0x00040000
452#define SF_RXDMA_USEBKUPQUEUE 0x00080000
453#define SF_RXDMA_QUEUEMODE 0x00700000
454#define SF_RXDMA_RXCQ2_ON 0x00800000
455#define SF_RXDMA_CSUMMODE 0x03000000
456#define SF_RXDMA_DMAPAUSEPKTS 0x04000000
457#define SF_RXDMA_DMACTLPKTS 0x08000000
458#define SF_RXDMA_DMACRXERRPKTS 0x10000000
459#define SF_RXDMA_DMABADPKTS 0x20000000
460#define SF_RXDMA_DMARUNTS 0x40000000
461#define SF_RXDMA_REPORTBADPKTS 0x80000000
462#define SF_RXDMA_HIGHPRIO_THRESH 6
463#define SF_RXDMA_BURST (64 / 32)
456
457#define SF_RXDQMODE_Q1ONLY 0x00100000
458#define SF_RXDQMODE_Q2_ON_FP 0x00200000
459#define SF_RXDQMODE_Q2_ON_SHORT 0x00300000
460#define SF_RXDQMODE_Q2_ON_PRIO 0x00400000
461#define SF_RXDQMODE_SPLITHDR 0x00500000
462
463#define SF_RXCSUMMODE_IGNORE 0x00000000

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562#define SF_MIIADDR_MAX 0x3FFF
563#define SF_MII_BLOCKS 32
564
565#define SF_MII_DATAVALID 0x80000000
566#define SF_MII_BUSY 0x40000000
567#define SF_MII_DATAPORT 0x0000FFFF
568
569#define SF_PHY_REG(phy, reg) \
464
465#define SF_RXDQMODE_Q1ONLY 0x00100000
466#define SF_RXDQMODE_Q2_ON_FP 0x00200000
467#define SF_RXDQMODE_Q2_ON_SHORT 0x00300000
468#define SF_RXDQMODE_Q2_ON_PRIO 0x00400000
469#define SF_RXDQMODE_SPLITHDR 0x00500000
470
471#define SF_RXCSUMMODE_IGNORE 0x00000000

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570#define SF_MIIADDR_MAX 0x3FFF
571#define SF_MII_BLOCKS 32
572
573#define SF_MII_DATAVALID 0x80000000
574#define SF_MII_BUSY 0x40000000
575#define SF_MII_DATAPORT 0x0000FFFF
576
577#define SF_PHY_REG(phy, reg) \
570 (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) + \
571 (reg * sizeof(u_int32_t)))
578 (SF_MIIADDR_BASE + ((phy) * SF_MII_BLOCKS * sizeof(uint32_t)) + \
579 ((reg) * sizeof(uint32_t)))
572
573/*
574 * Ethernet extra registers 0x4000 to 0x4FFF
575 */
576#define SF_TESTMODE 0x4000
577#define SF_RX_FRAMEPROC_CTL 0x4004
578#define SF_TX_FRAMEPROC_CTL 0x4008
579

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608#define SF_MACCFG1_PASSALLRX 0x00000100
609#define SF_MACCFG1_PREAM_DETCNT 0x00000200
610#define SF_MACCFG1_RX_FLOWENB 0x00000400
611#define SF_MACCFG1_TX_FLOWENB 0x00000800
612#define SF_MACCFG1_TESTMODE 0x00003000
613#define SF_MACCFG1_MIILOOPBK 0x00004000
614#define SF_MACCFG1_SOFTRESET 0x00008000
615
580
581/*
582 * Ethernet extra registers 0x4000 to 0x4FFF
583 */
584#define SF_TESTMODE 0x4000
585#define SF_RX_FRAMEPROC_CTL 0x4004
586#define SF_TX_FRAMEPROC_CTL 0x4008
587

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616#define SF_MACCFG1_PASSALLRX 0x00000100
617#define SF_MACCFG1_PREAM_DETCNT 0x00000200
618#define SF_MACCFG1_RX_FLOWENB 0x00000400
619#define SF_MACCFG1_TX_FLOWENB 0x00000800
620#define SF_MACCFG1_TESTMODE 0x00003000
621#define SF_MACCFG1_MIILOOPBK 0x00004000
622#define SF_MACCFG1_SOFTRESET 0x00008000
623
624#define SF_MACCFG2_AUTOVLANPAD 0x00000020
625
616/*
617 * There are the recommended IPG nibble counter settings
618 * specified in the Adaptec manual for full duplex and
619 * half duplex operation.
620 */
621#define SF_IPGT_FDX 0x15
622#define SF_IPGT_HDX 0x11
623

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638#define SF_RXFILT_HASH_VLANOFF 0x0008
639
640/*
641 * Statistics registers 0x7000 to 0x7FFF
642 */
643#define SF_STATS_BASE 0x7000
644#define SF_STATS_END 0x7FFF
645
626/*
627 * There are the recommended IPG nibble counter settings
628 * specified in the Adaptec manual for full duplex and
629 * half duplex operation.
630 */
631#define SF_IPGT_FDX 0x15
632#define SF_IPGT_HDX 0x11
633

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648#define SF_RXFILT_HASH_VLANOFF 0x0008
649
650/*
651 * Statistics registers 0x7000 to 0x7FFF
652 */
653#define SF_STATS_BASE 0x7000
654#define SF_STATS_END 0x7FFF
655
656#define SF_STATS_TX_FRAMES 0x0000
657#define SF_STATS_TX_SINGLE_COL 0x0004
658#define SF_STATS_TX_MULTI_COL 0x0008
659#define SF_STATS_TX_CRC_ERRS 0x000C
660#define SF_STATS_TX_BYTES 0x0010
661#define SF_STATS_TX_DEFERRED 0x0014
662#define SF_STATS_TX_LATE_COL 0x0018
663#define SF_STATS_TX_PAUSE 0x001C
664#define SF_STATS_TX_CTL_FRAME 0x0020
665#define SF_STATS_TX_EXCESS_COL 0x0024
666#define SF_STATS_TX_EXCESS_DEF 0x0028
667#define SF_STATS_TX_MULTI 0x002C
668#define SF_STATS_TX_BCAST 0x0030
669#define SF_STATS_TX_FRAME_LOST 0x0034
670#define SF_STATS_RX_FRAMES 0x0038
671#define SF_STATS_RX_CRC_ERRS 0x003C
672#define SF_STATS_RX_ALIGN_ERRS 0x0040
673#define SF_STATS_RX_BYTES 0x0044
674#define SF_STATS_RX_PAUSE 0x0048
675#define SF_STATS_RX_CTL_FRAME 0x004C
676#define SF_STATS_RX_UNSUP_FRAME 0x0050
677#define SF_STATS_RX_GIANTS 0x0054
678#define SF_STATS_RX_RUNTS 0x0058
679#define SF_STATS_RX_JABBER 0x005C
680#define SF_STATS_RX_FRAGMENTS 0x0060
681#define SF_STATS_RX_64 0x0064
682#define SF_STATS_RX_65_127 0x0068
683#define SF_STATS_RX_128_255 0x006C
684#define SF_STATS_RX_256_511 0x0070
685#define SF_STATS_RX_512_1023 0x0074
686#define SF_STATS_RX_1024_1518 0x0078
687#define SF_STATS_RX_FRAME_LOST 0x007C
688#define SF_STATS_TX_UNDERRUN 0x0080
689
646/*
647 * TX frame processor instruction space 0x8000 to 0x9FFF
648 */
690/*
691 * TX frame processor instruction space 0x8000 to 0x9FFF
692 */
693#define SF_TXGFP_MEM_BASE 0x8000
694#define SF_TXGFP_MEM_END 0x8FFF
649
695
696/* Number of bytes of an GFP instruction. */
697#define SF_GFP_INST_BYTES 6
650/*
651 * RX frame processor instruction space 0xA000 to 0xBFFF
652 */
698/*
699 * RX frame processor instruction space 0xA000 to 0xBFFF
700 */
701#define SF_RXGFP_MEM_BASE 0xA000
702#define SF_RXGFP_MEM_END 0xBFFF
653
654/*
655 * Ethernet FIFO access space 0xC000 to 0xDFFF
656 */
657
658/*
659 * Reserved 0xE000 to 0xFFFF
660 */
661
662/*
663 * Descriptor data structures.
664 */
665
703
704/*
705 * Ethernet FIFO access space 0xC000 to 0xDFFF
706 */
707
708/*
709 * Reserved 0xE000 to 0xFFFF
710 */
711
712/*
713 * Descriptor data structures.
714 */
715
666
667/* Receive descriptor formats. */
668#define SF_RX_MINSPACING 8
669#define SF_RX_DLIST_CNT 256
670#define SF_RX_CLIST_CNT 1024
671#define SF_RX_HOSTADDR(x) (((x) >> 2) & 0x3FFFFFFF)
672
673/*
716/*
674 * RX buffer descriptor type 0, 32-bit addressing. Note that we
675 * program the RX buffer queue control register(s) to allow a
676 * descriptor spacing of 16 bytes, which leaves room after each
677 * descriptor to store a pointer to the mbuf for each buffer.
717 * RX buffer descriptor type 0, 32-bit addressing.
678 */
679struct sf_rx_bufdesc_type0 {
718 */
719struct sf_rx_bufdesc_type0 {
680 u_int32_t sf_valid:1,
681 sf_end:1,
682 sf_addrlo:30;
683 u_int32_t sf_pad0;
684#ifdef __i386__
685 u_int32_t sf_pad1;
686#endif
687 struct mbuf *sf_mbuf;
720 uint32_t sf_addrlo;
721#define SF_RX_DESC_VALID 0x00000001
722#define SF_RX_DESC_END 0x00000002
688};
689
690/*
723};
724
725/*
691 * RX buffer descriptor type 0, 64-bit addressing.
726 * RX buffer descriptor type 1, 64-bit addressing.
692 */
693struct sf_rx_bufdesc_type1 {
727 */
728struct sf_rx_bufdesc_type1 {
694 u_int32_t sf_valid:1,
695 sf_end:1,
696 sf_addrlo:30;
697 u_int32_t sf_addrhi;
698#ifdef __i386__
699 u_int32_t sf_pad;
700#endif
701 struct mbuf *sf_mbuf;
729 uint64_t sf_addr;
702};
703
704/*
705 * RX completion descriptor, type 0 (short).
706 */
707struct sf_rx_cmpdesc_type0 {
730};
731
732/*
733 * RX completion descriptor, type 0 (short).
734 */
735struct sf_rx_cmpdesc_type0 {
708 u_int32_t sf_len:16,
709 sf_endidx:11,
710 sf_status1:3,
711 sf_id:2;
736 uint32_t sf_rx_status1;
737#define SF_RX_CMPDESC_LEN 0x0000ffff
738#define SF_RX_CMPDESC_EIDX 0x07ff0000
739#define SF_RX_CMPDESC_STAT1 0x38000000
740#define SF_RX_CMPDESC_ID 0x40000000
712};
713
714/*
715 * RX completion descriptor, type 1 (basic). Includes vlan ID
716 * if this is a vlan-addressed packet, plus extended status.
717 */
718struct sf_rx_cmpdesc_type1 {
741};
742
743/*
744 * RX completion descriptor, type 1 (basic). Includes vlan ID
745 * if this is a vlan-addressed packet, plus extended status.
746 */
747struct sf_rx_cmpdesc_type1 {
719 u_int32_t sf_len:16,
720 sf_endidx:11,
721 sf_status1:3,
722 sf_id:2;
723 u_int16_t sf_status2;
724 u_int16_t sf_vlanid;
748 uint32_t sf_rx_status1;
749 uint32_t sf_rx_status2;
750#define SF_RX_CMPDESC_VLAN 0x0000ffff
751#define SF_RX_CMPDESC_STAT2 0xffff0000
725};
726
727/*
728 * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP
729 * checksum instead of vlan tag, plus extended status.
730 */
731struct sf_rx_cmpdesc_type2 {
752};
753
754/*
755 * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP
756 * checksum instead of vlan tag, plus extended status.
757 */
758struct sf_rx_cmpdesc_type2 {
732 u_int32_t sf_len:16,
733 sf_endidx:11,
734 sf_status1:3,
735 sf_id:2;
736 u_int16_t sf_status2;
737 u_int16_t sf_cksum;
759 uint32_t sf_rx_status1;
760 uint32_t sf_rx_status2;
761#define SF_RX_CMPDESC_CSUM2 0x0000ffff
738};
739
740/*
741 * RX completion descriptor type 3 (full). Includes timestamp, partial
742 * TCP/IP checksum, vlan tag plus priority, two extended status fields.
743 */
744struct sf_rx_cmpdesc_type3 {
762};
763
764/*
765 * RX completion descriptor type 3 (full). Includes timestamp, partial
766 * TCP/IP checksum, vlan tag plus priority, two extended status fields.
767 */
768struct sf_rx_cmpdesc_type3 {
745 u_int32_t sf_len:16,
746 sf_endidx:11,
747 sf_status1:3,
748 sf_id:2;
749 u_int32_t sf_startidx:10,
750 sf_status3:6,
751 sf_status2:16;
752 u_int16_t sf_cksum;
753 u_int16_t sf_vlanid_prio;
754 u_int32_t sf_timestamp;
769 uint32_t sf_rx_status1;
770 uint32_t sf_rx_status2;
771 uint32_t sf_rx_status3;
772#define SF_RX_CMPDESC_CSUM3 0xffff0000
773#define SF_RX_CMPDESC_VLANPRI 0x0000ffff
774 uint32_t sf_rx_timestamp;
755};
756
775};
776
757#define SF_RXSTAT1_QUEUE 0x1
758#define SF_RXSTAT1_FIFOFULL 0x2
759#define SF_RXSTAT1_OK 0x4
777#define SF_RXSTAT1_QUEUE 0x08000000
778#define SF_RXSTAT1_FIFOFULL 0x10000000
779#define SF_RXSTAT1_OK 0x20000000
760
780
761 /* 0=unknown,5=unsupported */
762#define SF_RXSTAT2_FRAMETYPE 0x0007 /* 1=IPv4,2=IPv2,3=IPX,4=ICMP */
763#define SF_RXSTAT2_UDP 0x0008
764#define SF_RXSTAT2_TCP 0x0010
765#define SF_RXSTAT2_FRAG 0x0020
766#define SF_RXSTAT2_PCSUM_OK 0x0040 /* partial checksum ok */
767#define SF_RXSTAT2_CSUM_BAD 0x0080 /* TCP/IP checksum bad */
768#define SF_RXSTAT2_CSUM_OK 0x0100 /* TCP/IP checksum ok */
769#define SF_RXSTAT2_VLAN 0x0200
770#define SF_RXSTAT2_BADRXCODE 0x0400
771#define SF_RXSTAT2_DRIBBLE 0x0800
772#define SF_RXSTAT2_ISL_CRCERR 0x1000
773#define SF_RXSTAT2_CRCERR 0x2000
774#define SF_RXSTAT2_HASH 0x4000
775#define SF_RXSTAT2_PERFECT 0x8000
781#define SF_RXSTAT2_FRAMETYPE_MASK 0x00070000
782#define SF_RXSTAT2_FRAMETYPE_UNKN 0x00000000
783#define SF_RXSTAT2_FRAMETYPE_IPV4 0x00010000
784#define SF_RXSTAT2_FRAMETYPE_IPV6 0x00020000
785#define SF_RXSTAT2_FRAMETYPE_IPX 0x00030000
786#define SF_RXSTAT2_FRAMETYPE_ICMP 0x00040000
787#define SF_RXSTAT2_FRAMETYPE_UNSPRT 0x00050000
788#define SF_RXSTAT2_UDP 0x00080000
789#define SF_RXSTAT2_TCP 0x00100000
790#define SF_RXSTAT2_FRAG 0x00200000
791#define SF_RXSTAT2_PCSUM_OK 0x00400000 /* partial checksum ok */
792#define SF_RXSTAT2_CSUM_BAD 0x00800000 /* TCP/IP checksum bad */
793#define SF_RXSTAT2_CSUM_OK 0x01000000 /* TCP/IP checksum ok */
794#define SF_RXSTAT2_VLAN 0x02000000
795#define SF_RXSTAT2_BADRXCODE 0x04000000
796#define SF_RXSTAT2_DRIBBLE 0x08000000
797#define SF_RXSTAT2_ISL_CRCERR 0x10000000
798#define SF_RXSTAT2_CRCERR 0x20000000
799#define SF_RXSTAT2_HASH 0x40000000
800#define SF_RXSTAT2_PERFECT 0x80000000
801#define SF_RXSTAT2_MASK 0xFFFF0000
776
802
777#define SF_RXSTAT3_TRAILER 0x01
778#define SF_RXSTAT3_HEADER 0x02
779#define SF_RXSTAT3_CONTROL 0x04
780#define SF_RXSTAT3_PAUSE 0x08
781#define SF_RXSTAT3_ISL 0x10
803#define SF_RXSTAT3_ISL 0x00008000
804#define SF_RXSTAT3_PAUSE 0x00004000
805#define SF_RXSTAT3_CONTROL 0x00002000
806#define SF_RXSTAT3_HEADER 0x00001000
807#define SF_RXSTAT3_TRAILER 0x00000800
808#define SF_RXSTAT3_START_IDX_MASK 0x000007FF
782
809
783/*
784 * Transmit descriptor formats.
785 * Each transmit descriptor type allows for a skip field at the
786 * start of each structure. The size of the skip field can vary,
787 * however we always set it for 8 bytes, which is enough to hold
788 * a pointer (32 bits on x86, 64-bits on alpha) that we can use
789 * to hold the address of the head of the mbuf chain for the
790 * frame or fragment associated with the descriptor. This saves
791 * us from having to create a separate pointer array to hold
792 * the mbuf addresses.
793 */
794#define SF_TX_BUFDESC_ID 0xB
795#define SF_MAXFRAGS 14
796#define SF_TX_MINSPACING 128
797#define SF_TX_DLIST_CNT 128
798#define SF_TX_DLIST_SIZE 16384
799#define SF_TX_SKIPLEN 1
800#define SF_TX_CLIST_CNT 1024
801
802struct sf_frag {
810struct sf_frag {
803 u_int32_t sf_addr;
804 u_int16_t sf_fraglen;
805 u_int16_t sf_pktlen;
811 uint32_t sf_addr;
812 uint16_t sf_fraglen;
813 uint16_t sf_pktlen;
806};
807
808struct sf_frag_msdos {
814};
815
816struct sf_frag_msdos {
809 u_int16_t sf_pktlen;
810 u_int16_t sf_fraglen;
811 u_int32_t sf_addr;
817 uint16_t sf_pktlen;
818 uint16_t sf_fraglen;
819 uint32_t sf_addr;
812};
813
814/*
815 * TX frame descriptor type 0, 32-bit addressing. One descriptor can
820};
821
822/*
823 * TX frame descriptor type 0, 32-bit addressing. One descriptor can
816 * be used to map multiple packet fragments. We use this format since
817 * BSD networking fragments packet data across mbuf chains. Note that
818 * the number of fragments can be variable depending on how the descriptor
819 * spacing is specified in the TX descriptor queue control register.
824 * be used to map multiple packet fragments. Note that the number of
825 * fragments can be variable depending on how the descriptor spacing
826 * is specified in the TX descriptor queue control register.
820 * We always use a spacing of 128 bytes, and a skipfield length of 8
821 * bytes: this means 16 bytes for the descriptor, including the skipfield,
822 * with 121 bytes left for fragment maps. Each fragment requires 8 bytes,
823 * which allows for 14 fragments per descriptor. The total size of the
824 * transmit buffer queue is limited to 16384 bytes, so with a spacing of
825 * 128 bytes per descriptor, we have room for 128 descriptors in the queue.
826 */
827struct sf_tx_bufdesc_type0 {
827 * We always use a spacing of 128 bytes, and a skipfield length of 8
828 * bytes: this means 16 bytes for the descriptor, including the skipfield,
829 * with 121 bytes left for fragment maps. Each fragment requires 8 bytes,
830 * which allows for 14 fragments per descriptor. The total size of the
831 * transmit buffer queue is limited to 16384 bytes, so with a spacing of
832 * 128 bytes per descriptor, we have room for 128 descriptors in the queue.
833 */
834struct sf_tx_bufdesc_type0 {
828#ifdef __i386__
829 u_int32_t sf_pad;
830#endif
831 struct mbuf *sf_mbuf;
832 u_int32_t sf_rsvd0:24,
833 sf_crcen:1,
834 sf_caltcp:1,
835 sf_end:1,
836 sf_intr:1,
837 sf_id:4;
838 u_int8_t sf_fragcnt;
839 u_int8_t sf_rsvd2;
840 u_int16_t sf_rsvd1;
841 struct sf_frag sf_frags[14];
835 uint32_t sf_tx_ctrl;
836#define SF_TX_DESC_CRCEN 0x01000000
837#define SF_TX_DESC_CALTCP 0x02000000
838#define SF_TX_DESC_END 0x04000000
839#define SF_TX_DESC_INTR 0x08000000
840#define SF_TX_DESC_ID 0xb0000000
841 uint32_t sf_tx_frag;
842 /*
843 * Depending on descriptor spacing/skip field length it
844 * can have fixed number of struct sf_frag.
845 * struct sf_frag sf_frags[14];
846 */
842};
843
844/*
845 * TX buffer descriptor type 1, 32-bit addressing. Each descriptor
846 * maps a single fragment.
847 */
848struct sf_tx_bufdesc_type1 {
847};
848
849/*
850 * TX buffer descriptor type 1, 32-bit addressing. Each descriptor
851 * maps a single fragment.
852 */
853struct sf_tx_bufdesc_type1 {
849#ifdef __i386__
850 u_int32_t sf_pad;
851#endif
852 struct mbuf *sf_mbuf;
853 u_int32_t sf_fraglen:16,
854 sf_fragcnt:8,
855 sf_crcen:1,
856 sf_caltcp:1,
857 sf_end:1,
858 sf_intr:1,
859 sf_id:4;
860 u_int32_t sf_addr;
854 uint32_t sf_tx_ctrl;
855#define SF_TX_DESC_FRAGLEN 0x0000ffff
856#define SF_TX_DESC_FRAGCNT 0x00ff0000
857 uint32_t sf_addrlo;
861};
862
863/*
864 * TX buffer descriptor type 2, 64-bit addressing. Each descriptor
865 * maps a single fragment.
866 */
867struct sf_tx_bufdesc_type2 {
858};
859
860/*
861 * TX buffer descriptor type 2, 64-bit addressing. Each descriptor
862 * maps a single fragment.
863 */
864struct sf_tx_bufdesc_type2 {
868#ifdef __i386__
869 u_int32_t sf_pad;
870#endif
871 struct mbuf *sf_mbuf;
872 u_int32_t sf_fraglen:16,
873 sf_fragcnt:8,
874 sf_crcen:1,
875 sf_caltcp:1,
876 sf_end:1,
877 sf_intr:1,
878 sf_id:4;
879 u_int32_t sf_addrlo;
880 u_int32_t sf_addrhi;
865 uint32_t sf_tx_ctrl;
866 uint32_t sf_tx_reserved;
867 uint64_t sf_addr;
881};
882
883/* TX buffer descriptor type 3 is not defined. */
884
885/*
886 * TX frame descriptor type 4, 32-bit addressing. This is a special
887 * case of the type 0 descriptor, identical except that the fragment
888 * address and length fields are ordered differently. This is done
889 * to optimize copies in MS-DOS and OS/2 drivers.
890 */
891struct sf_tx_bufdesc_type4 {
868};
869
870/* TX buffer descriptor type 3 is not defined. */
871
872/*
873 * TX frame descriptor type 4, 32-bit addressing. This is a special
874 * case of the type 0 descriptor, identical except that the fragment
875 * address and length fields are ordered differently. This is done
876 * to optimize copies in MS-DOS and OS/2 drivers.
877 */
878struct sf_tx_bufdesc_type4 {
892#ifdef __i386__
893 u_int32_t sf_pad;
894#endif
895 struct mbuf *sf_mbuf;
896 u_int32_t sf_rsvd0:24,
897 sf_crcen:1,
898 sf_caltcp:1,
899 sf_end:1,
900 sf_intr:1,
901 sf_id:4;
902 u_int8_t sf_fragcnt;
903 u_int8_t sf_rsvd2;
904 u_int16_t sf_rsvd1;
905 struct sf_frag_msdos sf_frags[14];
879 uint32_t sf_tx_ctrl;
880 uint32_t sf_tx_frag;
881 /*
882 * Depending on descriptor spacing/skip field length it
883 * can have fixed number of struct sf_frag_msdos.
884 *
885 * struct sf_frag_msdos sf_frags[14];
886 */
906};
907
908/*
909 * Transmit completion queue descriptor formats.
910 */
911
912/*
913 * Transmit DMA completion descriptor, type 0.
914 */
887};
888
889/*
890 * Transmit completion queue descriptor formats.
891 */
892
893/*
894 * Transmit DMA completion descriptor, type 0.
895 */
915#define SF_TXCMPTYPE_DMA 0x4
896#define SF_TXCMPTYPE_DMA 0x80000000
897#define SF_TXCMPTYPE_TX 0xa0000000
916struct sf_tx_cmpdesc_type0 {
898struct sf_tx_cmpdesc_type0 {
917 u_int32_t sf_index:15,
918 sf_priority:1,
919 sf_timestamp:13,
920 sf_type:3;
899 uint32_t sf_tx_status1;
900#define SF_TX_CMPDESC_IDX 0x00007fff
901#define SF_TX_CMPDESC_HIPRI 0x00008000
902#define SF_TX_CMPDESC_STAT 0x1fff0000
903#define SF_TX_CMPDESC_TYPE 0xe0000000
921};
922
923/*
924 * Transmit completion descriptor, type 1.
925 */
904};
905
906/*
907 * Transmit completion descriptor, type 1.
908 */
926#define SF_TXCMPTYPE_TX 0x5
927struct sf_tx_cmpdesc_type1 {
909struct sf_tx_cmpdesc_type1 {
928 u_int32_t sf_index:15,
929 sf_priority:1,
930 sf_txstat:13,
931 sf_type:3;
910 uint32_t sf_tx_status1;
911 uint32_t sf_tx_status2;
932};
933
912};
913
934#define SF_TXSTAT_CRCERR 0x0001
935#define SF_TXSTAT_LENCHECKERR 0x0002
936#define SF_TXSTAT_LENRANGEERR 0x0004
937#define SF_TXSTAT_TX_OK 0x0008
938#define SF_TXSTAT_TX_DEFERED 0x0010
939#define SF_TXSTAT_EXCESS_DEFER 0x0020
940#define SF_TXSTAT_EXCESS_COLL 0x0040
941#define SF_TXSTAT_LATE_COLL 0x0080
942#define SF_TXSTAT_TOOBIG 0x0100
943#define SF_TXSTAT_TX_UNDERRUN 0x0200
944#define SF_TXSTAT_CTLFRAME_OK 0x0400
945#define SF_TXSTAT_PAUSEFRAME_OK 0x0800
946#define SF_TXSTAT_PAUSED 0x1000
914#define SF_TXSTAT_CRCERR 0x00010000
915#define SF_TXSTAT_LENCHECKERR 0x00020000
916#define SF_TXSTAT_LENRANGEERR 0x00040000
917#define SF_TXSTAT_TX_OK 0x00080000
918#define SF_TXSTAT_TX_DEFERED 0x00100000
919#define SF_TXSTAT_EXCESS_DEFER 0x00200000
920#define SF_TXSTAT_EXCESS_COLL 0x00400000
921#define SF_TXSTAT_LATE_COLL 0x00800000
922#define SF_TXSTAT_TOOBIG 0x01000000
923#define SF_TXSTAT_TX_UNDERRUN 0x02000000
924#define SF_TXSTAT_CTLFRAME_OK 0x04000000
925#define SF_TXSTAT_PAUSEFRAME_OK 0x08000000
926#define SF_TXSTAT_PAUSED 0x10000000
947
948/* Statistics counters. */
949struct sf_stats {
927
928/* Statistics counters. */
929struct sf_stats {
950 u_int32_t sf_tx_frames;
951 u_int32_t sf_tx_single_colls;
952 u_int32_t sf_tx_multi_colls;
953 u_int32_t sf_tx_crcerrs;
954 u_int32_t sf_tx_bytes;
955 u_int32_t sf_tx_defered;
956 u_int32_t sf_tx_late_colls;
957 u_int32_t sf_tx_pause_frames;
958 u_int32_t sf_tx_control_frames;
959 u_int32_t sf_tx_excess_colls;
960 u_int32_t sf_tx_excess_defer;
961 u_int32_t sf_tx_mcast_frames;
962 u_int32_t sf_tx_bcast_frames;
963 u_int32_t sf_tx_frames_lost;
964 u_int32_t sf_rx_rx_frames;
965 u_int32_t sf_rx_crcerrs;
966 u_int32_t sf_rx_alignerrs;
967 u_int32_t sf_rx_bytes;
968 u_int32_t sf_rx_control_frames;
969 u_int32_t sf_rx_unsup_control_frames;
970 u_int32_t sf_rx_giants;
971 u_int32_t sf_rx_runts;
972 u_int32_t sf_rx_jabbererrs;
973 u_int32_t sf_rx_pkts_64;
974 u_int32_t sf_rx_pkts_65_127;
975 u_int32_t sf_rx_pkts_128_255;
976 u_int32_t sf_rx_pkts_256_511;
977 u_int32_t sf_rx_pkts_512_1023;
978 u_int32_t sf_rx_pkts_1024_1518;
979 u_int32_t sf_rx_frames_lost;
980 u_int16_t sf_tx_underruns;
981 u_int16_t sf_pad;
930 uint64_t sf_tx_frames;
931 uint32_t sf_tx_single_colls;
932 uint32_t sf_tx_multi_colls;
933 uint32_t sf_tx_crcerrs;
934 uint64_t sf_tx_bytes;
935 uint32_t sf_tx_deferred;
936 uint32_t sf_tx_late_colls;
937 uint32_t sf_tx_pause_frames;
938 uint32_t sf_tx_control_frames;
939 uint32_t sf_tx_excess_colls;
940 uint32_t sf_tx_excess_defer;
941 uint32_t sf_tx_mcast_frames;
942 uint32_t sf_tx_bcast_frames;
943 uint32_t sf_tx_frames_lost;
944 uint64_t sf_rx_frames;
945 uint32_t sf_rx_crcerrs;
946 uint32_t sf_rx_alignerrs;
947 uint64_t sf_rx_bytes;
948 uint32_t sf_rx_pause_frames;
949 uint32_t sf_rx_control_frames;
950 uint32_t sf_rx_unsup_control_frames;
951 uint32_t sf_rx_giants;
952 uint32_t sf_rx_runts;
953 uint32_t sf_rx_jabbererrs;
954 uint32_t sf_rx_fragments;
955 uint64_t sf_rx_pkts_64;
956 uint64_t sf_rx_pkts_65_127;
957 uint64_t sf_rx_pkts_128_255;
958 uint64_t sf_rx_pkts_256_511;
959 uint64_t sf_rx_pkts_512_1023;
960 uint64_t sf_rx_pkts_1024_1518;
961 uint32_t sf_rx_frames_lost;
962 uint32_t sf_tx_underruns;
963 uint32_t sf_tx_gfp_stall;
964 uint32_t sf_rx_gfp_stall;
982};
983
984/*
985 * register space access macros
986 */
987#define CSR_WRITE_4(sc, reg, val) \
965};
966
967/*
968 * register space access macros
969 */
970#define CSR_WRITE_4(sc, reg, val) \
988 bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val)
971 bus_write_4((sc)->sf_res, reg, val)
989
990#define CSR_READ_4(sc, reg) \
972
973#define CSR_READ_4(sc, reg) \
991 bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg)
974 bus_read_4((sc)->sf_res, reg)
992
993#define CSR_READ_1(sc, reg) \
975
976#define CSR_READ_1(sc, reg) \
994 bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg)
977 bus_read_1((sc)->sf_res, reg)
995
996
997struct sf_type {
978
979
980struct sf_type {
998 u_int16_t sf_vid;
999 u_int16_t sf_did;
981 uint16_t sf_vid;
982 uint16_t sf_did;
1000 char *sf_name;
983 char *sf_name;
984 uint16_t sf_sdid;
985 char *sf_sname;
1001};
1002
986};
987
1003#define SF_INC(x, y) (x) = (x + 1) % y
988/* Use Tx descriptor type 2 : 64bit buffer descriptor */
989#define sf_tx_rdesc sf_tx_bufdesc_type2
990/* Use Rx descriptor type 1 : 64bit buffer descriptor */
991#define sf_rx_rdesc sf_rx_bufdesc_type1
992/* Use Tx completion type 0 */
993#define sf_tx_rcdesc sf_tx_cmpdesc_type0
994/* Use Rx completion type 2 : checksum */
995#define sf_rx_rcdesc sf_rx_cmpdesc_type2
1004
996
1005#define ETHER_ALIGN 2
997#define SF_TX_DLIST_CNT 256
998#define SF_RX_DLIST_CNT 256
999#define SF_TX_CLIST_CNT 1024
1000#define SF_RX_CLIST_CNT 1024
1001#define SF_TX_DLIST_SIZE (sizeof(struct sf_tx_rdesc) * SF_TX_DLIST_CNT)
1002#define SF_TX_CLIST_SIZE (sizeof(struct sf_tx_rcdesc) * SF_TX_CLIST_CNT)
1003#define SF_RX_DLIST_SIZE (sizeof(struct sf_rx_rdesc) * SF_RX_DLIST_CNT)
1004#define SF_RX_CLIST_SIZE (sizeof(struct sf_rx_rcdesc) * SF_RX_CLIST_CNT)
1005#define SF_RING_ALIGN 256
1006#define SF_RX_ALIGN sizeof(uint32_t)
1007#define SF_MAXTXSEGS 16
1006
1008
1007/*
1008 * Note: alignment is important here: each list must be aligned to
1009 * a 256-byte boundary. It turns out that each ring is some multiple
1010 * of 4K in length, so we can stack them all on top of each other
1011 * and just worry about aligning the whole mess. There's one transmit
1012 * buffer ring and two receive buffer rings: one RX ring is for small
1013 * packets and the other is for large packets. Each buffer ring also
1014 * has a companion completion queue.
1015 */
1016struct sf_list_data {
1017 struct sf_tx_bufdesc_type0 sf_tx_dlist[SF_TX_DLIST_CNT];
1018 struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT];
1019 struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT];
1020#ifdef notdef
1021 /*
1022 * Unfortunately, because the Starfire doesn't allow arbitrary
1023 * byte alignment, we have to copy packets in the RX handler in
1024 * order to align the payload correctly. This means that we
1025 * don't gain anything by having separate large and small descriptor
1026 * lists, so for now we don't bother with the small one.
1027 */
1028 struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT];
1029#endif
1030 struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT];
1009#define SF_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff)
1010#define SF_ADDR_HI(x) ((uint64_t)(x) >> 32)
1011#define SF_TX_DLIST_ADDR(sc, i) \
1012 ((sc)->sf_rdata.sf_tx_ring_paddr + sizeof(struct sf_tx_rdesc) * (i))
1013#define SF_TX_CLIST_ADDR(sc, i) \
1014 ((sc)->sf_rdata.sf_tx_cring_paddr + sizeof(struct sf_tx_crdesc) * (i))
1015#define SF_RX_DLIST_ADDR(sc, i) \
1016 ((sc)->sf_rdata.sf_rx_ring_paddr + sizeof(struct sf_rx_rdesc) * (i))
1017#define SF_RX_CLIST_ADDR(sc, i) \
1018 ((sc)->sf_rdata.sf_rx_cring_paddr + sizeof(struct sf_rx_rcdesc) * (i))
1019
1020#define SF_INC(x, y) (x) = ((x) + 1) % y
1021
1022#define SF_MAX_FRAMELEN 1536
1023#define SF_TX_THRESHOLD_UNIT 16
1024#define SF_MAX_TX_THRESHOLD (SF_MAX_FRAMELEN / SF_TX_THRESHOLD_UNIT)
1025#define SF_MIN_TX_THRESHOLD (128 / SF_TX_THRESHOLD_UNIT)
1026
1027struct sf_txdesc {
1028 struct mbuf *tx_m;
1029 int ndesc;
1030 bus_dmamap_t tx_dmamap;
1031};
1032
1031};
1032
1033struct sf_rxdesc {
1034 struct mbuf *rx_m;
1035 bus_dmamap_t rx_dmamap;
1036};
1037
1038struct sf_chain_data {
1039 bus_dma_tag_t sf_parent_tag;
1040 bus_dma_tag_t sf_tx_tag;
1041 struct sf_txdesc sf_txdesc[SF_TX_DLIST_CNT];
1042 bus_dma_tag_t sf_rx_tag;
1043 struct sf_rxdesc sf_rxdesc[SF_RX_DLIST_CNT];
1044 bus_dma_tag_t sf_tx_ring_tag;
1045 bus_dma_tag_t sf_rx_ring_tag;
1046 bus_dma_tag_t sf_tx_cring_tag;
1047 bus_dma_tag_t sf_rx_cring_tag;
1048 bus_dmamap_t sf_tx_ring_map;
1049 bus_dmamap_t sf_rx_ring_map;
1050 bus_dmamap_t sf_rx_sparemap;
1051 bus_dmamap_t sf_tx_cring_map;
1052 bus_dmamap_t sf_rx_cring_map;
1053 int sf_tx_prod;
1054 int sf_tx_cnt;
1055 int sf_txc_cons;
1056 int sf_rxc_cons;
1057};
1058
1059struct sf_ring_data {
1060 struct sf_tx_rdesc *sf_tx_ring;
1061 bus_addr_t sf_tx_ring_paddr;
1062 struct sf_tx_rcdesc *sf_tx_cring;
1063 bus_addr_t sf_tx_cring_paddr;
1064 struct sf_rx_rdesc *sf_rx_ring;
1065 bus_addr_t sf_rx_ring_paddr;
1066 struct sf_rx_rcdesc *sf_rx_cring;
1067 bus_addr_t sf_rx_cring_paddr;
1068};
1069
1070
1033struct sf_softc {
1034 struct ifnet *sf_ifp; /* interface info */
1035 device_t sf_dev; /* device info */
1071struct sf_softc {
1072 struct ifnet *sf_ifp; /* interface info */
1073 device_t sf_dev; /* device info */
1036 bus_space_handle_t sf_bhandle; /* bus space handle */
1037 bus_space_tag_t sf_btag; /* bus space tag */
1038 void *sf_intrhand; /* interrupt handler cookie */
1039 struct resource *sf_irq; /* irq resource descriptor */
1040 struct resource *sf_res; /* mem/ioport resource */
1074 void *sf_intrhand; /* interrupt handler cookie */
1075 struct resource *sf_irq; /* irq resource descriptor */
1076 struct resource *sf_res; /* mem/ioport resource */
1077 int sf_restype;
1078 int sf_rid;
1041 struct sf_type *sf_info; /* Starfire adapter info */
1042 device_t sf_miibus;
1079 struct sf_type *sf_info; /* Starfire adapter info */
1080 device_t sf_miibus;
1043 struct sf_list_data *sf_ldata;
1044 int sf_tx_cnt;
1045 u_int8_t sf_link;
1081 struct sf_chain_data sf_cdata;
1082 struct sf_ring_data sf_rdata;
1046 int sf_if_flags;
1083 int sf_if_flags;
1047 struct callout sf_stat_callout;
1084 struct callout sf_co;
1085 int sf_watchdog_timer;
1086 struct task sf_link_task;
1087 int sf_link;
1088 int sf_suspended;
1089 int sf_detach;
1090 uint32_t sf_txthresh;
1091 int sf_int_mod;
1092 struct sf_stats sf_statistics;
1048 struct mtx sf_mtx;
1049#ifdef DEVICE_POLLING
1050 int rxcycles;
1051#endif /* DEVICE_POLLING */
1052};
1053
1054
1055#define SF_LOCK(_sc) mtx_lock(&(_sc)->sf_mtx)
1056#define SF_UNLOCK(_sc) mtx_unlock(&(_sc)->sf_mtx)
1057#define SF_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sf_mtx, MA_OWNED)
1058
1059#define SF_TIMEOUT 1000
1093 struct mtx sf_mtx;
1094#ifdef DEVICE_POLLING
1095 int rxcycles;
1096#endif /* DEVICE_POLLING */
1097};
1098
1099
1100#define SF_LOCK(_sc) mtx_lock(&(_sc)->sf_mtx)
1101#define SF_UNLOCK(_sc) mtx_unlock(&(_sc)->sf_mtx)
1102#define SF_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sf_mtx, MA_OWNED)
1103
1104#define SF_TIMEOUT 1000