| ppcreg.h (42482) | ppcreg.h (43433) |
|---|---|
| 1/*- 2 * Copyright (c) 1997 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 1997 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $Id: ppcreg.h,v 1.6 1999/01/10 12:04:53 nsouch Exp $ | 26 * $Id: ppcreg.h,v 1.7 1999/01/10 16:41:13 nsouch Exp $ |
| 27 * 28 */ 29#ifndef __PPCREG_H 30#define __PPCREG_H 31 32/* 33 * Parallel Port Chipset type. 34 */ --- 62 unchanged lines hidden (view full) --- 97 98/* 99 * Parallel Port Chipset registers. 100 */ 101#define PPC_SPP_DTR 0 /* SPP data register */ 102#define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */ 103#define PPC_SPP_STR 1 /* SPP status register */ 104#define PPC_SPP_CTR 2 /* SPP control register */ | 27 * 28 */ 29#ifndef __PPCREG_H 30#define __PPCREG_H 31 32/* 33 * Parallel Port Chipset type. 34 */ --- 62 unchanged lines hidden (view full) --- 97 98/* 99 * Parallel Port Chipset registers. 100 */ 101#define PPC_SPP_DTR 0 /* SPP data register */ 102#define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */ 103#define PPC_SPP_STR 1 /* SPP status register */ 104#define PPC_SPP_CTR 2 /* SPP control register */ |
| 105#define PPC_EPP_ADDR 3 /* EPP address register (8 bit) */ |
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| 105#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */ 106#define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */ 107#define PPC_ECP_CNFGA 0x400 /* Configuration register A */ 108#define PPC_ECP_CNFGB 0x401 /* Configuration register B */ 109#define PPC_ECP_ECR 0x402 /* ECP extended control register */ 110 111#define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */ 112#define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */ --- 7 unchanged lines hidden (view full) --- 120#define PPC_ECR_EPP 0x80 121 122#define PPC_DISABLE_INTR (PPC_SERVICE_INTR | PPC_nFAULT_INTR) 123#define PPC_ECR_RESET (PPC_ECR_PS2 | PPC_DISABLE_INTR) 124 125#define r_dtr(ppc) (inb((ppc)->ppc_base + PPC_SPP_DTR)) 126#define r_str(ppc) (inb((ppc)->ppc_base + PPC_SPP_STR)) 127#define r_ctr(ppc) (inb((ppc)->ppc_base + PPC_SPP_CTR)) | 106#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */ 107#define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */ 108#define PPC_ECP_CNFGA 0x400 /* Configuration register A */ 109#define PPC_ECP_CNFGB 0x401 /* Configuration register B */ 110#define PPC_ECP_ECR 0x402 /* ECP extended control register */ 111 112#define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */ 113#define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */ --- 7 unchanged lines hidden (view full) --- 121#define PPC_ECR_EPP 0x80 122 123#define PPC_DISABLE_INTR (PPC_SERVICE_INTR | PPC_nFAULT_INTR) 124#define PPC_ECR_RESET (PPC_ECR_PS2 | PPC_DISABLE_INTR) 125 126#define r_dtr(ppc) (inb((ppc)->ppc_base + PPC_SPP_DTR)) 127#define r_str(ppc) (inb((ppc)->ppc_base + PPC_SPP_STR)) 128#define r_ctr(ppc) (inb((ppc)->ppc_base + PPC_SPP_CTR)) |
| 128#define r_epp(ppc) (inb((ppc)->ppc_base + PPC_EPP_DATA)) | 129#define r_epp_A(ppc) (inb((ppc)->ppc_base + PPC_EPP_ADDR)) 130#define r_epp_D(ppc) (inb((ppc)->ppc_base + PPC_EPP_DATA)) |
| 129#define r_cnfgA(ppc) (inb((ppc)->ppc_base + PPC_ECP_CNFGA)) 130#define r_cnfgB(ppc) (inb((ppc)->ppc_base + PPC_ECP_CNFGB)) 131#define r_ecr(ppc) (inb((ppc)->ppc_base + PPC_ECP_ECR)) 132#define r_fifo(ppc) (inb((ppc)->ppc_base + PPC_ECP_D_FIFO)) 133 134#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte) 135#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte) 136#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte) | 131#define r_cnfgA(ppc) (inb((ppc)->ppc_base + PPC_ECP_CNFGA)) 132#define r_cnfgB(ppc) (inb((ppc)->ppc_base + PPC_ECP_CNFGB)) 133#define r_ecr(ppc) (inb((ppc)->ppc_base + PPC_ECP_ECR)) 134#define r_fifo(ppc) (inb((ppc)->ppc_base + PPC_ECP_D_FIFO)) 135 136#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte) 137#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte) 138#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte) |
| 137#define w_epp(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte) | 139#define w_epp_A(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_ADDR, byte) 140#define w_epp_D(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte) |
| 138#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte) 139#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_D_FIFO, byte) 140 141/* 142 * Register defines for the PC873xx parts 143 */ 144 145#define PC873_FER 0x00 --- 77 unchanged lines hidden --- | 141#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte) 142#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_D_FIFO, byte) 143 144/* 145 * Register defines for the PC873xx parts 146 */ 147 148#define PC873_FER 0x00 --- 77 unchanged lines hidden --- |