1/*-
2 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software without specific prior written permission
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 *
25 */
26
27#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software without specific prior written permission
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 *
25 */
26
27#include <sys/cdefs.h>
|
28__FBSDID("$FreeBSD: head/sys/dev/pdq/if_fpa.c 152296 2005-11-11 07:36:14Z ru $");
| 28__FBSDID("$FreeBSD: head/sys/dev/pdq/if_fpa.c 166914 2007-02-23 19:34:52Z imp $");
|
29
30/*
31 * DEC PDQ FDDI Controller; code for BSD derived operating systems
32 *
33 * This module supports the DEC DEFPA PCI FDDI Controller
34 */
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/kernel.h>
39#include <sys/socket.h>
40
41#include <sys/module.h>
42#include <sys/bus.h>
43
44#include <machine/bus.h>
45#include <machine/resource.h>
46#include <sys/rman.h>
47
48#include <net/if.h>
49#include <net/if_media.h>
50#include <net/fddi.h>
51
52#include <dev/pci/pcivar.h>
53#include <dev/pci/pcireg.h>
54
55#include <dev/pdq/pdq_freebsd.h>
56#include <dev/pdq/pdqreg.h>
57
58#define DEC_VENDORID 0x1011
59#define DEFPA_CHIPID 0x000F
60
61#define DEFPA_LATENCY 0x88
62
63#define PCI_CFLT 0x0C /* Configuration Latency */
64#define PCI_CBMA 0x10 /* Configuration Base Memory Address */
65#define PCI_CBIO 0x14 /* Configuration Base I/O Address */
66
67static int pdq_pci_probe (device_t);
68static int pdq_pci_attach (device_t);
69static int pdq_pci_detach (device_t);
70static void pdq_pci_shutdown (device_t);
71static void pdq_pci_ifintr (void *);
72
73static void
74pdq_pci_ifintr(void *arg)
75{
76 device_t dev;
77 pdq_softc_t *sc;
78
79 dev = (device_t)arg;
80 sc = device_get_softc(dev);
81
82 PDQ_LOCK(sc);
83 (void) pdq_interrupt(sc->sc_pdq);
84 PDQ_UNLOCK(sc);
85
86 return;
87}
88
89/*
90 * This is the PCI configuration support.
91 */
92static int
93pdq_pci_probe(device_t dev)
94{
95 if (pci_get_vendor(dev) == DEC_VENDORID &&
96 pci_get_device(dev) == DEFPA_CHIPID) {
97 device_set_desc(dev, "Digital DEFPA PCI FDDI Controller");
98 return (BUS_PROBE_DEFAULT);
99 }
100
101 return (ENXIO);
102}
103
104static int
105pdq_pci_attach(device_t dev)
106{
107 pdq_softc_t *sc;
108 struct ifnet *ifp;
109 u_int32_t command;
110 int error;
111
112 sc = device_get_softc(dev);
113 ifp = sc->ifp;
114
115 sc->dev = dev;
116
117 /*
118 * Map control/status registers.
119 */
120 pci_enable_busmaster(dev);
121
122 command = pci_read_config(dev, PCIR_LATTIMER, 1);
123 if (command < DEFPA_LATENCY) {
124 command = DEFPA_LATENCY;
125 pci_write_config(dev, PCIR_LATTIMER, command, 1);
126 }
127
128 sc->mem_rid = PCI_CBMA;
129 sc->mem_type = SYS_RES_MEMORY;
130 sc->mem = bus_alloc_resource_any(dev, sc->mem_type, &sc->mem_rid,
131 RF_ACTIVE);
132 if (!sc->mem) {
133 device_printf(dev, "Unable to allocate I/O space resource.\n");
134 error = ENXIO;
135 goto bad;
136 }
137 sc->mem_bsh = rman_get_bushandle(sc->mem);
138 sc->mem_bst = rman_get_bustag(sc->mem);
139
140 sc->irq_rid = 0;
141 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
142 RF_SHAREABLE | RF_ACTIVE);
143 if (!sc->irq) {
144 device_printf(dev, "Unable to allocate interrupt resource.\n");
145 error = ENXIO;
146 goto bad;
147 }
148
149 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
150
151 sc->sc_pdq = pdq_initialize(sc->mem_bst, sc->mem_bsh,
152 ifp->if_xname, -1,
153 (void *)sc, PDQ_DEFPA);
154 if (sc->sc_pdq == NULL) {
155 device_printf(dev, "Initialization failed.\n");
156 error = ENXIO;
157 goto bad;
158 }
159
| 29
30/*
31 * DEC PDQ FDDI Controller; code for BSD derived operating systems
32 *
33 * This module supports the DEC DEFPA PCI FDDI Controller
34 */
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/kernel.h>
39#include <sys/socket.h>
40
41#include <sys/module.h>
42#include <sys/bus.h>
43
44#include <machine/bus.h>
45#include <machine/resource.h>
46#include <sys/rman.h>
47
48#include <net/if.h>
49#include <net/if_media.h>
50#include <net/fddi.h>
51
52#include <dev/pci/pcivar.h>
53#include <dev/pci/pcireg.h>
54
55#include <dev/pdq/pdq_freebsd.h>
56#include <dev/pdq/pdqreg.h>
57
58#define DEC_VENDORID 0x1011
59#define DEFPA_CHIPID 0x000F
60
61#define DEFPA_LATENCY 0x88
62
63#define PCI_CFLT 0x0C /* Configuration Latency */
64#define PCI_CBMA 0x10 /* Configuration Base Memory Address */
65#define PCI_CBIO 0x14 /* Configuration Base I/O Address */
66
67static int pdq_pci_probe (device_t);
68static int pdq_pci_attach (device_t);
69static int pdq_pci_detach (device_t);
70static void pdq_pci_shutdown (device_t);
71static void pdq_pci_ifintr (void *);
72
73static void
74pdq_pci_ifintr(void *arg)
75{
76 device_t dev;
77 pdq_softc_t *sc;
78
79 dev = (device_t)arg;
80 sc = device_get_softc(dev);
81
82 PDQ_LOCK(sc);
83 (void) pdq_interrupt(sc->sc_pdq);
84 PDQ_UNLOCK(sc);
85
86 return;
87}
88
89/*
90 * This is the PCI configuration support.
91 */
92static int
93pdq_pci_probe(device_t dev)
94{
95 if (pci_get_vendor(dev) == DEC_VENDORID &&
96 pci_get_device(dev) == DEFPA_CHIPID) {
97 device_set_desc(dev, "Digital DEFPA PCI FDDI Controller");
98 return (BUS_PROBE_DEFAULT);
99 }
100
101 return (ENXIO);
102}
103
104static int
105pdq_pci_attach(device_t dev)
106{
107 pdq_softc_t *sc;
108 struct ifnet *ifp;
109 u_int32_t command;
110 int error;
111
112 sc = device_get_softc(dev);
113 ifp = sc->ifp;
114
115 sc->dev = dev;
116
117 /*
118 * Map control/status registers.
119 */
120 pci_enable_busmaster(dev);
121
122 command = pci_read_config(dev, PCIR_LATTIMER, 1);
123 if (command < DEFPA_LATENCY) {
124 command = DEFPA_LATENCY;
125 pci_write_config(dev, PCIR_LATTIMER, command, 1);
126 }
127
128 sc->mem_rid = PCI_CBMA;
129 sc->mem_type = SYS_RES_MEMORY;
130 sc->mem = bus_alloc_resource_any(dev, sc->mem_type, &sc->mem_rid,
131 RF_ACTIVE);
132 if (!sc->mem) {
133 device_printf(dev, "Unable to allocate I/O space resource.\n");
134 error = ENXIO;
135 goto bad;
136 }
137 sc->mem_bsh = rman_get_bushandle(sc->mem);
138 sc->mem_bst = rman_get_bustag(sc->mem);
139
140 sc->irq_rid = 0;
141 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
142 RF_SHAREABLE | RF_ACTIVE);
143 if (!sc->irq) {
144 device_printf(dev, "Unable to allocate interrupt resource.\n");
145 error = ENXIO;
146 goto bad;
147 }
148
149 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
150
151 sc->sc_pdq = pdq_initialize(sc->mem_bst, sc->mem_bsh,
152 ifp->if_xname, -1,
153 (void *)sc, PDQ_DEFPA);
154 if (sc->sc_pdq == NULL) {
155 device_printf(dev, "Initialization failed.\n");
156 error = ENXIO;
157 goto bad;
158 }
159
|
160 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
| 160 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, NULL,
|
161 pdq_pci_ifintr, dev, &sc->irq_ih);
162 if (error) {
163 device_printf(dev, "Failed to setup interrupt handler.\n");
164 error = ENXIO;
165 goto bad;
166 }
167
168 pdq_ifattach(sc, sc->sc_pdq->pdq_hwaddr.lanaddr_bytes);
169
170 return (0);
171bad:
172 pdq_free(dev);
173 return (error);
174}
175
176static int
177pdq_pci_detach (dev)
178 device_t dev;
179{
180 pdq_softc_t *sc;
181
182 sc = device_get_softc(dev);
183 pdq_ifdetach(sc);
184
185 return (0);
186}
187
188static void
189pdq_pci_shutdown(device_t dev)
190{
191 pdq_softc_t *sc;
192
193 sc = device_get_softc(dev);
194 pdq_hwreset(sc->sc_pdq);
195
196 return;
197}
198
199static device_method_t pdq_pci_methods[] = {
200 /* Device interface */
201 DEVMETHOD(device_probe, pdq_pci_probe),
202 DEVMETHOD(device_attach, pdq_pci_attach),
203 DEVMETHOD(device_detach, pdq_pci_detach),
204 DEVMETHOD(device_shutdown, pdq_pci_shutdown),
205
206 { 0, 0 }
207};
208
209static driver_t pdq_pci_driver = {
210 "fpa",
211 pdq_pci_methods,
212 sizeof(pdq_softc_t),
213};
214
215DRIVER_MODULE(fpa, pci, pdq_pci_driver, pdq_devclass, 0, 0);
216MODULE_DEPEND(fpa, pci, 1, 1, 1);
217MODULE_DEPEND(fpa, fddi, 1, 1, 1);
| 161 pdq_pci_ifintr, dev, &sc->irq_ih);
162 if (error) {
163 device_printf(dev, "Failed to setup interrupt handler.\n");
164 error = ENXIO;
165 goto bad;
166 }
167
168 pdq_ifattach(sc, sc->sc_pdq->pdq_hwaddr.lanaddr_bytes);
169
170 return (0);
171bad:
172 pdq_free(dev);
173 return (error);
174}
175
176static int
177pdq_pci_detach (dev)
178 device_t dev;
179{
180 pdq_softc_t *sc;
181
182 sc = device_get_softc(dev);
183 pdq_ifdetach(sc);
184
185 return (0);
186}
187
188static void
189pdq_pci_shutdown(device_t dev)
190{
191 pdq_softc_t *sc;
192
193 sc = device_get_softc(dev);
194 pdq_hwreset(sc->sc_pdq);
195
196 return;
197}
198
199static device_method_t pdq_pci_methods[] = {
200 /* Device interface */
201 DEVMETHOD(device_probe, pdq_pci_probe),
202 DEVMETHOD(device_attach, pdq_pci_attach),
203 DEVMETHOD(device_detach, pdq_pci_detach),
204 DEVMETHOD(device_shutdown, pdq_pci_shutdown),
205
206 { 0, 0 }
207};
208
209static driver_t pdq_pci_driver = {
210 "fpa",
211 pdq_pci_methods,
212 sizeof(pdq_softc_t),
213};
214
215DRIVER_MODULE(fpa, pci, pdq_pci_driver, pdq_devclass, 0, 0);
216MODULE_DEPEND(fpa, pci, 1, 1, 1);
217MODULE_DEPEND(fpa, fddi, 1, 1, 1);
|