1/**************************************************************************
2**
3** $Id: pcireg.h,v 1.13 1997/04/20 06:57:43 phk Exp $
4**
5** Names for PCI configuration space registers.
6**
7** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.
8**
9**
10** Redistribution and use in source and binary forms, with or without
11** modification, are permitted provided that the following conditions
12** are met:
13** 1. Redistributions of source code must retain the above copyright
14** notice, this list of conditions and the following disclaimer.
15** 2. Redistributions in binary form must reproduce the above copyright
16** notice, this list of conditions and the following disclaimer in the
17** documentation and/or other materials provided with the distribution.
18** 3. The name of the author may not be used to endorse or promote products
19** derived from this software without specific prior written permission.
20**
21** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31**
32***************************************************************************
33*/
34
35#ifndef __PCI_REG_H__
36#define __PCI_REG_H__ "pl2 95/03/21"
37
| 1#ifndef PCI_COMPAT
2#define PCI_COMPAT
3#endif
|
38/*
| 4/*
|
39** Device identification register; contains a vendor ID and a device ID.
40** We have little need to distinguish the two parts.
41*/
42#define PCI_ID_REG 0x00
| 5 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $Id$
30 *
31 */
|
43
44/*
| 32
33/*
|
45** Command and status register.
46*/
47#define PCI_COMMAND_STATUS_REG 0x04
| 34 * PCIM_xxx: mask to locate subfield in register
35 * PCIR_xxx: config register offset
36 * PCIC_xxx: device class
37 * PCIS_xxx: device subclass
38 * PCIP_xxx: device programming interface
39 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
40 * PCID_xxx: device ID
41 */
|
48
| 42
|
49#define PCI_COMMAND_IO_ENABLE 0x00000001
50#define PCI_COMMAND_MEM_ENABLE 0x00000002
51#define PCI_COMMAND_MASTER_ENABLE 0x00000004
52#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008
53#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010
54#define PCI_COMMAND_PALETTE_ENABLE 0x00000020
55#define PCI_COMMAND_PARITY_ENABLE 0x00000040
56#define PCI_COMMAND_STEPPING_ENABLE 0x00000080
57#define PCI_COMMAND_SERR_ENABLE 0x00000100
58#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
| 43/* some PCI bus constants */
|
59
| 44
|
60#define PCI_STATUS_BACKTOBACK_OKAY 0x00800000
61#define PCI_STATUS_PARITY_ERROR 0x01000000
62#define PCI_STATUS_DEVSEL_FAST 0x00000000
63#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000
64#define PCI_STATUS_DEVSEL_SLOW 0x04000000
65#define PCI_STATUS_DEVSEL_MASK 0x06000000
66#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000
67#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000
68#define PCI_STATUS_MASTER_ABORT 0x20000000
69#define PCI_STATUS_SPECIAL_ERROR 0x40000000
70#define PCI_STATUS_PARITY_DETECT 0x80000000
| 45#define PCI_BUSMAX 255
46#define PCI_SLOTMAX 31
47#define PCI_FUNCMAX 7
48#define PCI_REGMAX 255
|
71
| 49
|
72/*
73** Class register; defines basic type of device.
74*/
75#define PCI_CLASS_REG 0x08
| 50/* PCI config header registers for all devices */
|
76
| 51
|
77#define PCI_CLASS_MASK 0xff000000
78#define PCI_SUBCLASS_MASK 0x00ff0000
| 52#define PCIR_DEVVENDOR 0x00
53#define PCIR_VENDOR 0x00
54#define PCIR_DEVICE 0x02
55#define PCIR_COMMAND 0x04
56#define PCIR_STATUS 0x06
57#define PCIR_REVID 0x08
58#define PCIR_PROGIF 0x09
59#define PCIR_SUBCLASS 0x0a
60#define PCIR_CLASS 0x0b
61#define PCIR_CACHELNSZ 0x0c
62#define PCIR_LATTIMER 0x0d
63#define PCIR_HEADERTYPE 0x0e
64#define PCIM_MFDEV 0x80
65#define PCIR_BIST 0x0f
|
79
| 66
|
80/* base classes */
81#define PCI_CLASS_PREHISTORIC 0x00000000
82#define PCI_CLASS_MASS_STORAGE 0x01000000
83#define PCI_CLASS_NETWORK 0x02000000
84#define PCI_CLASS_DISPLAY 0x03000000
85#define PCI_CLASS_MULTIMEDIA 0x04000000
86#define PCI_CLASS_MEMORY 0x05000000
87#define PCI_CLASS_BRIDGE 0x06000000
88#define PCI_CLASS_UNDEFINED 0xff000000
| 67/* config registers for header type 0 devices */
|
89
| 68
|
90/* 0x00 prehistoric subclasses */
91#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00000000
92#define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000
| 69#define PCIR_MAPS 0x10
70#define PCIR_CARDBUSCIS 0x28
71#define PCIR_SUBVEND_0 0x2c
72#define PCIR_SUBDEV_0 0x2e
73#define PCIR_INTLINE 0x3c
74#define PCIR_INTPIN 0x3d
75#define PCIR_MINGNT 0x3e
76#define PCIR_MAXLAT 0x3f
|
93
| 77
|
94/* 0x01 mass storage subclasses */
95#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000
96#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x00010000
97#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x00020000
98#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x00030000
99#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x00800000
| 78/* config registers for header type 1 devices */
|
100
| 79
|
101/* 0x02 network subclasses */
102#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00000000
103#define PCI_SUBCLASS_NETWORK_TOKENRING 0x00010000
104#define PCI_SUBCLASS_NETWORK_FDDI 0x00020000
105#define PCI_SUBCLASS_NETWORK_MISC 0x00800000
| 80#define PCIR_SECSTAT_1 0 /**/
|
106
| 81
|
107/* 0x03 display subclasses */
108#define PCI_SUBCLASS_DISPLAY_VGA 0x00000000
109#define PCI_SUBCLASS_DISPLAY_XGA 0x00010000
110#define PCI_SUBCLASS_DISPLAY_MISC 0x00800000
| 82#define PCIR_PRIBUS_1 0x18
83#define PCIR_SECBUS_1 0x19
84#define PCIR_SUBBUS_1 0x1a
85#define PCIR_SECLAT_1 0x1b
|
111
| 86
|
112/* 0x04 multimedia subclasses */
113#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00000000
114#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x00010000
115#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x00800000
| 87#define PCIR_IOBASEL_1 0x1c
88#define PCIR_IOLIMITL_1 0x1d
89#define PCIR_IOBASEH_1 0 /**/
90#define PCIR_IOLIMITH_1 0 /**/
|
116
| 91
|
117/* 0x05 memory subclasses */
118#define PCI_SUBCLASS_MEMORY_RAM 0x00000000
119#define PCI_SUBCLASS_MEMORY_FLASH 0x00010000
120#define PCI_SUBCLASS_MEMORY_MISC 0x00800000
| 92#define PCIR_MEMBASE_1 0x20
93#define PCIR_MEMLIMIT_1 0x22
|
121
| 94
|
122/* 0x06 bridge subclasses */
123#define PCI_SUBCLASS_BRIDGE_HOST 0x00000000
124#define PCI_SUBCLASS_BRIDGE_ISA 0x00010000
125#define PCI_SUBCLASS_BRIDGE_EISA 0x00020000
126#define PCI_SUBCLASS_BRIDGE_MC 0x00030000
127#define PCI_SUBCLASS_BRIDGE_PCI 0x00040000
128#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x00050000
129#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x00070000
130#define PCI_SUBCLASS_BRIDGE_MISC 0x00800000
| 95#define PCIR_PMBASEL_1 0x24
96#define PCIR_PMLIMITL_1 0x26
97#define PCIR_PMBASEH_1 0 /**/
98#define PCIR_PMLIMITH_1 0 /**/
|
131
| 99
|
132/*
133** Header registers
134*/
135#define PCI_HEADER_MISC 0x0c
| 100#define PCIR_BRIDGECTL_1 0 /**/
|
136
| 101
|
137#define PCI_HEADER_MULTIFUNCTION 0x00800000
| 102#define PCIR_SUBVEND_1 0x34
103#define PCIR_SUBDEV_1 0x36
|
138
| 104
|
139/*
140** Mapping registers
141*/
142#define PCI_MAP_REG_START 0x10
143#define PCI_MAP_REG_END 0x28
| 105/* config registers for header type 2 devices */
|
144
| 106
|
145#define PCI_MAP_MEMORY 0x00000000
146#define PCI_MAP_IO 0x00000001
| 107#define PCIR_SECSTAT_2 0x16
|
147
| 108
|
148#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000
149#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002
150#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004
151#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006
152#define PCI_MAP_MEMORY_CACHABLE 0x00000008
153#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0
| 109#define PCIR_PRIBUS_2 0x18
110#define PCIR_SECBUS_2 0x19
111#define PCIR_SUBBUS_2 0x1a
112#define PCIR_SECLAT_2 0x1b
|
154
| 113
|
155#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc
156/*
157** PCI-PCI bridge mapping registers
158*/
159#define PCI_PCI_BRIDGE_BUS_REG 0x18
160#define PCI_PCI_BRIDGE_IO_REG 0x1c
161#define PCI_PCI_BRIDGE_MEM_REG 0x20
162#define PCI_PCI_BRIDGE_PMEM_REG 0x24
| 114#define PCIR_MEMBASE0_2 0x1c
115#define PCIR_MEMLIMIT0_2 0x20
116#define PCIR_MEMBASE1_2 0x24
117#define PCIR_MEMLIMIT1_2 0x28
118#define PCIR_IOBASE0_2 0x2c
119#define PCIR_IOLIMIT0_2 0x30
120#define PCIR_IOBASE1_2 0x34
121#define PCIR_IOLIMIT1_2 0x38
|
163
| 122
|
164#define PCI_SUBID_REG0 0x2c
165#define PCI_SUBID_REG1 0x34
166#define PCI_SUBID_REG2 0x40
| 123#define PCIR_BRIDGECTL_2 0x3e
|
167
| 124
|
168#define PCI_SUBORDINATE_BUS_MASK 0x00ff0000
169#define PCI_SECONDARY_BUS_MASK 0x0000ff00
170#define PCI_PRIMARY_BUS_MASK 0x000000ff
| 125#define PCIR_SUBVEND_2 0x40
126#define PCIR_SUBDEV_2 0x42
|
171
| 127
|
172#define PCI_SUBORDINATE_BUS_EXTRACT(x) (((x) >> 16) & 0xff)
173#define PCI_SECONDARY_BUS_EXTRACT(x) (((x) >> 8) & 0xff)
174#define PCI_PRIMARY_BUS_EXTRACT(x) (((x) ) & 0xff)
| 128#define PCIR_PCCARDIF_2 0x44
|
175
| 129
|
176#define PCI_PRIMARY_BUS_INSERT(x, y) (((x) & ~PCI_PRIMARY_BUS_MASK) | ((y) << 0))
177#define PCI_SECONDARY_BUS_INSERT(x, y) (((x) & ~PCI_SECONDARY_BUS_MASK) | ((y) << 8))
178#define PCI_SUBORDINATE_BUS_INSERT(x, y) (((x) & ~PCI_SUBORDINATE_BUS_MASK) | ((y) << 16))
| 130/* PCI device class, subclass and programming interface definitions */
|
179
| 131
|
180#define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xF000)
181#define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xF000 | 0x0FFF)
| 132#define PCIC_OLD 0x00
133#define PCIS_OLD_NONVGA 0x00
134#define PCIS_OLD_VGA 0x01
|
182
| 135
|
183#define PCI_PPB_MEMBASE_EXTRACT(x) (((x) << 16) & 0xFFF00000)
184#define PCI_PPB_MEMLIMIT_EXTRACT(x) (((x) << 0) & 0xFFF00000 | 0x000FFFFF)
| 136#define PCIC_STORAGE 0x01
137#define PCIS_STORAGE_SCSI 0x00
138#define PCIS_STORAGE_IDE 0x01
139#define PCIP_STORAGE_IDE_MODEPRIM 0x01
140#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
141#define PCIP_STORAGE_IDE_MODESEC 0x04
142#define PCIP_STORAGE_IDE_PROGINDSEC 0x08
143#define PCIP_STORAGE_IDE_MASTERDEV 0x80
144#define PCIS_STORAGE_FLOPPY 0x02
145#define PCIS_STORAGE_IPI 0x03
146#define PCIS_STORAGE_RAID 0x04
147#define PCIS_STORAGE_OTHER 0x80
|
185
| 148
|
186/*
187** PCI-Cardbus bridge mapping registers
188*/
189#define PCI_CARDBUS_SOCKET_REG 0x10
| 149#define PCIC_NETWORK 0x02
150#define PCIS_NETWORK_ETHERNET 0x00
151#define PCIS_NETWORK_TOKENRING 0x01
152#define PCIS_NETWORK_FDDI 0x02
153#define PCIS_NETWORK_ATM 0x03
154#define PCIS_NETWORK_OTHER 0x80
|
190
| 155
|
191/*
192** Interrupt configuration register
193*/
194#define PCI_INTERRUPT_REG 0x3c
| 156#define PCIC_DISPLAY 0x03
157#define PCIS_DISPLAY_VGA 0x00
158#define PCIS_DISPLAY_XGA 0x01
159#define PCIS_DISPLAY_OTHER 0x80
|
195
| 160
|
196#define PCI_INTERRUPT_PIN_MASK 0x0000ff00
197#define PCI_INTERRUPT_PIN_EXTRACT(x) ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff)
198#define PCI_INTERRUPT_PIN_NONE 0x00
199#define PCI_INTERRUPT_PIN_A 0x01
200#define PCI_INTERRUPT_PIN_B 0x02
201#define PCI_INTERRUPT_PIN_C 0x03
202#define PCI_INTERRUPT_PIN_D 0x04
| 161#define PCIC_MULTIMEDIA 0x04
162#define PCIS_MULTIMEDIA_VIDEO 0x00
163#define PCIS_MULTIMEDIA_AUDIO 0x01
164#define PCIS_MULTIMEDIA_OTHER 0x80
|
203
| 165
|
204#define PCI_INTERRUPT_LINE_MASK 0x000000ff
205#define PCI_INTERRUPT_LINE_EXTRACT(x) ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff)
206#define PCI_INTERRUPT_LINE_INSERT(x,v) (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0))
| 166#define PCIC_MEMORY 0x05
167#define PCIS_MEMORY_RAM 0x00
168#define PCIS_MEMORY_FLASH 0x01
169#define PCIS_MEMORY_OTHER 0x80
|
207
| 170
|
208#endif /* __PCI_REG_H__ */
| 171#define PCIC_BRIDGE 0x06
172#define PCIS_BRDIGE_HOST 0x00
173#define PCIS_BRIDGE_ISA 0x01
174#define PCIS_BRIDGE_EISA 0x02
175#define PCIS_BRIDGE_MCA 0x03
176#define PCIS_BRIDGE_PCI 0x04
177#define PCIS_BRIDGE_PCMCIA 0x05
178#define PCIS_BRIDGE_NUBUS 0x06
179#define PCIS_BRIDGE_CARDBUS 0x07
180#define PCIS_BRIDGE_OTHER 0x80
181
182#define PCIC_SIMPLECOMM 0x07
183#define PCIS_SIMPLECOMM_UART 0x00
184#define PCIS_SIMPLECOMM_PAR 0x01
185#define PCIS_SIMPLECOMM_OTHER 0x80
186
187#define PCIC_BASEPERIPH 0x08
188#define PCIS_BASEPERIPH_PIC 0x00
189#define PCIS_BASEPERIPH_DMA 0x01
190#define PCIS_BASEPERIPH_TIMER 0x02
191#define PCIS_BASEPERIPH_RTC 0x03
192#define PCIS_BASEPERIPH_OTHER 0x80
193
194#define PCIC_INPUTDEV 0x09
195#define PCIS_INPUTDEV_KEYBOARD 0x00
196#define PCIS_INPUTDEV_DIGITIZER 0x01
197#define PCIS_INPUTDEV_MOUSE 0x02
198#define PCIS_INPUTDEV_OTHER 0x80
199
200#define PCIC_DOCKING 0x0a
201#define PCIS_DOCKING_GENERIC 0x00
202#define PCIS_DOCKING_OTHER 0x80
203
204#define PCIC_PROCESSOR 0x0b
205#define PCIS_PROCESSOR_386 0x00
206#define PCIS_PROCESSOR_486 0x01
207#define PCIS_PROCESSOR_PENTIUM 0x02
208#define PCIS_PROCESSOR_ALPHA 0x10
209#define PCIS_PROCESSOR_POWERPC 0x20
210#define PCIS_PROCESSOR_COPROC 0x40
211
212#define PCIC_SERIALBUS 0x0c
213#define PCIS_SERIALBUS_FW 0x00
214#define PCIS_SERIALBUS_ACCESS 0x01
215#define PCIS_SERIALBUS_SSA 0x02
216#define PCIS_SERIALBUS_USB 0x03
217#define PCIS_SERIALBUS_FC 0x04
218#define PCIS_SERIALBUS
219#define PCIS_SERIALBUS
220
221#define PCIC_OTHER 0xff
222
223/* some PCI vendor definitions (only used to identify ancient devices !!! */
224
225#define PCIV_INTEL 0x8086
226
227#define PCID_INTEL_SATURN 0x0483
228#define PCID_INTEL_ORION 0x84c4
229
230/* for compatibility to FreeBSD-2.2 version of PCI code */
231
232#ifdef PCI_COMPAT
233
234#define PCI_ID_REG 0x00
235#define PCI_COMMAND_STATUS_REG 0x04
236#define PCI_COMMAND_IO_ENABLE 0x00000001
237#define PCI_CLASS_REG 0x08
238#define PCI_CLASS_MASK 0xff000000
239#define PCI_SUBCLASS_MASK 0x00ff0000
240#define PCI_CLASS_PREHISTORIC 0x00000000
241#define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000
242#define PCI_CLASS_DISPLAY 0x03000000
243#define PCI_SUBCLASS_DISPLAY_VGA 0x00000000
244#define PCI_CLASS_BRIDGE 0x06000000
245#define PCI_MAP_REG_START 0x10
246#define PCI_MAP_REG_END 0x28
247#define PCI_MAP_IO 0x00000001
248#define PCI_INTERRUPT_REG 0x3c
249
250#endif /* PCI_COMPAT */
|
| |