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pcireg.h (168157) pcireg.h (168162)
1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/pci/pcireg.h 168157 2007-03-31 20:41:00Z jhb $
26 * $FreeBSD: head/sys/dev/pci/pcireg.h 168162 2007-03-31 21:39:02Z jhb $
27 *
28 */
29
30/*
31 * PCIM_xxx: mask to locate subfield in register
32 * PCIR_xxx: config register offset
33 * PCIC_xxx: device class
34 * PCIS_xxx: device subclass

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113#define PCIY_EXPRESS 0x10 /* PCI Express */
114#define PCIY_MSIX 0x11 /* MSI-X */
115
116/* config registers for header type 0 devices */
117
118#define PCIR_BARS 0x10
119#define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
120#define PCI_RID2BAR(rid) (((rid)-PCIR_BARS)/4)
27 *
28 */
29
30/*
31 * PCIM_xxx: mask to locate subfield in register
32 * PCIR_xxx: config register offset
33 * PCIC_xxx: device class
34 * PCIS_xxx: device subclass

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113#define PCIY_EXPRESS 0x10 /* PCI Express */
114#define PCIY_MSIX 0x11 /* MSI-X */
115
116/* config registers for header type 0 devices */
117
118#define PCIR_BARS 0x10
119#define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
120#define PCI_RID2BAR(rid) (((rid)-PCIR_BARS)/4)
121#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
122#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
123#define PCIM_BAR_SPACE 0x00000001
124#define PCIM_BAR_MEM_SPACE 0
125#define PCIM_BAR_IO_SPACE 1
126#define PCIM_BAR_MEM_TYPE 0x00000006
127#define PCIM_BAR_MEM_32 0
128#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */
129#define PCIM_BAR_MEM_64 4
130#define PCIM_BAR_MEM_PREFETCH 0x00000008
131#define PCIM_BAR_MEM_BASE 0xfffffff0
132#define PCIM_BAR_IO_RESERVED 0x00000002
133#define PCIM_BAR_IO_BASE 0xfffffffc
121#define PCIR_CIS 0x28
122#define PCIM_CIS_ASI_MASK 0x7
123#define PCIM_CIS_ASI_TUPLE 0
124#define PCIM_CIS_ASI_BAR0 1
125#define PCIM_CIS_ASI_BAR1 2
126#define PCIM_CIS_ASI_BAR2 3
127#define PCIM_CIS_ASI_BAR3 4
128#define PCIM_CIS_ASI_BAR4 5

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134#define PCIR_CIS 0x28
135#define PCIM_CIS_ASI_MASK 0x7
136#define PCIM_CIS_ASI_TUPLE 0
137#define PCIM_CIS_ASI_BAR0 1
138#define PCIM_CIS_ASI_BAR1 2
139#define PCIM_CIS_ASI_BAR2 3
140#define PCIM_CIS_ASI_BAR3 4
141#define PCIM_CIS_ASI_BAR4 5

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