1/*- |
2 * Copyright (C) 2013 Emulex |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * --- 22 unchanged lines hidden (view full) --- 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 39 40 |
41/* $FreeBSD: head/sys/dev/oce/oce_mbox.c 252869 2013-07-06 08:30:45Z delphij $ */ |
42 43 44#include "oce_if.h" 45extern uint32_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_NUM_ELE]; 46 47/** 48 * @brief Reset (firmware) common function 49 * @param sc software handle to the device --- 672 unchanged lines hidden (view full) --- 722 * @param *fwcmd pointer to the rss mbox command 723 * @returns none 724 */ 725static int 726oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd) 727{ 728 int i = 0, j = 0, rc = 0; 729 uint8_t *tbl = fwcmd->params.req.cputable; |
730 struct oce_rq *rq = NULL; |
731 732 |
733 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) { 734 for_all_rss_queues(sc, rq, i) { 735 if ((j + i) >= INDIRECTION_TABLE_ENTRIES) 736 break; 737 tbl[j + i] = rq->rss_cpuid; |
738 } 739 } 740 if (i == 0) { 741 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n"); 742 rc = ENXIO; 743 744 } 745 --- 17 unchanged lines hidden (view full) --- 763 int rc; 764 struct oce_mbx mbx; 765 struct mbx_config_nic_rss *fwcmd = 766 (struct mbx_config_nic_rss *)&mbx.payload; 767 int version; 768 769 bzero(&mbx, sizeof(struct oce_mbx)); 770 |
771 if (IS_XE201(sc) || IS_SH(sc)) { |
772 version = OCE_MBX_VER_V1; 773 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 | 774 RSS_ENABLE_UDP_IPV6; 775 } else 776 version = OCE_MBX_VER_V0; 777 778 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 779 MBX_SUBSYSTEM_NIC, --- 891 unchanged lines hidden (view full) --- 1671 int rc = 0, version, num_pages; 1672 1673 bzero(&mbx, sizeof(struct oce_mbx)); 1674 1675 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload; 1676 if (IS_XE201(sc)) { 1677 version = OCE_MBX_VER_V1; 1678 fwcmd->params.req.if_id = sc->if_id; |
1679 } else if(IS_BE(sc)) 1680 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2) 1681 : (version = OCE_MBX_VER_V0); 1682 else 1683 version = OCE_MBX_VER_V2; |
1684 1685 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1686 MBX_SUBSYSTEM_NIC, 1687 NIC_CREATE_WQ, MBX_TIMEOUT_SEC, 1688 sizeof(struct mbx_create_nic_wq), 1689 version); 1690 1691 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]); --- 11 unchanged lines hidden (view full) --- 1703 if (!rc) 1704 rc = fwcmd->hdr.u0.rsp.status; 1705 if (rc) { 1706 device_printf(sc->dev,"%s failed - cmd status: %d\n", 1707 __FUNCTION__, rc); 1708 goto error; 1709 } 1710 wq->wq_id = LE_16(fwcmd->params.rsp.wq_id); |
1711 if (version == OCE_MBX_VER_V2) 1712 wq->db_offset = LE_32(fwcmd->params.rsp.db_offset); 1713 else 1714 wq->db_offset = PD_TXULP_DB; |
1715error: 1716 return rc; 1717 1718} 1719 1720 1721 1722int --- 155 unchanged lines hidden (view full) --- 1878 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1879 1880 fwcmd->params.req.port = LE_32(sc->port_id); 1881 fwcmd->params.req.page_num = LE_32(page_num); 1882 1883 /* command post */ 1884 rc = oce_mbox_post(sc, &mbx, NULL); 1885 if (!rc) |
1886 rc = fwcmd->hdr.u0.rsp.status; |
1887 if (rc) { 1888 device_printf(sc->dev,"%s failed - cmd status: %d\n", 1889 __FUNCTION__, rc); 1890 goto error; 1891 } 1892 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0) 1893 { 1894 bcopy((char *)fwcmd->params.rsp.page_data, 1895 (char *)&sfp_vpd_dump_buffer[0], 1896 TRANSCEIVER_A0_SIZE); 1897 } 1898 1899 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2) 1900 { 1901 bcopy((char *)fwcmd->params.rsp.page_data, 1902 (char *)&sfp_vpd_dump_buffer[32], 1903 TRANSCEIVER_A2_SIZE); 1904 } 1905error: |
1906 oce_dma_free(sc, &dma); |
1907 return rc; 1908} 1909 1910void 1911oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1912 int num) 1913{ 1914 struct oce_mbx mbx; --- 25 unchanged lines hidden (view full) --- 1940 htole32(set_eqd[i].delay_multiplier); 1941 } 1942 1943 1944 /* command post */ 1945 rc = oce_mbox_post(sc, &mbx, NULL); 1946 1947 if (!rc) |
1948 rc = fwcmd->hdr.u0.rsp.status; |
1949 if (rc) 1950 device_printf(sc->dev,"%s failed - cmd status: %d\n", 1951 __FUNCTION__, rc); 1952} 1953 |
1954int 1955oce_get_profile_config(POCE_SOFTC sc) 1956{ 1957 struct oce_mbx mbx; 1958 struct mbx_common_get_profile_config *fwcmd; 1959 int rc = 0; 1960 int version = 0; 1961 struct oce_mq_sge *sgl; 1962 OCE_DMA_MEM dma; 1963 uint32_t desc_count = 0; 1964 struct oce_nic_resc_desc *nic_desc = NULL; 1965 int i; 1966 boolean_t nic_desc_valid = FALSE; |
1967 |
1968 if (IS_BE2(sc)) 1969 return -1; 1970 1971 /* Allocate DMA mem*/ 1972 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config), 1973 &dma, 0)) 1974 return ENOMEM; 1975 1976 /* Initialize MODIFY_EQ_DELAY ioctl header */ 1977 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config); 1978 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config)); 1979 1980 if (IS_BE3(sc)) 1981 version = OCE_MBX_VER_V1; 1982 else 1983 version = OCE_MBX_VER_V0; 1984 1985 bzero(&mbx, sizeof(struct oce_mbx)); 1986 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1987 MBX_SUBSYSTEM_COMMON, 1988 OPCODE_COMMON_GET_PROFILE_CONFIG, 1989 MBX_TIMEOUT_SEC, 1990 sizeof(struct mbx_common_get_profile_config), 1991 version); 1992 /* fill rest of mbx */ 1993 mbx.u0.s.embedded = 0; 1994 mbx.payload_length = sizeof(struct mbx_common_get_profile_config); 1995 mbx.u0.s.sge_count = 1; 1996 sgl = &mbx.payload.u0.u1.sgl[0]; 1997 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 1998 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 1999 sgl->length = htole32(mbx.payload_length); 2000 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2001 2002 fwcmd->params.req.type = ACTIVE_PROFILE; 2003 2004 /* command post */ 2005 rc = oce_mbox_post(sc, &mbx, NULL); 2006 if (!rc) 2007 rc = fwcmd->hdr.u0.rsp.status; 2008 if (rc) { 2009 device_printf(sc->dev,"%s failed - cmd status: %d\n", 2010 __FUNCTION__, rc); 2011 goto error; 2012 } 2013 2014 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources; 2015 desc_count = HOST_32(fwcmd->params.rsp.desc_count); 2016 for (i = 0; i < desc_count; i++) { 2017 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) || 2018 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) { 2019 nic_desc_valid = TRUE; 2020 break; 2021 } 2022 nic_desc = (struct oce_nic_resc_desc *) \ 2023 ((char *)nic_desc + nic_desc->desc_len); 2024 } 2025 if (!nic_desc_valid) { 2026 rc = -1; 2027 goto error; 2028 } 2029 else { 2030 sc->nwqs = HOST_32(nic_desc->txq_count); 2031 if (sc->nwqs) 2032 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ); 2033 else 2034 sc->nwqs = OCE_MAX_WQ; 2035 2036 } 2037error: 2038 oce_dma_free(sc, &dma); 2039 return rc; 2040 2041} 2042 2043int 2044oce_get_func_config(POCE_SOFTC sc) 2045{ 2046 struct oce_mbx mbx; 2047 struct mbx_common_get_func_config *fwcmd; 2048 int rc = 0; 2049 int version = 0; 2050 struct oce_mq_sge *sgl; 2051 OCE_DMA_MEM dma; 2052 uint32_t desc_count = 0; 2053 struct oce_nic_resc_desc *nic_desc = NULL; 2054 int i; 2055 boolean_t nic_desc_valid = FALSE; 2056 uint32_t max_rss = 0; 2057 2058 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native)) 2059 max_rss = OCE_LEGACY_MODE_RSS; 2060 else 2061 max_rss = OCE_MAX_RSS; 2062 2063 /* Allocate DMA mem*/ 2064 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config), 2065 &dma, 0)) 2066 return ENOMEM; 2067 2068 /* Initialize MODIFY_EQ_DELAY ioctl header */ 2069 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config); 2070 bzero(fwcmd, sizeof(struct mbx_common_get_func_config)); 2071 2072 if (IS_SH(sc)) 2073 version = OCE_MBX_VER_V1; 2074 else 2075 version = OCE_MBX_VER_V0; 2076 2077 bzero(&mbx, sizeof(struct oce_mbx)); 2078 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2079 MBX_SUBSYSTEM_COMMON, 2080 OPCODE_COMMON_GET_FUNCTION_CONFIG, 2081 MBX_TIMEOUT_SEC, 2082 sizeof(struct mbx_common_get_func_config), 2083 version); 2084 /* fill rest of mbx */ 2085 mbx.u0.s.embedded = 0; 2086 mbx.payload_length = sizeof(struct mbx_common_get_func_config); 2087 mbx.u0.s.sge_count = 1; 2088 sgl = &mbx.payload.u0.u1.sgl[0]; 2089 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 2090 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 2091 sgl->length = htole32(mbx.payload_length); 2092 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2093 2094 /* command post */ 2095 rc = oce_mbox_post(sc, &mbx, NULL); 2096 if (!rc) 2097 rc = fwcmd->hdr.u0.rsp.status; 2098 if (rc) { 2099 device_printf(sc->dev,"%s failed - cmd status: %d\n", 2100 __FUNCTION__, rc); 2101 goto error; 2102 } 2103 2104 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources; 2105 desc_count = HOST_32(fwcmd->params.rsp.desc_count); 2106 for (i = 0; i < desc_count; i++) { 2107 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) || 2108 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) { 2109 nic_desc_valid = TRUE; 2110 break; 2111 } 2112 nic_desc = (struct oce_nic_resc_desc *) \ 2113 ((char *)nic_desc + nic_desc->desc_len); 2114 } 2115 if (!nic_desc_valid) { 2116 rc = -1; 2117 goto error; 2118 } 2119 else { 2120 sc->nwqs = HOST_32(nic_desc->txq_count); 2121 if (sc->nwqs) 2122 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ); 2123 else 2124 sc->nwqs = OCE_MAX_WQ; 2125 2126 sc->nrssqs = HOST_32(nic_desc->rssq_count); 2127 if (sc->nrssqs) 2128 sc->nrssqs = MIN(sc->nrssqs, max_rss); 2129 else 2130 sc->nrssqs = max_rss; 2131 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */; 2132 } 2133error: 2134 oce_dma_free(sc, &dma); 2135 return rc; 2136 2137} |