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< * Copyright (C) 2012 Emulex
---
> * Copyright (C) 2013 Emulex
41c41
< /* $FreeBSD: head/sys/dev/oce/oce_mbox.c 247880 2013-03-06 09:53:38Z delphij $ */
---
> /* $FreeBSD: head/sys/dev/oce/oce_mbox.c 252869 2013-07-06 08:30:45Z delphij $ */
729a730
> struct oce_rq *rq = NULL;
732,735c733,737
< for (j = 0; j < sc->nrqs; j++) {
< if (sc->rq[j]->cfg.is_rss_queue) {
< tbl[i] = sc->rq[j]->rss_cpuid;
< i = i + 1;
---
> for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) {
> for_all_rss_queues(sc, rq, i) {
> if ((j + i) >= INDIRECTION_TABLE_ENTRIES)
> break;
> tbl[j + i] = rq->rss_cpuid;
769c771
< if (IS_XE201(sc)) {
---
> if (IS_XE201(sc) || IS_SH(sc)) {
1677,1678c1679,1683
< } else
< version = OCE_MBX_VER_V0;
---
> } else if(IS_BE(sc))
> IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2)
> : (version = OCE_MBX_VER_V0);
> else
> version = OCE_MBX_VER_V2;
1705a1711,1714
> if (version == OCE_MBX_VER_V2)
> wq->db_offset = LE_32(fwcmd->params.rsp.db_offset);
> else
> wq->db_offset = PD_TXULP_DB;
1877c1886
< rc = fwcmd->hdr.u0.rsp.status;
---
> rc = fwcmd->hdr.u0.rsp.status;
1896a1906
> oce_dma_free(sc, &dma);
1938c1948
< rc = fwcmd->hdr.u0.rsp.status;
---
> rc = fwcmd->hdr.u0.rsp.status;
1943a1954,1966
> int
> oce_get_profile_config(POCE_SOFTC sc)
> {
> struct oce_mbx mbx;
> struct mbx_common_get_profile_config *fwcmd;
> int rc = 0;
> int version = 0;
> struct oce_mq_sge *sgl;
> OCE_DMA_MEM dma;
> uint32_t desc_count = 0;
> struct oce_nic_resc_desc *nic_desc = NULL;
> int i;
> boolean_t nic_desc_valid = FALSE;
1944a1968,2137
> if (IS_BE2(sc))
> return -1;
>
> /* Allocate DMA mem*/
> if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config),
> &dma, 0))
> return ENOMEM;
>
> /* Initialize MODIFY_EQ_DELAY ioctl header */
> fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config);
> bzero(fwcmd, sizeof(struct mbx_common_get_profile_config));
>
> if (IS_BE3(sc))
> version = OCE_MBX_VER_V1;
> else
> version = OCE_MBX_VER_V0;
>
> bzero(&mbx, sizeof(struct oce_mbx));
> mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
> MBX_SUBSYSTEM_COMMON,
> OPCODE_COMMON_GET_PROFILE_CONFIG,
> MBX_TIMEOUT_SEC,
> sizeof(struct mbx_common_get_profile_config),
> version);
> /* fill rest of mbx */
> mbx.u0.s.embedded = 0;
> mbx.payload_length = sizeof(struct mbx_common_get_profile_config);
> mbx.u0.s.sge_count = 1;
> sgl = &mbx.payload.u0.u1.sgl[0];
> sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
> sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
> sgl->length = htole32(mbx.payload_length);
> DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
>
> fwcmd->params.req.type = ACTIVE_PROFILE;
>
> /* command post */
> rc = oce_mbox_post(sc, &mbx, NULL);
> if (!rc)
> rc = fwcmd->hdr.u0.rsp.status;
> if (rc) {
> device_printf(sc->dev,"%s failed - cmd status: %d\n",
> __FUNCTION__, rc);
> goto error;
> }
>
> nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
> desc_count = HOST_32(fwcmd->params.rsp.desc_count);
> for (i = 0; i < desc_count; i++) {
> if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
> (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
> nic_desc_valid = TRUE;
> break;
> }
> nic_desc = (struct oce_nic_resc_desc *) \
> ((char *)nic_desc + nic_desc->desc_len);
> }
> if (!nic_desc_valid) {
> rc = -1;
> goto error;
> }
> else {
> sc->nwqs = HOST_32(nic_desc->txq_count);
> if (sc->nwqs)
> sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
> else
> sc->nwqs = OCE_MAX_WQ;
>
> }
> error:
> oce_dma_free(sc, &dma);
> return rc;
>
> }
>
> int
> oce_get_func_config(POCE_SOFTC sc)
> {
> struct oce_mbx mbx;
> struct mbx_common_get_func_config *fwcmd;
> int rc = 0;
> int version = 0;
> struct oce_mq_sge *sgl;
> OCE_DMA_MEM dma;
> uint32_t desc_count = 0;
> struct oce_nic_resc_desc *nic_desc = NULL;
> int i;
> boolean_t nic_desc_valid = FALSE;
> uint32_t max_rss = 0;
>
> if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
> max_rss = OCE_LEGACY_MODE_RSS;
> else
> max_rss = OCE_MAX_RSS;
>
> /* Allocate DMA mem*/
> if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config),
> &dma, 0))
> return ENOMEM;
>
> /* Initialize MODIFY_EQ_DELAY ioctl header */
> fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config);
> bzero(fwcmd, sizeof(struct mbx_common_get_func_config));
>
> if (IS_SH(sc))
> version = OCE_MBX_VER_V1;
> else
> version = OCE_MBX_VER_V0;
>
> bzero(&mbx, sizeof(struct oce_mbx));
> mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
> MBX_SUBSYSTEM_COMMON,
> OPCODE_COMMON_GET_FUNCTION_CONFIG,
> MBX_TIMEOUT_SEC,
> sizeof(struct mbx_common_get_func_config),
> version);
> /* fill rest of mbx */
> mbx.u0.s.embedded = 0;
> mbx.payload_length = sizeof(struct mbx_common_get_func_config);
> mbx.u0.s.sge_count = 1;
> sgl = &mbx.payload.u0.u1.sgl[0];
> sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
> sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
> sgl->length = htole32(mbx.payload_length);
> DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
>
> /* command post */
> rc = oce_mbox_post(sc, &mbx, NULL);
> if (!rc)
> rc = fwcmd->hdr.u0.rsp.status;
> if (rc) {
> device_printf(sc->dev,"%s failed - cmd status: %d\n",
> __FUNCTION__, rc);
> goto error;
> }
>
> nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
> desc_count = HOST_32(fwcmd->params.rsp.desc_count);
> for (i = 0; i < desc_count; i++) {
> if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
> (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
> nic_desc_valid = TRUE;
> break;
> }
> nic_desc = (struct oce_nic_resc_desc *) \
> ((char *)nic_desc + nic_desc->desc_len);
> }
> if (!nic_desc_valid) {
> rc = -1;
> goto error;
> }
> else {
> sc->nwqs = HOST_32(nic_desc->txq_count);
> if (sc->nwqs)
> sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
> else
> sc->nwqs = OCE_MAX_WQ;
>
> sc->nrssqs = HOST_32(nic_desc->rssq_count);
> if (sc->nrssqs)
> sc->nrssqs = MIN(sc->nrssqs, max_rss);
> else
> sc->nrssqs = max_rss;
> sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */;
> }
> error:
> oce_dma_free(sc, &dma);
> return rc;
>
> }