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oce_if.h (246799) oce_if.h (247880)
1/*-
2 * Copyright (C) 2012 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

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31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
1/*-
2 * Copyright (C) 2012 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

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31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39/* $FreeBSD: head/sys/dev/oce/oce_if.h 246799 2013-02-14 17:34:17Z jpaetzel $ */
40
39
40/* $FreeBSD: head/sys/dev/oce/oce_if.h 247880 2013-03-06 09:53:38Z delphij $ */
41
41#include <sys/param.h>
42#include <sys/endian.h>
43#include <sys/module.h>
44#include <sys/kernel.h>
45#include <sys/bus.h>
46#include <sys/mbuf.h>
47#include <sys/rman.h>
48#include <sys/socket.h>

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82#include <netinet/tcp.h>
83#include <netinet/sctp.h>
84#include <netinet/tcp_lro.h>
85
86#include <machine/bus.h>
87
88#include "oce_hw.h"
89
42#include <sys/param.h>
43#include <sys/endian.h>
44#include <sys/module.h>
45#include <sys/kernel.h>
46#include <sys/bus.h>
47#include <sys/mbuf.h>
48#include <sys/rman.h>
49#include <sys/socket.h>

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83#include <netinet/tcp.h>
84#include <netinet/sctp.h>
85#include <netinet/tcp_lro.h>
86
87#include <machine/bus.h>
88
89#include "oce_hw.h"
90
90/* OCE device driver module component revision informaiton */
91#define COMPONENT_REVISION "4.2.127.0"
91#define COMPONENT_REVISION "4.6.95.0"
92
92
93
94/* OCE devices supported by this driver */
95#define PCI_VENDOR_EMULEX 0x10df /* Emulex */
96#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */
97#define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */
98#define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */
99#define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */
100#define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */
101

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127#define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
128#define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */
129
130#define OCE_DEFAULT_WQ_EQD 16
131#define OCE_MAX_PACKET_Q 16
132#define OCE_RQ_BUF_SIZE 2048
133#define OCE_LSO_MAX_SIZE (64 * 1024)
134#define LONG_TIMEOUT 30
93/* OCE devices supported by this driver */
94#define PCI_VENDOR_EMULEX 0x10df /* Emulex */
95#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */
96#define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */
97#define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */
98#define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */
99#define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */
100

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126#define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
127#define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */
128
129#define OCE_DEFAULT_WQ_EQD 16
130#define OCE_MAX_PACKET_Q 16
131#define OCE_RQ_BUF_SIZE 2048
132#define OCE_LSO_MAX_SIZE (64 * 1024)
133#define LONG_TIMEOUT 30
135#define OCE_MAX_JUMBO_FRAME_SIZE 16360
134#define OCE_MAX_JUMBO_FRAME_SIZE 9018
136#define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \
137 ETHER_VLAN_ENCAP_LEN - \
138 ETHER_HDR_LEN)
139
140#define OCE_MAX_TX_ELEMENTS 29
141#define OCE_MAX_TX_DESC 1024
142#define OCE_MAX_TX_SIZE 65535
143#define OCE_MAX_RX_SIZE 4096

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476 struct oce_rx_stats rx;
477 struct oce_tx_stats tx;
478 union {
479 struct oce_be_stats be;
480 struct oce_xe201_stats xe201;
481 } u0;
482};
483
135#define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \
136 ETHER_VLAN_ENCAP_LEN - \
137 ETHER_HDR_LEN)
138
139#define OCE_MAX_TX_ELEMENTS 29
140#define OCE_MAX_TX_DESC 1024
141#define OCE_MAX_TX_SIZE 65535
142#define OCE_MAX_RX_SIZE 4096

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475 struct oce_rx_stats rx;
476 struct oce_tx_stats tx;
477 union {
478 struct oce_be_stats be;
479 struct oce_xe201_stats xe201;
480 } u0;
481};
482
483#define INTR_RATE_HWM 15000
484#define INTR_RATE_LWM 10000
484
485
486#define OCE_MAX_EQD 128u
487#define OCE_MIN_EQD 50u
485
488
489struct oce_set_eqd {
490 uint32_t eq_id;
491 uint32_t phase;
492 uint32_t delay_multiplier;
493};
494
495struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
496 boolean_t enable;
497 uint32_t min_eqd; /* in usecs */
498 uint32_t max_eqd; /* in usecs */
499 uint32_t cur_eqd; /* in usecs */
500 uint32_t et_eqd; /* configured value when aic is off */
501 uint64_t ticks;
502 uint64_t intr_prev;
503};
504
486#define MAX_LOCK_DESC_LEN 32
487struct oce_lock {
488 struct mtx mutex;
489 char name[MAX_LOCK_DESC_LEN+1];
490};
491#define OCE_LOCK struct oce_lock
492
493#define LOCK_CREATE(lock, desc) { \

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560 void *cb_context;
561 oce_ring_buffer_t *ring;
562 uint32_t ref_count;
563 qstate_t qstate;
564 struct oce_cq *cq[OCE_MAX_CQ_EQ];
565 int cq_valid;
566 struct eq_config eq_cfg;
567 int vector;
505#define MAX_LOCK_DESC_LEN 32
506struct oce_lock {
507 struct mtx mutex;
508 char name[MAX_LOCK_DESC_LEN+1];
509};
510#define OCE_LOCK struct oce_lock
511
512#define LOCK_CREATE(lock, desc) { \

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579 void *cb_context;
580 oce_ring_buffer_t *ring;
581 uint32_t ref_count;
582 qstate_t qstate;
583 struct oce_cq *cq[OCE_MAX_CQ_EQ];
584 int cq_valid;
585 struct eq_config eq_cfg;
586 int vector;
587 uint64_t intr;
568};
569
570enum cq_len {
571 CQ_LEN_256 = 256,
572 CQ_LEN_512 = 512,
573 CQ_LEN_1024 = 1024
574};
575

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822 uint32_t if_id; /* interface ID */
823 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */
824 uint32_t pmac_id; /* PMAC id */
825
826 uint32_t if_cap_flags;
827
828 uint32_t flow_control;
829 uint32_t promisc;
588};
589
590enum cq_len {
591 CQ_LEN_256 = 256,
592 CQ_LEN_512 = 512,
593 CQ_LEN_1024 = 1024
594};
595

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842 uint32_t if_id; /* interface ID */
843 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */
844 uint32_t pmac_id; /* PMAC id */
845
846 uint32_t if_cap_flags;
847
848 uint32_t flow_control;
849 uint32_t promisc;
850
851 struct oce_aic_obj aic_obj[OCE_MAX_EQ];
852
830 /*Vlan Filtering related */
831 eventhandler_tag vlan_attach;
832 eventhandler_tag vlan_detach;
833 uint16_t vlans_added;
834 uint8_t vlan_tag[MAX_VLANS];
835 /*stats */
836 OCE_DMA_MEM stats_mem;
837 struct oce_drv_stats oce_stats_info;
838 struct callout timer;
839 int8_t be3_native;
853 /*Vlan Filtering related */
854 eventhandler_tag vlan_attach;
855 eventhandler_tag vlan_detach;
856 uint16_t vlans_added;
857 uint8_t vlan_tag[MAX_VLANS];
858 /*stats */
859 OCE_DMA_MEM stats_mem;
860 struct oce_drv_stats oce_stats_info;
861 struct callout timer;
862 int8_t be3_native;
840 uint32_t pvid;
863 uint16_t qnq_debug_event;
864 uint16_t qnqid;
865 uint16_t pvid;
841
842} OCE_SOFTC, *POCE_SOFTC;
843
844
845
846/**************************************************
847 * BUS memory read/write macros
848 * BE3: accesses three BAR spaces (CFG, CSR, DB)

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991int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
992 uint32_t offset, uint32_t optype);
993int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
994int oce_mbox_create_rq(struct oce_rq *rq);
995int oce_mbox_create_wq(struct oce_wq *wq);
996int oce_mbox_create_eq(struct oce_eq *eq);
997int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
998 uint32_t is_eventable);
866
867} OCE_SOFTC, *POCE_SOFTC;
868
869
870
871/**************************************************
872 * BUS memory read/write macros
873 * BE3: accesses three BAR spaces (CFG, CSR, DB)

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1016int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1017 uint32_t offset, uint32_t optype);
1018int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
1019int oce_mbox_create_rq(struct oce_rq *rq);
1020int oce_mbox_create_wq(struct oce_wq *wq);
1021int oce_mbox_create_eq(struct oce_eq *eq);
1022int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
1023 uint32_t is_eventable);
1024int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
1025void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1026 int num);
999void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1000 uint8_t dom,
1001 uint8_t port,
1002 uint8_t subsys,
1003 uint8_t opcode,
1004 uint32_t timeout, uint32_t pyld_len,
1005 uint8_t version);
1006

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1071 }
1072
1073 if (c == 1)
1074 return b;
1075
1076 return 0;
1077}
1078
1027void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1028 uint8_t dom,
1029 uint8_t port,
1030 uint8_t subsys,
1031 uint8_t opcode,
1032 uint32_t timeout, uint32_t pyld_len,
1033 uint8_t version);
1034

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1099 }
1100
1101 if (c == 1)
1102 return b;
1103
1104 return 0;
1105}
1106
1107#define TRANSCEIVER_DATA_NUM_ELE 64
1108#define TRANSCEIVER_DATA_SIZE 256
1109#define TRANSCEIVER_A0_SIZE 128
1110#define TRANSCEIVER_A2_SIZE 128
1111#define PAGE_NUM_A0 0xa0
1112#define PAGE_NUM_A2 0xa2
1113#define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
1114 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
1115